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path: root/package/kernel/gpio-button-hotplug/src/gpio-button-hotplug.c
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/*
 *  GPIO Button Hotplug driver
 *
 *  Copyright (C) 2012 Felix Fietkau <nbd@nbd.name>
 *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
 *
 *  Based on the diag.c - GPIO interface driver for Broadcom boards
 *    Copyright (C) 2006 Mike Baker <mbm@openwrt.org>,
 *    Copyright (C) 2006-2007 Felix Fietkau <nbd@nbd.name>
 *    Copyright (C) 2008 Andy Boyett <agb@openwrt.org>
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License version 2 as published
 *  by the Free Software Foundation.
 */

#include <linux/module.h>
#include <linux/version.h>
#include <linux/kmod.h>

#include <linux/workqueue.h>
#include <linux/skbuff.h>
#include <linux/netlink.h>
#include <linux/kobject.h>
#include <linux/input.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/of_gpio.h>
#include <linux/of_irq.h>
#include <linux/gpio_keys.h>
#include <linux/gpio/consumer.h>

#define BH_SKB_SIZE	2048

#define DRV_NAME	"gpio-keys"
#define PFX	DRV_NAME ": "

struct bh_event {
	const char		*name;
	unsigned int		type;
	char			*action;
	unsigned long		seen;

	struct sk_buff		*skb;
	struct work_struct	work;
};

struct bh_map {
	unsigned int	code;
	const char	*name;
};

struct gpio_keys_button_data {
	struct delayed_work work;
	unsigned long seen;
	int map_entry;
	int last_state;
	int count;
	int threshold;
	int can_sleep;
	int irq;
	unsigned int software_debounce;
	struct gpio_desc *gpiod;
	const struct gpio_keys_button *b;
};

extern u64 uevent_next_seqnum(void);

#define BH_MAP(_code, _name)		\
	{				\
		.code = (_code),	\
		.name = (_name),	\
	}

static struct bh_map button_map[] = {
	BH_MAP(BTN_0,			"BTN_0"),
	BH_MAP(BTN_1,			"BTN_1"),
	BH_MAP(BTN_2,			"BTN_2"),
	BH_MAP(BTN_3,			"BTN_3"),
	BH_MAP(BTN_4,			"BTN_4"),
	BH_MAP(BTN_5,			"BTN_5"),
	BH_MAP(BTN_6,			"BTN_6"),
	BH_MAP(BTN_7,			"BTN_7"),
	BH_MAP(BTN_8,			"BTN_8"),
	BH_MAP(BTN_9,			"BTN_9"),
	BH_MAP(KEY_BRIGHTNESS_ZERO,	"brightness_zero"),
	BH_MAP(KEY_CONFIG,		"config"),
	BH_MAP(KEY_COPY,		"copy"),
	BH_MAP(KEY_EJECTCD,		"eject"),
	BH_MAP(KEY_HELP,		"help"),
	BH_MAP(KEY_LIGHTS_TOGGLE,	"lights_toggle"),
	BH_MAP(KEY_PHONE,		"phone"),
	BH_MAP(KEY_POWER,		"power"),
	BH_MAP(KEY_POWER2,		"reboot"),
	BH_MAP(KEY_RESTART,		"reset"),
	BH_MAP(KEY_RFKILL,		"rfkill"),
	BH_MAP(KEY_VIDEO,		"video"),
	BH_MAP(KEY_VOLUMEDOWN,		"volume_down"),
	BH_MAP(KEY_VOLUMEUP,		"volume_up"),
	BH_MAP(KEY_WIMAX,		"wwan"),
	BH_MAP(KEY_WLAN,		"wlan"),
	BH_MAP(KEY_WPS_BUTTON,		"wps"),
};

/* -------------------------------------------------------------------------*/

static __printf(3, 4)
int bh_event_add_var(struct bh_event *event, int argv, const char *format, ...)
{
	static char buf[128];
	char *s;
	va_list args;
	int len;

	if (argv)
		return 0;

	va_start(args, format);
	len = vsnprintf(buf, sizeof(buf), format, args);
	va_end(args);

	if (len >= sizeof(buf)) {
		WARN(1, "buffer size too small");
		return -ENOMEM;
	}

	s = skb_put(event->skb, len + 1);
	strcpy(s, buf);

	pr_debug(PFX "added variable '%s'\n", s);

	return 0;
}

static int button_hotplug_fill_event(struct bh_event *event)
{
	int ret;

	ret = bh_event_add_var(event, 0, "HOME=%s", "/");
	if (ret)
		return ret;

	ret = bh_event_add_var(event, 0, "PATH=%s",
					"/sbin:/bin:/usr/sbin:/usr/bin");
	if (ret)
		return ret;

	ret = bh_event_add_var(event, 0, "SUBSYSTEM=%s", "button");
	if (ret)
		return ret;

	ret = bh_event_add_var(event, 0, "ACTION=%s", event->action);
	if (ret)
		return ret;

	ret = bh_event_add_var(event, 0, "BUTTON=%s", event->name);
	if (ret)
		return ret;

	if (event->type == EV_SW) {
		ret = bh_event_add_var(event, 0, "TYPE=%s", "switch");
		if (ret)
			return ret;
	}

	ret = bh_event_add_var(event, 0, "SEEN=%ld", event->seen);
	if (ret)
		return ret;

	ret = bh_event_add_var(event, 0, "SEQNUM=%llu", uevent_next_seqnum());

	return ret;
}

static void button_hotplug_work(struct work_struct *work)
{
	struct bh_event *event = container_of(work, struct bh_event, work);
	int ret = 0;

	event->skb = alloc_skb(BH_SKB_SIZE, GFP_KERNEL);
	if (!event->skb)
		goto out_free_event;

	ret = bh_event_add_var(event, 0, "%s@", event->action);
	if (ret)
		goto out_free_skb;

	ret = button_hotplug_fill_event(event);
	if (ret)
		goto out_free_skb;

	NETLINK_CB(event->skb).dst_group = 1;
	broadcast_uevent(event->skb, 0, 1, GFP_KERNEL);

 out_free_skb:
	if (ret) {
		pr_err(PFX "work error %d\n", ret);
		kfree_skb(event->skb);
	}
 out_free_event:
	kfree(event);
}

static int button_hotplug_create_event(const char *name, unsigned int type,
		unsigned long seen, int pressed)
{
	struct bh_event *event;

	pr_debug(PFX "create event, name=%s, seen=%lu, pressed=%d\n",
		 name, seen, pressed);

	event = kzalloc(sizeof(*event), GFP_KERNEL);
	if (!event)
		return -ENOMEM;

	event->name = name;
	event->type = type;
	event->seen = seen;
	event->action = pressed ? "pressed" : "released";

	INIT_WORK(&event->work, (void *)(void *)button_hotplug_work);
	schedule_work(&event->work);

	return 0;
}

/* -------------------------------------------------------------------------*/

static int button_get_index(unsigned int code)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(button_map); i++)
		if (button_map[i].code == code)
			return i;

	return -1;
}

static int gpio_button_get_value(struct gpio_keys_button_data *bdata)
{
	int val;

	if (bdata->can_sleep)
		val = !!gpiod_get_value_cansleep(bdata->gpiod);
	else
		val = !!gpiod_get_value(bdata->gpiod);

	return val;
}

static void gpio_keys_handle_button(struct gpio_keys_button_data *bdata)
{
	unsigned int type = bdata->b->type ?: EV_KEY;
	int state = gpio_button_get_value(bdata);
	unsigned long seen = jiffies;

	pr_debug(PFX "event type=%u, code=%u, pressed=%d\n",
		 type, bdata->b->code, state);

	/* is this the initialization state? */
	if (bdata->last_state == -1) {
		/*
		 * Don't advertise unpressed buttons on initialization.
		 * Just save their state and continue otherwise this
		 * can cause OpenWrt to enter failsafe.
		 */
		if (type == EV_KEY && state == 0)
			goto set_state;
		/*
		 * But we are very interested in pressed buttons and
		 * initial switch state. These will be reported to
		 * userland.
		 */
	} else if (bdata->last_state == state) {
		/* reset asserted counter (only relevant for polled keys) */
		bdata->count = 0;
		return;
	}

	if (bdata->count < bdata->threshold) {
		bdata->count++;
		return;
	}

	if (bdata->seen == 0)
		bdata->seen = seen;

	button_hotplug_create_event(button_map[bdata->map_entry].name, type,
				    (seen - bdata->seen) / HZ, state);
	bdata->seen = seen;

set_state:
	bdata->last_state = state;
	bdata->count = 0;
}

struct gpio_keys_button_dev {
	int polled;
	struct delayed_work work;

	struct device *dev;
	struct gpio_keys_platform_data *pdata;
	struct gpio_keys_button_data data[0];
};

static void gpio_keys_polled_queue_work(struct gpio_keys_button_dev *bdev)
{
	struct gpio_keys_platform_data *pdata = bdev->pdata;
	unsigned long delay = msecs_to_jiffies(pdata->poll_interval);

	if (delay >= HZ)
		delay = round_jiffies_relative(delay);
	schedule_delayed_work(&bdev->work, delay);
}

static void gpio_keys_polled_poll(struct work_struct *work)
{
	struct gpio_keys_button_dev *bdev =
		container_of(work, struct gpio_keys_button_dev, work.work);
	int i;

	for (i = 0; i < bdev->pdata->nbuttons; i++) {
		struct gpio_keys_button_data *bdata = &bdev->data[i];

		if (bdata->gpiod)
			gpio_keys_handle_button(bdata);
	}
	gpio_keys_polled_queue_work(bdev);
}

static void gpio_keys_polled_close(struct gpio_keys_button_dev *bdev)
{
	struct gpio_keys_platform_data *pdata = bdev->pdata;

	cancel_delayed_work_sync(&bdev->work);

	if (pdata->disable)
		pdata->disable(bdev->dev);
}

static void gpio_keys_irq_work_func(struct work_struct *work)
{
	struct gpio_keys_button_data *bdata = container_of(work,
		struct gpio_keys_button_data, work.work);

	gpio_keys_handle_button(bdata);
}

static irqreturn_t button_handle_irq(int irq, void *_bdata)
{
	struct gpio_keys_button_data *bdata =
		(struct gpio_keys_button_data *) _bdata;

	mod_delayed_work(system_wq, &bdata->work,
			 msecs_to_jiffies(bdata->software_debounce));

	return IRQ_HANDLED;
}

#ifdef CONFIG_OF
static struct gpio_keys_platform_data *
gpio_keys_get_devtree_pdata(struct device *dev)
{
	struct device_node *node, *pp;
	struct gpio_keys_platform_data *pdata;
	struct gpio_keys_button *button;
	int nbuttons;
	int i = 0;

	node = dev->of_node;
	if (!node)
		return NULL;

	nbuttons = of_get_child_count(node);
	if (nbuttons == 0)
		return ERR_PTR(-EINVAL);

	pdata = devm_kzalloc(dev, sizeof(*pdata) + nbuttons * (sizeof *button),
		GFP_KERNEL);
	if (!pdata)
		return ERR_PTR(-ENOMEM);

	pdata->buttons = (struct gpio_keys_button *)(pdata + 1);
	pdata->nbuttons = nbuttons;

	pdata->rep = !!of_get_property(node, "autorepeat", NULL);
	of_property_read_u32(node, "poll-interval", &pdata->poll_interval);

	for_each_child_of_node(node, pp) {
		button = (struct gpio_keys_button *)(&pdata->buttons[i++]);

		if (of_property_read_u32(pp, "linux,code", &button->code)) {
			dev_err(dev, "Button node '%s' without keycode\n",
				pp->full_name);
			of_node_put(pp);
			return ERR_PTR(-EINVAL);
		}

		button->desc = of_get_property(pp, "label", NULL);

		if (of_property_read_u32(pp, "linux,input-type", &button->type))
			button->type = EV_KEY;

		button->wakeup = !!of_get_property(pp, "gpio-key,wakeup", NULL);

		if (of_property_read_u32(pp, "debounce-interval",
					&button->debounce_interval))
			button->debounce_interval = 5;

		button->irq = irq_of_parse_and_map(pp, 0);
		button->gpio = -ENOENT; /* mark this as device-tree */
	}

	return pdata;
}

static struct of_device_id gpio_keys_of_match[] = {
	{ .compatible = "gpio-keys", },
	{ },
};
MODULE_DEVICE_TABLE(of, gpio_keys_of_match);

static struct of_device_id gpio_keys_polled_of_match[] = {
	{ .compatible = "gpio-keys-polled", },
	{ },
};
MODULE_DEVICE_TABLE(of, gpio_keys_polled_of_match);

#else

static inline struct gpio_keys_platform_data *
gpio_keys_get_devtree_pdata(struct device *dev)
{
	return NULL;
}
#endif

static int gpio_keys_button_probe(struct platform_device *pdev,
		struct gpio_keys_button_dev **_bdev, int polled)
{
	struct device *dev = &pdev->dev;
	struct gpio_keys_platform_data *pdata = dev_get_platdata(dev);
	struct gpio_keys_button_dev *bdev;
	struct gpio_keys_button *buttons;
	struct device_node *prev = NULL;
	int error = 0;
	int i;

	if (!pdata) {
		pdata = gpio_keys_get_devtree_pdata(dev);
		if (IS_ERR(pdata))
			return PTR_ERR(pdata);
		if (!pdata) {
			dev_err(dev, "missing platform data\n");
			return -EINVAL;
		}
	}

	if (polled && !pdata->poll_interval) {
		dev_err(dev, "missing poll_interval value\n");
		return -EINVAL;
	}

	buttons = devm_kzalloc(dev, pdata->nbuttons * sizeof(struct gpio_keys_button),
		       GFP_KERNEL);
	if (!buttons) {
		dev_err(dev, "no memory for button data\n");
		return -ENOMEM;
	}
	memcpy(buttons, pdata->buttons, pdata->nbuttons * sizeof(struct gpio_keys_button));

	bdev = devm_kzalloc(dev, sizeof(struct gpio_keys_button_dev) +
		       pdata->nbuttons * sizeof(struct gpio_keys_button_data),
		       GFP_KERNEL);
	if (!bdev) {
		dev_err(dev, "no memory for private data\n");
		return -ENOMEM;
	}

	bdev->polled = polled;

	for (i = 0; i < pdata->nbuttons; i++) {
		struct gpio_keys_button *button = &buttons[i];
		struct gpio_keys_button_data *bdata = &bdev->data[i];
		const char *desc = button->desc ? button->desc : DRV_NAME;

		if (button->wakeup) {
			dev_err(dev, "does not support wakeup\n");
			error = -EINVAL;
			goto out;
		}

		bdata->map_entry = button_get_index(button->code);
		if (bdata->map_entry < 0) {
			dev_err(dev, "does not support key code:%u\n",
				button->code);
			error = -EINVAL;
			goto out;
		}

		if (!(button->type == 0 || button->type == EV_KEY ||
		      button->type == EV_SW)) {
			dev_err(dev, "only supports buttons or switches\n");
			error = -EINVAL;
			goto out;
		}

		if (gpio_is_valid(button->gpio)) {
			/* legacy platform data... but is it the lookup table? */
			bdata->gpiod = devm_gpiod_get_index(dev, desc, i,
							    GPIOD_IN);
			if (IS_ERR(bdata->gpiod)) {
				/* or the legacy (button->gpio is good) way? */
				error = devm_gpio_request_one(dev,
					button->gpio, GPIOF_IN | (
					button->active_low ? GPIOF_ACTIVE_LOW :
					0), desc);
				if (error) {
					if (error != -EPROBE_DEFER) {
						dev_err(dev, "unable to claim gpio %d, err=%d\n",
							button->gpio, error);
					}
					goto out;
				}

				bdata->gpiod = gpio_to_desc(button->gpio);
			}
		} else {
			/* Device-tree */
			struct device_node *child =
				of_get_next_child(dev->of_node, prev);

			bdata->gpiod = devm_gpiod_get_from_of_node(dev,
				child, "gpios", 0, GPIOD_IN, desc);

			prev = child;
		}

		if (IS_ERR_OR_NULL(bdata->gpiod)) {
			error = IS_ERR(bdata->gpiod) ? PTR_ERR(bdata->gpiod) :
				-EINVAL;
			goto out;
		}

		bdata->can_sleep = gpiod_cansleep(bdata->gpiod);
		bdata->last_state = -1; /* Unknown state on boot */

		if (bdev->polled) {
			bdata->threshold = DIV_ROUND_UP(button->debounce_interval,
							pdata->poll_interval);
		} else {
			/* bdata->threshold = 0; already initialized */

			if (button->debounce_interval) {
				error = gpiod_set_debounce(bdata->gpiod,
					button->debounce_interval * 1000);
				/*
				 * use timer if gpiolib doesn't provide
				 * debounce.
				 */
				if (error < 0) {
					bdata->software_debounce =
						button->debounce_interval;
				}
			}
		}

		bdata->b = &pdata->buttons[i];
	}

	bdev->dev = &pdev->dev;
	bdev->pdata = pdata;
	platform_set_drvdata(pdev, bdev);

	*_bdev = bdev;
	error = 0;

out:
	of_node_put(prev);
	return error;
}

static int gpio_keys_probe(struct platform_device *pdev)
{
	struct gpio_keys_platform_data *pdata;
	struct gpio_keys_button_dev *bdev;
	int ret, i;

	ret = gpio_keys_button_probe(pdev, &bdev, 0);
	if (ret)
		return ret;

	pdata = bdev->pdata;
	for (i = 0; i < pdata->nbuttons; i++) {
		const struct gpio_keys_button *button = &pdata->buttons[i];
		struct gpio_keys_button_data *bdata = &bdev->data[i];
		unsigned long irqflags = IRQF_ONESHOT;

		INIT_DELAYED_WORK(&bdata->work, gpio_keys_irq_work_func);

		if (!button->irq) {
			bdata->irq = gpiod_to_irq(bdata->gpiod);
			if (bdata->irq < 0) {
				dev_err(&pdev->dev, "failed to get irq for gpio:%d\n",
					button->gpio);
				continue;
			}

			irqflags |= IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING;
		} else {
			bdata->irq = button->irq;
		}

		schedule_delayed_work(&bdata->work,
				      msecs_to_jiffies(bdata->software_debounce));

		ret = devm_request_threaded_irq(&pdev->dev,
			bdata->irq, NULL, button_handle_irq,
			irqflags, dev_name(&pdev->dev), bdata);
		if (ret < 0) {
			bdata->irq = 0;
			dev_err(&pdev->dev, "failed to request irq:%d for gpio:%d\n",
				bdata->irq, button->gpio);
			continue;
		} else {
			dev_dbg(&pdev->dev, "gpio:%d has irq:%d\n",
				button->gpio, bdata->irq);
		}
	}

	return 0;
}

static int gpio_keys_polled_probe(struct platform_device *pdev)
{
	struct gpio_keys_platform_data *pdata;
	struct gpio_keys_button_dev *bdev;
	int ret;

	ret = gpio_keys_button_probe(pdev, &bdev, 1);
	if (ret)
		return ret;

	INIT_DELAYED_WORK(&bdev->work, gpio_keys_polled_poll);

	pdata = bdev->pdata;
	if (pdata->enable)
		pdata->enable(bdev->dev);

	gpio_keys_polled_queue_work(bdev);

	return ret;
}

static void gpio_keys_irq_close(struct gpio_keys_button_dev *bdev)
{
	struct gpio_keys_platform_data *pdata = bdev->pdata;
	size_t i;

	for (i = 0; i < pdata->nbuttons; i++) {
		struct gpio_keys_button_data *bdata = &bdev->data[i];

		disable_irq(bdata->irq);
		cancel_delayed_work_sync(&bdata->work);
	}
}

static int gpio_keys_remove(struct platform_device *pdev)
{
	struct gpio_keys_button_dev *bdev = platform_get_drvdata(pdev);

	platform_set_drvdata(pdev, NULL);

	if (bdev->polled)
		gpio_keys_polled_close(bdev);
	else
		gpio_keys_irq_close(bdev);

	return 0;
}

static struct platform_driver gpio_keys_driver = {
	.probe	= gpio_keys_probe,
	.remove	= gpio_keys_remove,
	.driver	= {
		.name	= "gpio-keys",
		.owner	= THIS_MODULE,
		.of_match_table = of_match_ptr(gpio_keys_of_match),
	},
};

static struct platform_driver gpio_keys_polled_driver = {
	.probe	= gpio_keys_polled_probe,
	.remove	= gpio_keys_remove,
	.driver	= {
		.name	= "gpio-keys-polled",
		.owner	= THIS_MODULE,
		.of_match_table = of_match_ptr(gpio_keys_polled_of_match),
	},
};

static int __init gpio_button_init(void)
{
	int ret;

	ret = platform_driver_register(&gpio_keys_driver);
	if (ret)
		return ret;

	ret = platform_driver_register(&gpio_keys_polled_driver);
	if (ret)
		platform_driver_unregister(&gpio_keys_driver);

	return ret;
}

static void __exit gpio_button_exit(void)
{
	platform_driver_unregister(&gpio_keys_driver);
	platform_driver_unregister(&gpio_keys_polled_driver);
}

module_init(gpio_button_init);
module_exit(gpio_button_exit);

MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
MODULE_AUTHOR("Felix Fietkau <nbd@nbd.name>");
MODULE_DESCRIPTION("Polled GPIO Buttons hotplug driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:" DRV_NAME);
n class="n">F( 99); F(100); F(101); F(102); F(103); F(104); F(105); F(106); F(107); F(108); F(109); F(110); F(111); F(112); F(113); F(114); F(115); F(116); F(117); F(118); F(119); F(120); F(121); F(122); F(123); F(124); F(125); F(126); F(127); } # undef F } #endif /* XEN */ static inline unsigned long rotate_reg (unsigned long sor, unsigned long rrb, unsigned long reg) { reg += rrb; if (reg >= sor) reg -= sor; return reg; } #if defined(XEN) void set_rse_reg (struct pt_regs *regs, unsigned long r1, unsigned long val, unsigned long nat) { unsigned long *bsp, *bspstore, *addr, *rnat_addr; unsigned long *kbs = (void *) current + IA64_RBS_OFFSET; unsigned long nat_mask; unsigned long old_rsc, new_rsc, psr; unsigned long rnat; long sof = (regs->cr_ifs) & 0x7f; long sor = 8 * ((regs->cr_ifs >> 14) & 0xf); long rrb_gr = (regs->cr_ifs >> 18) & 0x7f; long ridx = r1 - 32; if (ridx >= sof) { /* this should never happen, as the "rsvd register fault" has higher priority */ DPRINT("ignoring write to r%lu; only %lu registers are allocated!\n", r1, sof); return; } if (ridx < sor) ridx = rotate_reg(sor, rrb_gr, ridx); old_rsc=ia64_get_rsc(); /* put RSC to lazy mode, and set loadrs 0 */ new_rsc = old_rsc & (~0x3fff0003); ia64_set_rsc(new_rsc); bsp = kbs + (regs->loadrs >> 19); /* 16 + 3 */ addr = ia64_rse_skip_regs(bsp, -sof + ridx); nat_mask = 1UL << ia64_rse_slot_num(addr); rnat_addr = ia64_rse_rnat_addr(addr); local_irq_save(psr); bspstore = (unsigned long*)ia64_get_bspstore(); if(addr >= bspstore){ ia64_flushrs (); ia64_mf (); *addr = val; bspstore = (unsigned long*)ia64_get_bspstore(); rnat = ia64_get_rnat (); if(bspstore < rnat_addr){ rnat=rnat&(~nat_mask); }else{ *rnat_addr = (*rnat_addr)&(~nat_mask); } ia64_mf(); ia64_loadrs(); ia64_set_rnat(rnat); }else{ rnat = ia64_get_rnat (); *addr = val; if(bspstore < rnat_addr){ rnat=rnat&(~nat_mask); }else{ *rnat_addr = (*rnat_addr)&(~nat_mask); } ia64_set_bspstore (bspstore); ia64_set_rnat(rnat); } local_irq_restore(psr); ia64_set_rsc(old_rsc); } static void get_rse_reg (struct pt_regs *regs, unsigned long r1, unsigned long *val, int*nat) { unsigned long *bsp, *addr, *rnat_addr, *bspstore; unsigned long *kbs = (void *) current + IA64_RBS_OFFSET; unsigned long nat_mask; unsigned long old_rsc, new_rsc; long sof = (regs->cr_ifs) & 0x7f; long sor = 8 * ((regs->cr_ifs >> 14) & 0xf); long rrb_gr = (regs->cr_ifs >> 18) & 0x7f; long ridx = r1 - 32; if (ridx >= sof) { /* read of out-of-frame register returns an undefined value; 0 in our case. */ DPRINT("ignoring read from r%lu; only %lu registers are allocated!\n", r1, sof); panic("wrong stack register number (iip=%lx)\n", regs->cr_iip); } if (ridx < sor) ridx = rotate_reg(sor, rrb_gr, ridx); old_rsc=ia64_get_rsc(); new_rsc=old_rsc&(~(0x3)); ia64_set_rsc(new_rsc); bspstore = (unsigned long*)ia64_get_bspstore(); bsp =kbs + (regs->loadrs >> 19); //16+3; addr = ia64_rse_skip_regs(bsp, -sof + ridx); nat_mask = 1UL << ia64_rse_slot_num(addr); rnat_addr = ia64_rse_rnat_addr(addr); if(addr >= bspstore){ ia64_flushrs (); ia64_mf (); bspstore = (unsigned long*)ia64_get_bspstore(); } *val=*addr; if(nat){ if(bspstore < rnat_addr){ *nat=(int)!!(ia64_get_rnat()&nat_mask); }else{ *nat = (int)!!((*rnat_addr)&nat_mask); } ia64_set_rsc(old_rsc); } } #else static void set_rse_reg (struct pt_regs *regs, unsigned long r1, unsigned long val, int nat) { struct switch_stack *sw = (struct switch_stack *) regs - 1; unsigned long *bsp, *bspstore, *addr, *rnat_addr, *ubs_end; unsigned long *kbs = (void *) current + IA64_RBS_OFFSET; unsigned long rnats, nat_mask; unsigned long on_kbs; long sof = (regs->cr_ifs) & 0x7f; long sor = 8 * ((regs->cr_ifs >> 14) & 0xf); long rrb_gr = (regs->cr_ifs >> 18) & 0x7f; long ridx = r1 - 32; if (ridx >= sof) { /* this should never happen, as the "rsvd register fault" has higher priority */ DPRINT("ignoring write to r%lu; only %lu registers are allocated!\n", r1, sof); return; } if (ridx < sor) ridx = rotate_reg(sor, rrb_gr, ridx); DPRINT("r%lu, sw.bspstore=%lx pt.bspstore=%lx sof=%ld sol=%ld ridx=%ld\n", r1, sw->ar_bspstore, regs->ar_bspstore, sof, (regs->cr_ifs >> 7) & 0x7f, ridx); on_kbs = ia64_rse_num_regs(kbs, (unsigned long *) sw->ar_bspstore); addr = ia64_rse_skip_regs((unsigned long *) sw->ar_bspstore, -sof + ridx); if (addr >= kbs) { /* the register is on the kernel backing store: easy... */ rnat_addr = ia64_rse_rnat_addr(addr); if ((unsigned long) rnat_addr >= sw->ar_bspstore) rnat_addr = &sw->ar_rnat; nat_mask = 1UL << ia64_rse_slot_num(addr); *addr = val; if (nat) *rnat_addr |= nat_mask; else *rnat_addr &= ~nat_mask; return; } if (!user_stack(current, regs)) { DPRINT("ignoring kernel write to r%lu; register isn't on the kernel RBS!", r1); return; } bspstore = (unsigned long *)regs->ar_bspstore; ubs_end = ia64_rse_skip_regs(bspstore, on_kbs); bsp = ia64_rse_skip_regs(ubs_end, -sof); addr = ia64_rse_skip_regs(bsp, ridx); DPRINT("ubs_end=%p bsp=%p addr=%p\n", (void *) ubs_end, (void *) bsp, (void *) addr); ia64_poke(current, sw, (unsigned long) ubs_end, (unsigned long) addr, val); rnat_addr = ia64_rse_rnat_addr(addr); ia64_peek(current, sw, (unsigned long) ubs_end, (unsigned long) rnat_addr, &rnats); DPRINT("rnat @%p = 0x%lx nat=%d old nat=%ld\n", (void *) rnat_addr, rnats, nat, (rnats >> ia64_rse_slot_num(addr)) & 1); nat_mask = 1UL << ia64_rse_slot_num(addr); if (nat) rnats |= nat_mask; else rnats &= ~nat_mask; ia64_poke(current, sw, (unsigned long) ubs_end, (unsigned long) rnat_addr, rnats); DPRINT("rnat changed to @%p = 0x%lx\n", (void *) rnat_addr, rnats); } static void get_rse_reg (struct pt_regs *regs, unsigned long r1, unsigned long *val, int *nat) { struct switch_stack *sw = (struct switch_stack *) regs - 1; unsigned long *bsp, *addr, *rnat_addr, *ubs_end, *bspstore; unsigned long *kbs = (void *) current + IA64_RBS_OFFSET; unsigned long rnats, nat_mask; unsigned long on_kbs; long sof = (regs->cr_ifs) & 0x7f; long sor = 8 * ((regs->cr_ifs >> 14) & 0xf); long rrb_gr = (regs->cr_ifs >> 18) & 0x7f; long ridx = r1 - 32; if (ridx >= sof) { /* read of out-of-frame register returns an undefined value; 0 in our case. */ DPRINT("ignoring read from r%lu; only %lu registers are allocated!\n", r1, sof); goto fail; } if (ridx < sor) ridx = rotate_reg(sor, rrb_gr, ridx); DPRINT("r%lu, sw.bspstore=%lx pt.bspstore=%lx sof=%ld sol=%ld ridx=%ld\n", r1, sw->ar_bspstore, regs->ar_bspstore, sof, (regs->cr_ifs >> 7) & 0x7f, ridx); on_kbs = ia64_rse_num_regs(kbs, (unsigned long *) sw->ar_bspstore); addr = ia64_rse_skip_regs((unsigned long *) sw->ar_bspstore, -sof + ridx); if (addr >= kbs) { /* the register is on the kernel backing store: easy... */ *val = *addr; if (nat) { rnat_addr = ia64_rse_rnat_addr(addr); if ((unsigned long) rnat_addr >= sw->ar_bspstore) rnat_addr = &sw->ar_rnat; nat_mask = 1UL << ia64_rse_slot_num(addr); *nat = (*rnat_addr & nat_mask) != 0; } return; } if (!user_stack(current, regs)) { DPRINT("ignoring kernel read of r%lu; register isn't on the RBS!", r1); goto fail; } bspstore = (unsigned long *)regs->ar_bspstore; ubs_end = ia64_rse_skip_regs(bspstore, on_kbs); bsp = ia64_rse_skip_regs(ubs_end, -sof); addr = ia64_rse_skip_regs(bsp, ridx); DPRINT("ubs_end=%p bsp=%p addr=%p\n", (void *) ubs_end, (void *) bsp, (void *) addr); ia64_peek(current, sw, (unsigned long) ubs_end, (unsigned long) addr, val); if (nat) { rnat_addr = ia64_rse_rnat_addr(addr); nat_mask = 1UL << ia64_rse_slot_num(addr); DPRINT("rnat @%p = 0x%lx\n", (void *) rnat_addr, rnats); ia64_peek(current, sw, (unsigned long) ubs_end, (unsigned long) rnat_addr, &rnats); *nat = (rnats & nat_mask) != 0; } return; fail: *val = 0; if (nat) *nat = 0; return; } #endif #ifdef XEN void #else static void #endif setreg (unsigned long regnum, unsigned long val, int nat, struct pt_regs *regs) { struct switch_stack *sw = (struct switch_stack *) regs - 1; unsigned long addr; unsigned long bitmask; unsigned long *unat; /* * First takes care of stacked registers */ if (regnum >= IA64_FIRST_STACKED_GR) { set_rse_reg(regs, regnum, val, nat); return; } /* * Using r0 as a target raises a General Exception fault which has higher priority * than the Unaligned Reference fault. */ /* * Now look at registers in [0-31] range and init correct UNAT */ if (GR_IN_SW(regnum)) { addr = (unsigned long)sw; unat = &sw->ar_unat; } else { addr = (unsigned long)regs; #if defined(XEN) unat = &regs->eml_unat; #else unat = &sw->caller_unat; #endif } DPRINT("tmp_base=%lx switch_stack=%s offset=%d\n", addr, unat==&sw->ar_unat ? "yes":"no", GR_OFFS(regnum)); /* * add offset from base of struct * and do it ! */ addr += GR_OFFS(regnum); *(unsigned long *)addr = val; /* * We need to clear the corresponding UNAT bit to fully emulate the load * UNAT bit_pos = GR[r3]{8:3} form EAS-2.4 */ bitmask = 1UL << (addr >> 3 & 0x3f); DPRINT("*0x%lx=0x%lx NaT=%d prev_unat @%p=%lx\n", addr, val, nat, (void *) unat, *unat); if (nat) { *unat |= bitmask; } else { *unat &= ~bitmask; } DPRINT("*0x%lx=0x%lx NaT=%d new unat: %p=%lx\n", addr, val, nat, (void *) unat,*unat); } /* * Return the (rotated) index for floating point register REGNUM (REGNUM must be in the * range from 32-127, result is in the range from 0-95. */ static inline unsigned long fph_index (struct pt_regs *regs, long regnum) { unsigned long rrb_fr = (regs->cr_ifs >> 25) & 0x7f; return rotate_reg(96, rrb_fr, (regnum - IA64_FIRST_ROTATING_FR)); } #ifndef XEN static void setfpreg (unsigned long regnum, struct ia64_fpreg *fpval, struct pt_regs *regs) { struct switch_stack *sw = (struct switch_stack *)regs - 1; unsigned long addr; /* * From EAS-2.5: FPDisableFault has higher priority than Unaligned * Fault. Thus, when we get here, we know the partition is enabled. * To update f32-f127, there are three choices: * * (1) save f32-f127 to thread.fph and update the values there * (2) use a gigantic switch statement to directly access the registers * (3) generate code on the fly to update the desired register * * For now, we are using approach (1). */ if (regnum >= IA64_FIRST_ROTATING_FR) { ia64_sync_fph(current); #ifdef XEN current->arch._thread.fph[fph_index(regs, regnum)] = *fpval; #else current->thread.fph[fph_index(regs, regnum)] = *fpval; #endif } else { /* * pt_regs or switch_stack ? */ if (FR_IN_SW(regnum)) { addr = (unsigned long)sw; } else { addr = (unsigned long)regs; } DPRINT("tmp_base=%lx offset=%d\n", addr, FR_OFFS(regnum)); addr += FR_OFFS(regnum); *(struct ia64_fpreg *)addr = *fpval; /* * mark the low partition as being used now * * It is highly unlikely that this bit is not already set, but * let's do it for safety. */ regs->cr_ipsr |= IA64_PSR_MFL; } } #endif /* XEN */ /* * Those 2 inline functions generate the spilled versions of the constant floating point * registers which can be used with stfX */ static inline void float_spill_f0 (struct ia64_fpreg *final) { ia64_stf_spill(final, 0); } static inline void float_spill_f1 (struct ia64_fpreg *final) { ia64_stf_spill(final, 1); } #ifndef XEN static void getfpreg (unsigned long regnum, struct ia64_fpreg *fpval, struct pt_regs *regs) { struct switch_stack *sw = (struct switch_stack *) regs - 1; unsigned long addr; /* * From EAS-2.5: FPDisableFault has higher priority than * Unaligned Fault. Thus, when we get here, we know the partition is * enabled. * * When regnum > 31, the register is still live and we need to force a save * to current->thread.fph to get access to it. See discussion in setfpreg() * for reasons and other ways of doing this. */ if (regnum >= IA64_FIRST_ROTATING_FR) { ia64_flush_fph(current); #ifdef XEN *fpval = current->arch._thread.fph[fph_index(regs, regnum)]; #else *fpval = current->thread.fph[fph_index(regs, regnum)]; #endif } else { /* * f0 = 0.0, f1= 1.0. Those registers are constant and are thus * not saved, we must generate their spilled form on the fly */ switch(regnum) { case 0: float_spill_f0(fpval); break; case 1: float_spill_f1(fpval); break; default: /* * pt_regs or switch_stack ? */ addr = FR_IN_SW(regnum) ? (unsigned long)sw : (unsigned long)regs; DPRINT("is_sw=%d tmp_base=%lx offset=0x%x\n", FR_IN_SW(regnum), addr, FR_OFFS(regnum)); addr += FR_OFFS(regnum); *fpval = *(struct ia64_fpreg *)addr; } } } #else void getfpreg (unsigned long regnum, struct ia64_fpreg *fpval, struct pt_regs *regs) { // Take floating register rotation into consideration if(regnum >= IA64_FIRST_ROTATING_FR) regnum = IA64_FIRST_ROTATING_FR + fph_index(regs, regnum); #define CASE_FIXED_FP(reg) \ case reg: \ ia64_stf_spill(fpval,reg); \ break #define CASE_SAVED_FP(reg) \ case reg: \ fpval->u.bits[0] = regs->f##reg.u.bits[0]; \ fpval->u.bits[1] = regs->f##reg.u.bits[1]; \ break switch(regnum) { CASE_FIXED_FP(0); CASE_FIXED_FP(1); CASE_FIXED_FP(2); CASE_FIXED_FP(3); CASE_FIXED_FP(4); CASE_FIXED_FP(5); CASE_SAVED_FP(6); CASE_SAVED_FP(7); CASE_SAVED_FP(8); CASE_SAVED_FP(9); CASE_SAVED_FP(10); CASE_SAVED_FP(11); CASE_FIXED_FP(12); CASE_FIXED_FP(13); CASE_FIXED_FP(14); CASE_FIXED_FP(15); CASE_FIXED_FP(16); CASE_FIXED_FP(17); CASE_FIXED_FP(18); CASE_FIXED_FP(19); CASE_FIXED_FP(20); CASE_FIXED_FP(21); CASE_FIXED_FP(22); CASE_FIXED_FP(23); CASE_FIXED_FP(24); CASE_FIXED_FP(25); CASE_FIXED_FP(26); CASE_FIXED_FP(27); CASE_FIXED_FP(28); CASE_FIXED_FP(29); CASE_FIXED_FP(30); CASE_FIXED_FP(31); CASE_FIXED_FP(32); CASE_FIXED_FP(33); CASE_FIXED_FP(34); CASE_FIXED_FP(35); CASE_FIXED_FP(36); CASE_FIXED_FP(37); CASE_FIXED_FP(38); CASE_FIXED_FP(39); CASE_FIXED_FP(40); CASE_FIXED_FP(41); CASE_FIXED_FP(42); CASE_FIXED_FP(43); CASE_FIXED_FP(44); CASE_FIXED_FP(45); CASE_FIXED_FP(46); CASE_FIXED_FP(47); CASE_FIXED_FP(48); CASE_FIXED_FP(49); CASE_FIXED_FP(50); CASE_FIXED_FP(51); CASE_FIXED_FP(52); CASE_FIXED_FP(53); CASE_FIXED_FP(54); CASE_FIXED_FP(55); CASE_FIXED_FP(56); CASE_FIXED_FP(57); CASE_FIXED_FP(58); CASE_FIXED_FP(59); CASE_FIXED_FP(60); CASE_FIXED_FP(61); CASE_FIXED_FP(62); CASE_FIXED_FP(63); CASE_FIXED_FP(64); CASE_FIXED_FP(65); CASE_FIXED_FP(66); CASE_FIXED_FP(67); CASE_FIXED_FP(68); CASE_FIXED_FP(69); CASE_FIXED_FP(70); CASE_FIXED_FP(71); CASE_FIXED_FP(72); CASE_FIXED_FP(73); CASE_FIXED_FP(74); CASE_FIXED_FP(75); CASE_FIXED_FP(76); CASE_FIXED_FP(77); CASE_FIXED_FP(78); CASE_FIXED_FP(79); CASE_FIXED_FP(80); CASE_FIXED_FP(81); CASE_FIXED_FP(82); CASE_FIXED_FP(83); CASE_FIXED_FP(84); CASE_FIXED_FP(85); CASE_FIXED_FP(86); CASE_FIXED_FP(87); CASE_FIXED_FP(88); CASE_FIXED_FP(89); CASE_FIXED_FP(90); CASE_FIXED_FP(91); CASE_FIXED_FP(92); CASE_FIXED_FP(93); CASE_FIXED_FP(94); CASE_FIXED_FP(95); CASE_FIXED_FP(96); CASE_FIXED_FP(97); CASE_FIXED_FP(98); CASE_FIXED_FP(99); CASE_FIXED_FP(100); CASE_FIXED_FP(101); CASE_FIXED_FP(102); CASE_FIXED_FP(103); CASE_FIXED_FP(104); CASE_FIXED_FP(105); CASE_FIXED_FP(106); CASE_FIXED_FP(107); CASE_FIXED_FP(108); CASE_FIXED_FP(109); CASE_FIXED_FP(110); CASE_FIXED_FP(111); CASE_FIXED_FP(112); CASE_FIXED_FP(113); CASE_FIXED_FP(114); CASE_FIXED_FP(115); CASE_FIXED_FP(116); CASE_FIXED_FP(117); CASE_FIXED_FP(118); CASE_FIXED_FP(119); CASE_FIXED_FP(120); CASE_FIXED_FP(121); CASE_FIXED_FP(122); CASE_FIXED_FP(123); CASE_FIXED_FP(124); CASE_FIXED_FP(125); CASE_FIXED_FP(126); CASE_FIXED_FP(127); } #undef CASE_FIXED_FP #undef CASE_SAVED_FP } void setfpreg (unsigned long regnum, struct ia64_fpreg *fpval, struct pt_regs *regs) { // Take floating register rotation into consideration ia64_fph_enable(); if(regnum >= IA64_FIRST_ROTATING_FR) regnum = IA64_FIRST_ROTATING_FR + fph_index(regs, regnum); #define CASE_FIXED_FP(reg) \ case reg: \ ia64_ldf_fill(reg,fpval); \ break #define CASE_RESTORED_FP(reg) \ case reg: \ regs->f##reg.u.bits[0] = fpval->u.bits[0]; \ regs->f##reg.u.bits[1] = fpval->u.bits[1] ; \ break switch(regnum) { CASE_FIXED_FP(2); CASE_FIXED_FP(3); CASE_FIXED_FP(4); CASE_FIXED_FP(5); CASE_RESTORED_FP(6); CASE_RESTORED_FP(7); CASE_RESTORED_FP(8); CASE_RESTORED_FP(9); CASE_RESTORED_FP(10); CASE_RESTORED_FP(11); CASE_FIXED_FP(12); CASE_FIXED_FP(13); CASE_FIXED_FP(14); CASE_FIXED_FP(15); CASE_FIXED_FP(16); CASE_FIXED_FP(17); CASE_FIXED_FP(18); CASE_FIXED_FP(19); CASE_FIXED_FP(20); CASE_FIXED_FP(21); CASE_FIXED_FP(22); CASE_FIXED_FP(23); CASE_FIXED_FP(24); CASE_FIXED_FP(25); CASE_FIXED_FP(26); CASE_FIXED_FP(27); CASE_FIXED_FP(28); CASE_FIXED_FP(29); CASE_FIXED_FP(30); CASE_FIXED_FP(31); CASE_FIXED_FP(32); CASE_FIXED_FP(33); CASE_FIXED_FP(34); CASE_FIXED_FP(35); CASE_FIXED_FP(36); CASE_FIXED_FP(37); CASE_FIXED_FP(38); CASE_FIXED_FP(39); CASE_FIXED_FP(40); CASE_FIXED_FP(41); CASE_FIXED_FP(42); CASE_FIXED_FP(43); CASE_FIXED_FP(44); CASE_FIXED_FP(45); CASE_FIXED_FP(46); CASE_FIXED_FP(47); CASE_FIXED_FP(48); CASE_FIXED_FP(49); CASE_FIXED_FP(50); CASE_FIXED_FP(51); CASE_FIXED_FP(52); CASE_FIXED_FP(53); CASE_FIXED_FP(54); CASE_FIXED_FP(55); CASE_FIXED_FP(56); CASE_FIXED_FP(57); CASE_FIXED_FP(58); CASE_FIXED_FP(59); CASE_FIXED_FP(60); CASE_FIXED_FP(61); CASE_FIXED_FP(62); CASE_FIXED_FP(63); CASE_FIXED_FP(64); CASE_FIXED_FP(65); CASE_FIXED_FP(66); CASE_FIXED_FP(67); CASE_FIXED_FP(68); CASE_FIXED_FP(69); CASE_FIXED_FP(70); CASE_FIXED_FP(71); CASE_FIXED_FP(72); CASE_FIXED_FP(73); CASE_FIXED_FP(74); CASE_FIXED_FP(75); CASE_FIXED_FP(76); CASE_FIXED_FP(77); CASE_FIXED_FP(78); CASE_FIXED_FP(79); CASE_FIXED_FP(80); CASE_FIXED_FP(81); CASE_FIXED_FP(82); CASE_FIXED_FP(83); CASE_FIXED_FP(84); CASE_FIXED_FP(85); CASE_FIXED_FP(86); CASE_FIXED_FP(87); CASE_FIXED_FP(88); CASE_FIXED_FP(89); CASE_FIXED_FP(90); CASE_FIXED_FP(91); CASE_FIXED_FP(92); CASE_FIXED_FP(93); CASE_FIXED_FP(94); CASE_FIXED_FP(95); CASE_FIXED_FP(96); CASE_FIXED_FP(97); CASE_FIXED_FP(98); CASE_FIXED_FP(99); CASE_FIXED_FP(100); CASE_FIXED_FP(101); CASE_FIXED_FP(102); CASE_FIXED_FP(103); CASE_FIXED_FP(104); CASE_FIXED_FP(105); CASE_FIXED_FP(106); CASE_FIXED_FP(107); CASE_FIXED_FP(108); CASE_FIXED_FP(109); CASE_FIXED_FP(110); CASE_FIXED_FP(111); CASE_FIXED_FP(112); CASE_FIXED_FP(113); CASE_FIXED_FP(114); CASE_FIXED_FP(115); CASE_FIXED_FP(116); CASE_FIXED_FP(117); CASE_FIXED_FP(118); CASE_FIXED_FP(119); CASE_FIXED_FP(120); CASE_FIXED_FP(121); CASE_FIXED_FP(122); CASE_FIXED_FP(123); CASE_FIXED_FP(124); CASE_FIXED_FP(125); CASE_FIXED_FP(126); CASE_FIXED_FP(127); } #undef CASE_FIXED_FP #undef CASE_RESTORED_FP } #endif /* XEN */ #ifdef XEN void #else static void #endif getreg (unsigned long regnum, unsigned long *val, int *nat, struct pt_regs *regs) { struct switch_stack *sw = (struct switch_stack *) regs - 1; unsigned long addr, *unat; if (regnum >= IA64_FIRST_STACKED_GR) { get_rse_reg(regs, regnum, val, nat); return; } /* * take care of r0 (read-only always evaluate to 0) */ if (regnum == 0) { *val = 0; if (nat) *nat = 0; return; } /* * Now look at registers in [0-31] range and init correct UNAT */ if (GR_IN_SW(regnum)) { addr = (unsigned long)sw; unat = &sw->ar_unat; } else { addr = (unsigned long)regs; #if defined(XEN) unat = &regs->eml_unat;; #else unat = &sw->caller_unat; #endif } DPRINT("addr_base=%lx offset=0x%x\n", addr, GR_OFFS(regnum)); addr += GR_OFFS(regnum); *val = *(unsigned long *)addr; /* * do it only when requested */ if (nat) *nat = (*unat >> (addr >> 3 & 0x3f)) & 0x1UL; } #ifndef XEN static void emulate_load_updates (update_t type, load_store_t ld, struct pt_regs *regs, unsigned long ifa) { /* * IMPORTANT: * Given the way we handle unaligned speculative loads, we should * not get to this point in the code but we keep this sanity check, * just in case. */ if (ld.x6_op == 1 || ld.x6_op == 3) { printk(KERN_ERR "%s: register update on speculative load, error\n", __FUNCTION__); die_if_kernel("unaligned reference on speculative load with register update\n", regs, 30); } /* * at this point, we know that the base register to update is valid i.e., * it's not r0 */ if (type == UPD_IMMEDIATE) { unsigned long imm; /* * Load +Imm: ldXZ r1=[r3],imm(9) * * * form imm9: [13:19] contain the first 7 bits */ imm = ld.x << 7 | ld.imm; /* * sign extend (1+8bits) if m set */ if (ld.m) imm |= SIGN_EXT9; /* * ifa == r3 and we know that the NaT bit on r3 was clear so * we can directly use ifa. */ ifa += imm; setreg(ld.r3, ifa, 0, regs); DPRINT("ld.x=%d ld.m=%d imm=%ld r3=0x%lx\n", ld.x, ld.m, imm, ifa); } else if (ld.m) { unsigned long r2; int nat_r2; /* * Load +Reg Opcode: ldXZ r1=[r3],r2 * * Note: that we update r3 even in the case of ldfX.a * (where the load does not happen) * * The way the load algorithm works, we know that r3 does not * have its NaT bit set (would have gotten NaT consumption * before getting the unaligned fault). So we can use ifa * which equals r3 at this point. * * IMPORTANT: * The above statement holds ONLY because we know that we * never reach this code when trying to do a ldX.s. * If we ever make it to here on an ldfX.s then */ getreg(ld.imm, &r2, &nat_r2, regs); ifa += r2; /* * propagate Nat r2 -> r3 */ setreg(ld.r3, ifa, nat_r2, regs); DPRINT("imm=%d r2=%ld r3=0x%lx nat_r2=%d\n",ld.imm, r2, ifa, nat_r2); } } static int emulate_load_int (unsigned long ifa, load_store_t ld, struct pt_regs *regs) { unsigned int len = 1 << ld.x6_sz; unsigned long val = 0; /* * r0, as target, doesn't need to be checked because Illegal Instruction * faults have higher priority than unaligned faults. * * r0 cannot be found as the base as it would never generate an * unaligned reference. */ /* * ldX.a we will emulate load and also invalidate the ALAT entry. * See comment below for explanation on how we handle ldX.a */ if (len != 2 && len != 4 && len != 8) { DPRINT("unknown size: x6=%d\n", ld.x6_sz); return -1; } /* this assumes little-endian byte-order: */ if (copy_from_user(&val, (void __user *) ifa, len)) return -1; setreg(ld.r1, val, 0, regs); /* * check for updates on any kind of loads */ if (ld.op == 0x5 || ld.m) emulate_load_updates(ld.op == 0x5 ? UPD_IMMEDIATE: UPD_REG, ld, regs, ifa); /* * handling of various loads (based on EAS2.4): * * ldX.acq (ordered load): * - acquire semantics would have been used, so force fence instead. * * ldX.c.clr (check load and clear): * - if we get to this handler, it's because the entry was not in the ALAT. * Therefore the operation reverts to a normal load * * ldX.c.nc (check load no clear): * - same as previous one * * ldX.c.clr.acq (ordered check load and clear): * - same as above for c.clr part. The load needs to have acquire semantics. So * we use the fence semantics which is stronger and thus ensures correctness. * * ldX.a (advanced load): * - suppose ldX.a r1=[r3]. If we get to the unaligned trap it's because the * address doesn't match requested size alignment. This means that we would * possibly need more than one load to get the result. * * The load part can be handled just like a normal load, however the difficult * part is to get the right thing into the ALAT. The critical piece of information * in the base address of the load & size. To do that, a ld.a must be executed, * clearly any address can be pushed into the table by using ld1.a r1=[r3]. Now * if we use the same target register, we will be okay for the check.a instruction. * If we look at the store, basically a stX [r3]=r1 checks the ALAT for any entry * which would overlap within [r3,r3+X] (the size of the load was store in the * ALAT). If such an entry is found the entry is invalidated. But this is not good * enough, take the following example: * r3=3 * ld4.a r1=[r3] * * Could be emulated by doing: * ld1.a r1=[r3],1 * store to temporary; * ld1.a r1=[r3],1 * store & shift to temporary; * ld1.a r1=[r3],1 * store & shift to temporary; * ld1.a r1=[r3] * store & shift to temporary; * r1=temporary * * So in this case, you would get the right value is r1 but the wrong info in * the ALAT. Notice that you could do it in reverse to finish with address 3 * but you would still get the size wrong. To get the size right, one needs to * execute exactly the same kind of load. You could do it from a aligned * temporary location, but you would get the address wrong. * * So no matter what, it is not possible to emulate an advanced load * correctly. But is that really critical ? * * We will always convert ld.a into a normal load with ALAT invalidated. This * will enable compiler to do optimization where certain code path after ld.a * is not required to have ld.c/chk.a, e.g., code path with no intervening stores. * * If there is a store after the advanced load, one must either do a ld.c.* or * chk.a.* to reuse the value stored in the ALAT. Both can "fail" (meaning no * entry found in ALAT), and that's perfectly ok because: * * - ld.c.*, if the entry is not present a normal load is executed * - chk.a.*, if the entry is not present, execution jumps to recovery code * * In either case, the load can be potentially retried in another form. * * ALAT must be invalidated for the register (so that chk.a or ld.c don't pick * up a stale entry later). The register base update MUST also be performed. */ /* * when the load has the .acq completer then * use ordering fence. */ if (ld.x6_op == 0x5 || ld.x6_op == 0xa) mb(); /* * invalidate ALAT entry in case of advanced load */ if (ld.x6_op == 0x2) invala_gr(ld.r1); return 0; } static int emulate_store_int (unsigned long ifa, load_store_t ld, struct pt_regs *regs) { unsigned long r2; unsigned int len = 1 << ld.x6_sz; /* * if we get to this handler, Nat bits on both r3 and r2 have already * been checked. so we don't need to do it * * extract the value to be stored */ getreg(ld.imm, &r2, NULL, regs); /* * we rely on the macros in unaligned.h for now i.e., * we let the compiler figure out how to read memory gracefully. * * We need this switch/case because the way the inline function * works. The code is optimized by the compiler and looks like * a single switch/case. */ DPRINT("st%d [%lx]=%lx\n", len, ifa, r2); if (len != 2 && len != 4 && len != 8) { DPRINT("unknown size: x6=%d\n", ld.x6_sz); return -1; } /* this assumes little-endian byte-order: */ if (copy_to_user((void __user *) ifa, &r2, len)) return -1; /* * stX [r3]=r2,imm(9) * * NOTE: * ld.r3 can never be r0, because r0 would not generate an * unaligned access. */ if (ld.op == 0x5) { unsigned long imm; /* * form imm9: [12:6] contain first 7bits */ imm = ld.x << 7 | ld.r1; /* * sign extend (8bits) if m set */ if (ld.m) imm |= SIGN_EXT9; /* * ifa == r3 (NaT is necessarily cleared) */ ifa += imm; DPRINT("imm=%lx r3=%lx\n", imm, ifa); setreg(ld.r3, ifa, 0, regs); } /* * we don't have alat_invalidate_multiple() so we need * to do the complete flush :-<< */ ia64_invala(); /* * stX.rel: use fence instead of release */ if (ld.x6_op == 0xd) mb(); return 0; } #endif /* XEN */ /* * floating point operations sizes in bytes */ static const unsigned char float_fsz[4]={ 10, /* extended precision (e) */ 8, /* integer (8) */ 4, /* single precision (s) */ 8 /* double precision (d) */ }; static inline void mem2float_extended (struct ia64_fpreg *init, struct ia64_fpreg *final) { ia64_ldfe(6, init); ia64_stop(); ia64_stf_spill(final, 6); } static inline void mem2float_integer (struct ia64_fpreg *init, struct ia64_fpreg *final) { ia64_ldf8(6, init); ia64_stop(); ia64_stf_spill(final, 6); } static inline void mem2float_single (struct ia64_fpreg *init, struct ia64_fpreg *final) { ia64_ldfs(6, init); ia64_stop(); ia64_stf_spill(final, 6); } static inline void mem2float_double (struct ia64_fpreg *init, struct ia64_fpreg *final) { ia64_ldfd(6, init); ia64_stop(); ia64_stf_spill(final, 6); } static inline void float2mem_extended (struct ia64_fpreg *init, struct ia64_fpreg *final) { ia64_ldf_fill(6, init); ia64_stop(); ia64_stfe(final, 6); } static inline void float2mem_integer (struct ia64_fpreg *init, struct ia64_fpreg *final) { ia64_ldf_fill(6, init); ia64_stop(); ia64_stf8(final, 6); } static inline void float2mem_single (struct ia64_fpreg *init, struct ia64_fpreg *final) { ia64_ldf_fill(6, init); ia64_stop(); ia64_stfs(final, 6); } static inline void float2mem_double (struct ia64_fpreg *init, struct ia64_fpreg *final) { ia64_ldf_fill(6, init); ia64_stop(); ia64_stfd(final, 6); } #ifndef XEN static int emulate_load_floatpair (unsigned long ifa, load_store_t ld, struct pt_regs *regs) { struct ia64_fpreg fpr_init[2]; struct ia64_fpreg fpr_final[2]; unsigned long len = float_fsz[ld.x6_sz]; /* * fr0 & fr1 don't need to be checked because Illegal Instruction faults have * higher priority than unaligned faults. * * r0 cannot be found as the base as it would never generate an unaligned * reference. */ /* * make sure we get clean buffers */ memset(&fpr_init, 0, sizeof(fpr_init)); memset(&fpr_final, 0, sizeof(fpr_final)); /* * ldfpX.a: we don't try to emulate anything but we must * invalidate the ALAT entry and execute updates, if any. */ if (ld.x6_op != 0x2) { /* * This assumes little-endian byte-order. Note that there is no "ldfpe" * instruction: */ if (copy_from_user(&fpr_init[0], (void __user *) ifa, len) || copy_from_user(&fpr_init[1], (void __user *) (ifa + len), len)) return -1; DPRINT("ld.r1=%d ld.imm=%d x6_sz=%d\n", ld.r1, ld.imm, ld.x6_sz); DDUMP("frp_init =", &fpr_init, 2*len); /* * XXX fixme * Could optimize inlines by using ldfpX & 2 spills */ switch( ld.x6_sz ) { case 0: mem2float_extended(&fpr_init[0], &fpr_final[0]); mem2float_extended(&fpr_init[1], &fpr_final[1]); break; case 1: mem2float_integer(&fpr_init[0], &fpr_final[0]); mem2float_integer(&fpr_init[1], &fpr_final[1]); break; case 2: mem2float_single(&fpr_init[0], &fpr_final[0]); mem2float_single(&fpr_init[1], &fpr_final[1]); break; case 3: mem2float_double(&fpr_init[0], &fpr_final[0]); mem2float_double(&fpr_init[1], &fpr_final[1]); break; } DDUMP("fpr_final =", &fpr_final, 2*len); /* * XXX fixme * * A possible optimization would be to drop fpr_final and directly * use the storage from the saved context i.e., the actual final * destination (pt_regs, switch_stack or thread structure). */ setfpreg(ld.r1, &fpr_final[0], regs); setfpreg(ld.imm, &fpr_final[1], regs); } /* * Check for updates: only immediate updates are available for this * instruction. */ if (ld.m) { /* * the immediate is implicit given the ldsz of the operation: * single: 8 (2x4) and for all others it's 16 (2x8) */ ifa += len<<1; /* * IMPORTANT: * the fact that we force the NaT of r3 to zero is ONLY valid * as long as we don't come here with a ldfpX.s. * For this reason we keep this sanity check */ if (ld.x6_op == 1 || ld.x6_op == 3) printk(KERN_ERR "%s: register update on speculative load pair, error\n", __FUNCTION__); setreg(ld.r3, ifa, 0, regs); } /* * Invalidate ALAT entries, if any, for both registers. */ if (ld.x6_op == 0x2) { invala_fr(ld.r1); invala_fr(ld.imm); } return 0; } static int emulate_load_float (unsigned long ifa, load_store_t ld, struct pt_regs *regs) { struct ia64_fpreg fpr_init; struct ia64_fpreg fpr_final; unsigned long len = float_fsz[ld.x6_sz]; /* * fr0 & fr1 don't need to be checked because Illegal Instruction * faults have higher priority than unaligned faults. * * r0 cannot be found as the base as it would never generate an * unaligned reference. */ /* * make sure we get clean buffers */ memset(&fpr_init,0, sizeof(fpr_init)); memset(&fpr_final,0, sizeof(fpr_final)); /* * ldfX.a we don't try to emulate anything but we must * invalidate the ALAT entry. * See comments in ldX for descriptions on how the various loads are handled. */ if (ld.x6_op != 0x2) { if (copy_from_user(&fpr_init, (void __user *) ifa, len)) return -1; DPRINT("ld.r1=%d x6_sz=%d\n", ld.r1, ld.x6_sz); DDUMP("fpr_init =", &fpr_init, len); /* * we only do something for x6_op={0,8,9} */ switch( ld.x6_sz ) { case 0: mem2float_extended(&fpr_init, &fpr_final); break; case 1: mem2float_integer(&fpr_init, &fpr_final); break; case 2: mem2float_single(&fpr_init, &fpr_final); break; case 3: mem2float_double(&fpr_init, &fpr_final); break; } DDUMP("fpr_final =", &fpr_final, len); /* * XXX fixme * * A possible optimization would be to drop fpr_final and directly * use the storage from the saved context i.e., the actual final * destination (pt_regs, switch_stack or thread structure). */ setfpreg(ld.r1, &fpr_final, regs); } /* * check for updates on any loads */ if (ld.op == 0x7 || ld.m) emulate_load_updates(ld.op == 0x7 ? UPD_IMMEDIATE: UPD_REG, ld, regs, ifa); /* * invalidate ALAT entry in case of advanced floating point loads */ if (ld.x6_op == 0x2) invala_fr(ld.r1); return 0; } static int emulate_store_float (unsigned long ifa, load_store_t ld, struct pt_regs *regs) { struct ia64_fpreg fpr_init; struct ia64_fpreg fpr_final; unsigned long len = float_fsz[ld.x6_sz]; /* * make sure we get clean buffers */ memset(&fpr_init,0, sizeof(fpr_init)); memset(&fpr_final,0, sizeof(fpr_final)); /* * if we get to this handler, Nat bits on both r3 and r2 have already * been checked. so we don't need to do it * * extract the value to be stored */ getfpreg(ld.imm, &fpr_init, regs); /* * during this step, we extract the spilled registers from the saved * context i.e., we refill. Then we store (no spill) to temporary * aligned location */ switch( ld.x6_sz ) { case 0: float2mem_extended(&fpr_init, &fpr_final); break; case 1: float2mem_integer(&fpr_init, &fpr_final); break; case 2: float2mem_single(&fpr_init, &fpr_final); break; case 3: float2mem_double(&fpr_init, &fpr_final); break; } DPRINT("ld.r1=%d x6_sz=%d\n", ld.r1, ld.x6_sz); DDUMP("fpr_init =", &fpr_init, len); DDUMP("fpr_final =", &fpr_final, len); if (copy_to_user((void __user *) ifa, &fpr_final, len)) return -1; /* * stfX [r3]=r2,imm(9) * * NOTE: * ld.r3 can never be r0, because r0 would not generate an * unaligned access. */ if (ld.op == 0x7) { unsigned long imm; /* * form imm9: [12:6] contain first 7bits */ imm = ld.x << 7 | ld.r1; /* * sign extend (8bits) if m set */ if (ld.m) imm |= SIGN_EXT9; /* * ifa == r3 (NaT is necessarily cleared) */ ifa += imm; DPRINT("imm=%lx r3=%lx\n", imm, ifa); setreg(ld.r3, ifa, 0, regs); } /* * we don't have alat_invalidate_multiple() so we need * to do the complete flush :-<< */ ia64_invala(); return 0; } /* * Make sure we log the unaligned access, so that user/sysadmin can notice it and * eventually fix the program. However, we don't want to do that for every access so we * pace it with jiffies. This isn't really MP-safe, but it doesn't really have to be * either... */ static int within_logging_rate_limit (void) { static unsigned long count, last_time; if (jiffies - last_time > 5*HZ) count = 0; if (++count < 5) { last_time = jiffies; return 1; } return 0; } #endif /* XEN */ void ia64_handle_unaligned (unsigned long ifa, struct pt_regs *regs) { #ifdef XEN printk("ia64_handle_unaligned: called, not working yet\n"); #else struct ia64_psr *ipsr = ia64_psr(regs); mm_segment_t old_fs = get_fs(); unsigned long bundle[2]; unsigned long opcode; struct siginfo si; const struct exception_table_entry *eh = NULL; union { unsigned long l; load_store_t insn; } u; int ret = -1; if (ia64_psr(regs)->be) { /* we don't support big-endian accesses */ die_if_kernel("big-endian unaligned accesses are not supported", regs, 0); goto force_sigbus; } /* * Treat kernel accesses for which there is an exception handler entry the same as * user-level unaligned accesses. Otherwise, a clever program could trick this * handler into reading an arbitrary kernel addresses... */ if (!user_mode(regs)) eh = search_exception_tables(regs->cr_iip + ia64_psr(regs)->ri); if (user_mode(regs) || eh) { if ((current->thread.flags & IA64_THREAD_UAC_SIGBUS) != 0) goto force_sigbus; if (!(current->thread.flags & IA64_THREAD_UAC_NOPRINT) && within_logging_rate_limit()) { char buf[200]; /* comm[] is at most 16 bytes... */ size_t len; len = snprintf(buf, sizeof(buf), "%s(%d): unaligned access to 0x%016lx, " "ip=0x%016lx\n\r", current->comm, current->pid, ifa, regs->cr_iip + ipsr->ri); /* * Don't call tty_write_message() if we're in the kernel; we might * be holding locks... */ if (user_mode(regs)) tty_write_message(current->signal->tty, buf); buf[len-1] = '\0'; /* drop '\r' */ printk(KERN_WARNING "%s", buf); /* watch for command names containing %s */ } } else { if (within_logging_rate_limit()) printk(KERN_WARNING "kernel unaligned access to 0x%016lx, ip=0x%016lx\n", ifa, regs->cr_iip + ipsr->ri); set_fs(KERNEL_DS); } DPRINT("iip=%lx ifa=%lx isr=%lx (ei=%d, sp=%d)\n", regs->cr_iip, ifa, regs->cr_ipsr, ipsr->ri, ipsr->it); if (__copy_from_user(bundle, (void __user *) regs->cr_iip, 16)) goto failure; /* * extract the instruction from the bundle given the slot number */ switch (ipsr->ri) { case 0: u.l = (bundle[0] >> 5); break; case 1: u.l = (bundle[0] >> 46) | (bundle[1] << 18); break; case 2: u.l = (bundle[1] >> 23); break; } opcode = (u.l >> IA64_OPCODE_SHIFT) & IA64_OPCODE_MASK; DPRINT("opcode=%lx ld.qp=%d ld.r1=%d ld.imm=%d ld.r3=%d ld.x=%d ld.hint=%d " "ld.x6=0x%x ld.m=%d ld.op=%d\n", opcode, u.insn.qp, u.insn.r1, u.insn.imm, u.insn.r3, u.insn.x, u.insn.hint, u.insn.x6_sz, u.insn.m, u.insn.op); /* * IMPORTANT: * Notice that the switch statement DOES not cover all possible instructions * that DO generate unaligned references. This is made on purpose because for some * instructions it DOES NOT make sense to try and emulate the access. Sometimes it * is WRONG to try and emulate. Here is a list of instruction we don't emulate i.e., * the program will get a signal and die: * * load/store: * - ldX.spill * - stX.spill * Reason: RNATs are based on addresses * - ld16 * - st16 * Reason: ld16 and st16 are supposed to occur in a single * memory op * * synchronization: * - cmpxchg * - fetchadd * - xchg * Reason: ATOMIC operations cannot be emulated properly using multiple * instructions. * * speculative loads: * - ldX.sZ * Reason: side effects, code must be ready to deal with failure so simpler * to let the load fail. * --------------------------------------------------------------------------------- * XXX fixme * * I would like to get rid of this switch case and do something * more elegant. */ switch (opcode) { case LDS_OP: case LDSA_OP: if (u.insn.x) /* oops, really a semaphore op (cmpxchg, etc) */ goto failure; /* no break */ case LDS_IMM_OP: case LDSA_IMM_OP: case LDFS_OP: case LDFSA_OP: case LDFS_IMM_OP: /* * The instruction will be retried with deferred exceptions turned on, and * we should get Nat bit installed * * IMPORTANT: When PSR_ED is set, the register & immediate update forms * are actually executed even though the operation failed. So we don't * need to take care of this. */ DPRINT("forcing PSR_ED\n"); regs->cr_ipsr |= IA64_PSR_ED; goto done; case LD_OP: case LDA_OP: case LDBIAS_OP: case LDACQ_OP: case LDCCLR_OP: case LDCNC_OP: case LDCCLRACQ_OP: if (u.insn.x) /* oops, really a semaphore op (cmpxchg, etc) */ goto failure; /* no break */ case LD_IMM_OP: case LDA_IMM_OP: case LDBIAS_IMM_OP: case LDACQ_IMM_OP: case LDCCLR_IMM_OP: case LDCNC_IMM_OP: case LDCCLRACQ_IMM_OP: ret = emulate_load_int(ifa, u.insn, regs); break; case ST_OP: case STREL_OP: if (u.insn.x) /* oops, really a semaphore op (cmpxchg, etc) */ goto failure; /* no break */ case ST_IMM_OP: case STREL_IMM_OP: ret = emulate_store_int(ifa, u.insn, regs); break; case LDF_OP: case LDFA_OP: case LDFCCLR_OP: case LDFCNC_OP: case LDF_IMM_OP: case LDFA_IMM_OP: case LDFCCLR_IMM_OP: case LDFCNC_IMM_OP: if (u.insn.x) ret = emulate_load_floatpair(ifa, u.insn, regs); else ret = emulate_load_float(ifa, u.insn, regs); break; case STF_OP: case STF_IMM_OP: ret = emulate_store_float(ifa, u.insn, regs); break; default: goto failure; } DPRINT("ret=%d\n", ret); if (ret) goto failure; if (ipsr->ri == 2) /* * given today's architecture this case is not likely to happen because a * memory access instruction (M) can never be in the last slot of a * bundle. But let's keep it for now. */ regs->cr_iip += 16; ipsr->ri = (ipsr->ri + 1) & 0x3; DPRINT("ipsr->ri=%d iip=%lx\n", ipsr->ri, regs->cr_iip); done: set_fs(old_fs); /* restore original address limit */ return; failure: /* something went wrong... */ if (!user_mode(regs)) { if (eh) { ia64_handle_exception(regs, eh); goto done; } die_if_kernel("error during unaligned kernel access\n", regs, ret); /* NOT_REACHED */ } force_sigbus: si.si_signo = SIGBUS; si.si_errno = 0; si.si_code = BUS_ADRALN; si.si_addr = (void __user *) ifa; si.si_flags = 0; si.si_isr = 0; si.si_imm = 0; force_sig_info(SIGBUS, &si, current); goto done; #endif }