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From b1b3c3d2ce62872c8dec4a7d645af6b3c565e094 Mon Sep 17 00:00:00 2001
From: Sam Shih <sam.shih@mediatek.com>
Date: Mon, 20 Apr 2020 17:11:32 +0800
Subject: [PATCH 2/3] mt7622 uboot: add dts and config for spi nand
This patch add dts and config for mt7622 spi nand
Signed-off-by: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
---
arch/arm/dts/mt7622-rfb.dts | 6 ++++++
arch/arm/dts/mt7622.dtsi | 20 ++++++++++++++++++++
2 files changed, 26 insertions(+)
diff --git a/arch/arm/dts/mt7622-rfb.dts b/arch/arm/dts/mt7622-rfb.dts
index f05c3fe14d..05502bddec 100644
--- a/arch/arm/dts/mt7622-rfb.dts
+++ b/arch/arm/dts/mt7622-rfb.dts
@@ -143,6 +143,12 @@
};
};
+&nandc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&snfi_pins>;
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
diff --git a/arch/arm/dts/mt7622.dtsi b/arch/arm/dts/mt7622.dtsi
index 1e8ec9b48b..63fdb63d4a 100644
--- a/arch/arm/dts/mt7622.dtsi
+++ b/arch/arm/dts/mt7622.dtsi
@@ -52,6 +52,26 @@
#size-cells = <0>;
};
+ nandc: nfi@1100d000 {
+ compatible = "mediatek,mt7622-nfc";
+ reg = <0x1100d000 0x1000>,
+ <0x1100e000 0x1000>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_NFI_PD>,
+ <&pericfg CLK_PERI_NFIECC_PD>,
+ <&pericfg CLK_PERI_SNFI_PD>,
+ <&topckgen CLK_TOP_NFI_INFRA_SEL>,
+ <&topckgen CLK_TOP_UNIVPLL2_D8>;
+ clock-names = "nfi_clk",
+ "ecc_clk",
+ "snfi_clk",
+ "spinfi_sel",
+ "spinfi_parent_50m";
+ nand-ecc-mode = "hw";
+ status = "disabled";
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
--
2.17.1
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