aboutsummaryrefslogtreecommitdiffstats
path: root/target/linux/realtek
Commit message (Collapse)AuthorAgeFilesLines
...
* realtek: clean up RTL930x timer DT nodeSander Vanheule2022-02-201-3/+1
| | | | | | | | | | | | | | The Realtek timer node for RTL930x doesn't have any child nodes, making the use of '#address-cells' quite pointless. It is also not an interrupt controller, meaning it makes no sense to define '#interrupt-cells'. The I/O address for this node is also wrong, but this is hidden by the fact that the driver associated with this node bypasses the usual DT machinery and does it's own thing. Correct the address to have a sane value, even though it isn't actually used. Fixes: a75b9e3ecb61 ("realtek: Adding RTL930X sub-target") Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: ZyXEL GS1900-48: fix system LED polaritySander Vanheule2022-02-201-1/+1
| | | | | | | | | When driven by a GPIO pin, the system LED needs to be configured as active high. Otherwise the LED switches off after booting and initialisation. Fixes: 47f5a0a3eed5 ("realtek: Add support for ZyXEL GS1900-48 Switch") Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: ZyXEL GS1900-48: drop status from gpio1Sander Vanheule2022-02-201-2/+0
| | | | | | | | The default value for a DT node's status property is already "okay", so there's no need to specify it again. Drop the status property to clean up the DTS. Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: use higher priority for timer interruptsSander Vanheule2022-02-201-1/+1
| | | | | | | | | | | | | | The assigned output index for the event timers was quite low, lower even than the ethernet interrupt. This means that high network load could preempt timer interrupts, possibly leading to all sorts of strange behaviour. Increase the interrupt output index of the event timers to 5, which is the highest priority output and corresponds to the (otherwise unused) MIPS CPU timer interrupt. Fixes: a75b9e3ecb61 ("realtek: Adding RTL930X sub-target") Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: move RTL8231 definitions to board filesSander Vanheule2022-02-204-21/+23
| | | | | | | | | | | | | | The RTL8231 is an external chip, and not part of the SoC. That means it is more appropriate to define it in the board specific (base) files, instead of the DT include for the SoC itself. Moving the RTL8231 definition also ensures that boards with no GPIO expander, or an alternative one, don't have a useless gpio1 node label defined. Tested on a Netgear GS110TPPv1. Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: fix node addresses for RTL839xSander Vanheule2022-02-201-3/+3
| | | | | | | | | | The address in some node names doesn't match the actual offset specified in the DT node. Update the names to fix this. While fixing the node names, also drop the unused node labels. Fixes: 0a7565e53653 ("realtek: Update rtl839x.dtsi for realtek,rtl-intc, new gpio controller remove RTL8231 node") Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: consolidate bootargs againSander Vanheule2022-02-205-11/+3
| | | | | | | | | | | | | | | | | Bootargs for devices in the realtek target were previously consolidated in commit af2cfbda2bf5 ("realtek: Consolidate bootargs"), since all devices currently use the same arguments. Commit a75b9e3ecb61 ("realtek: Adding RTL930X sub-target") reverted this without any argumentation, so let's undo that. Commit 0b8dfe085180 ("realtek: Add RTL931X sub-target") introduced the old bootargs also for RTL931x, without providing any actual device support. Until that is done, let's assume vendors will have done what they did before, and use a baud rate of 115200. Fixes: a75b9e3ecb61 ("realtek: Adding RTL930X sub-target") Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: fix locking bug in rtl838x_hw_receive()Birger Koblitz2022-02-181-3/+4
| | | | | | | | | | | | | | A Locking bug in the packet receive path was introduced with PR #4973. The following patch prevents the driver from locking after a few minutes with an endless flow of [ 1434.185085] rtl838x-eth 1b00a300.ethernet eth0: Ring contention: r: 0, last a28000f4, cur a28000f8 [ 1434.208971] rtl838x-eth 1b00a300.ethernet eth0: Ring contention: r: 0, last a28000f4, cur a28000fc [ 1434.794800] rtl838x-eth 1b00a300.ethernet eth0: Ring contention: r: 0, last a28000f4, cur a28000fc [ 1435.049187] rtl838x-eth 1b00a300.ethernet eth0: Ring contention: r: 0, last a28000f4, cur a28000fc Signed-off-by: Bjørn Mork <bjorn@mork.no> Signed-off-by: Birger Koblitz <mail@birger-koblitz.de>
* realtek: add RTL8231 chip detectionSander Vanheule2022-02-171-1/+14
| | | | | | | | | | | | | | | | | | | | | | When initialising the driver, check if the RTL8231 chip is actually present at the specified address. If the READY_CODE value does not match the expected value, return -ENXIO to fail probing. This should help users to figure out which address an RTL8231 is configured to use, if measuring pull-up/-down resistors is not an option. On an unsuccesful probe, the driver will log: [ 0.795364] Probing RTL8231 GPIOs [ 0.798978] rtl8231_init called, MDIO bus ID: 30 [ 0.804194] rtl8231-gpio rtl8231-gpio: no device found at bus address 30 When a device is found, only the first two lines will be logged: [ 0.453698] Probing RTL8231 GPIOs [ 0.457312] rtl8231_init called, MDIO bus ID: 31 Signed-off-by: Sander Vanheule <sander@svanheule.net> Tested-by: Stijn Tintel <stijn@linux-ipv6.be>
* realtek: always require SMI bus ID for RTL8231Sander Vanheule2022-02-171-17/+16
| | | | | | | | | | | | | | | The SMI bus ID for RTL8231 currently defaults to 0, and can be overridden from the devicetree. However, there is no value check on the DT-provided value, aside from masking which would only cause value wrap-around. Change the driver to always require the "indirect-access-bus-id" property, as there is no real reason to use 0 as default, and perform a sanity check on the value when probing. This allows the other parts of the driver to be simplified a bit. Signed-off-by: Sander Vanheule <sander@svanheule.net> Tested-by: Stijn Tintel <stijn@linux-ipv6.be>
* realtek: use automatic GPIO numbering for RTL8231Sander Vanheule2022-02-171-1/+1
| | | | | | | | | Set the gpio_chip.base to -1 to use automatic GPIO line indexing. Setting base to 0 or a positive number is deprecated and should not be used. Signed-off-by: Sander Vanheule <sander@svanheule.net> Tested-by: Stijn Tintel <stijn@linux-ipv6.be>
* realtek: fix RTL8231 gpio countSander Vanheule2022-02-171-1/+1
| | | | | | | | | | The RTL8231's gpio_chip.ngpio was set to 36, which is the largest valid GPIO index. Fix the allowed number of GPIOs by setting ngpio to 37, the actual line count. Reported-by: INAGAKI Hiroshi <musashino.open@gmail.com> Signed-off-by: Sander Vanheule <sander@svanheule.net> Tested-by: Stijn Tintel <stijn@linux-ipv6.be>
* realtek: rtl83xx-phy: abstract and document PHY featuresDaniel Golle2022-02-171-114/+135
| | | | | | | | | | | | | Replace magic values with more self-descriptive code now that I start to understand more about the design of the PHY (and MDIO controller). Remove one line before reading RTL8214FC internal PHY id which turned out to be a no-op and can hence safely be removed (confirmed by INAGAKI Hiroshi[1]) [1]: https://github.com/openwrt/openwrt/commit/df8e6be59a1fbce3f8c6878fe7440a129b1245d6#r66890713 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
* realtek: fix locking issuesBirger Koblitz2022-02-172-26/+22
| | | | | | | Fixe a coupld of locking issues found by applying lock debugging to the code. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: switch to use generic MDIO accessor functionsDaniel Golle2022-02-176-473/+1238
| | | | | | | | Instead of directly calling SoC-specific functions in order to access (paged) MII registers or MMD registers, create infrastructure to allow using the generic phy_*, phy_*_paged and phy_*_mmd functions. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
* realtek: implement Clause-45 MDIO write on rtl931xDaniel Golle2022-02-172-26/+65
| | | | | | | | | * Add missing Clause-45 write support for rtl931x * Switch to use helper functions in all Clause-45 access functions to make the code more readable. * More meaningful/unified debugging output (dynamic kprintf) Signed-off-by: Daniel Golle <daniel@makrotopia.org>
* realtek: backport Clause-45 MDIO helper functionsDaniel Golle2022-02-171-0/+53
| | | | | | | | Import commit ("c6af53f038aa3 net: mdio: add helpers to extract clause 45 regad and devad fields") from Linux 5.17 to allow making the MDIO code in the ethernet driver more readable. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
* realtek: add support for port led configuration on RTL93XXBirger Koblitz2022-02-176-8/+175
| | | | | | | | | Using the led-set attribute of a port in the dts we allow configuration of the port leds. Each led-set is being defined in the led-set configuration of the .dts, giving a specific configuration to steer the port LEDs via a serial connection. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Add support for the RTL8221B PHYBirger Koblitz2022-02-172-0/+18
| | | | | | | | | The RTL8221B PHY is a newer version of the RTL8226, also supporting 2.5GBit Ethernet. It is found with RTL931X devices such as the EdgeCore ECS4125-10P Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com> Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Add specific PHY polling options to support the Zyxel XGS1250/XGS1210Birger Koblitz2022-02-172-14/+101
| | | | | | | | | | Both the Aquantia AQR113c and the RTL8226 PHYs in the Zyxel XGS1250 and the Zyxel XGS1210 require special polling configuration settings in the RTL930X_SMI_10GPHY_POLLING_REGxx_CFG configuration registers. Set them. Additionally, for RTL 1GBit phys set the RTL930X_SMI_PRVTE_POLLING_CTRL bits in the poll mask. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Fix link status detection on RTL9302 for SFP modulesBirger Koblitz2022-02-172-3/+23
| | | | | | | For SFP slots on the RTL9302, the link status is not correctly detected. Use the link media status instead. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Add RTL931X sub-targetBirger Koblitz2022-02-177-1/+517
| | | | | | | | We add the RTL931X sub-target with kernel configuration for a dual core MIPS InterAptive CPU. Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com> Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Add HW support for RTL931X for PIE, L2 and STP agingBirger Koblitz2022-02-172-52/+1188
| | | | | | | | We add HW support routines for the RTL931X SoC family for handling the Packet Inspection Engine, L2 table handling and STP aging. Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com> Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Store and Restore MC memberships for port enable/disableBirger Koblitz2022-02-172-55/+86
| | | | | | | | | We need to store and restore MC memberships in HW when a port joins or leaves a bridge as well as when it is enabled or disabled, as these properties should not change in these situations. Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com> Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Copy all BPDUs to the kernelBirger Koblitz2022-02-174-8/+140
| | | | | | | | In order to receive STP information at the kernel level, we make sure that all Bridge Protocol Data Units are copied to the CPU-Port. Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com> Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Add L2 aging configuration functions for all SoC familiesBirger Koblitz2022-02-176-19/+58
| | | | | | | | Instead of a generic L2 aging configuration function with complex logic, we implement an individual function for all SoC types. Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com> Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realted: Add DSA bridge offload configurationBirger Koblitz2022-02-174-1/+139
| | | | | | | | Add functionality to enable or disable L2 learning offload and port flooding for RTL83XX. Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com> Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Backport bridge configuration for DSABirger Koblitz2022-02-171-0/+144
| | | | | | | | | Adds the DSA API for bridge configuration (flooding, L2 learning, and aging) offload as found in Linux 5.12 so that we can implement it in our drivver. Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com> Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Add Link Aggregation (aka trunking) supportBirger Koblitz2022-02-178-15/+369
| | | | | | | | | This adds LAG support for all 4 SoC families, including support ofr the use of different distribution algorithm for the load- balancing between individual links. Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com> Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Backport LAG functionality for DSABirger Koblitz2022-02-171-0/+759
| | | | | | | | Add the LAG configuration API for DSA as found in Linux 5.12 so that we can implement it in the dsa driver. Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com> Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Cleanup setting inner/outer PVID and Ingress/Egres VLAN filteringBirger Koblitz2022-02-176-28/+189
| | | | | | | | Use setting functions instead of register numbers in order to clean up the code. Also use enums to define inner/outer VLAN types and the filter type. Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com> Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Add support for ZxXEL XGS1250-12 SwitchBirger Koblitz2022-02-172-0/+321
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ZyXEL XGS1250-12 Switch is a 11 + 1 port multi-GBit switch with 8 x 1000BaseT, 3 x 1000/2500/5000/10000BaseT Ethernet ports and 1 SFP+ module slot. Hardware: - RTL9302B SoC - Macronix MX25L12833F (16MB flash) - Nanja NT5CC64M16GP-1 (128MB DDR3 SDRAM) - RTL8231 GPIO extender to control the port LEDs - RTL8218D 8x Gigabit PHY - Aquantia AQR113c 1/2.5/5/10 Gigabit PHYs - SFP+ 10GBit slot Power is supplied via a 12V 2A standard barrel connector. At the right side behind the grid is UART serial connector. A Serial header can be connected to from the outside of the switch trough the airvents with a standard 2.54mm header. Pins are from top to bottom Vcc(3.3V), TX, RX and GND. Serial connection is via 115200 baud, 8N1. A reset button is accessble through a hole in the front panel At the time of this commit, all ethernet ports work under OpenWRT, including the various NBaseT modes, however the 10GBit SFP+ slot is not supported. Installation -------------- * Connect serial as per the layout above. Connection parameters: 115200 8N1. * Navigate to 'Management' in the OEM web interface and click on 'Firmware upgrade' to the left. * Upload the OpenWrt initramfs image, and wait till the switch reboots. * Connect to the device through serial and change the U-boot boot command. > fw_setenv bootcmd 'rtk network on; boota' * Reboot, scp the sysupgrade image to /tmp, verify the checksum and flash it: > sysupgrade /tmp/openwrt-realtek-rtl930x-zyxel_xgs1250-12-squashfs-sysupgrade.bin * Upon reboot, you have a functional OpenWrt installation. Leave the bootcmd value as is - without 'rtk network on' the switch will fail to initialise the network. Web recovery ------------ The XGS1250-12 has a handy web recovery that will load when U-boot does not find a bootable kernel. In case you would like to trigger the web recovery manually, partially overwrite the firmware partition with some zeroes: # dd if=/dev/zero of=/dev/mtd5 bs=1M count=2 If you have serial connected you'll see U-boot will start the web recovery and print it's listening on 192.168.1.1, but by default it seems to be on the OEM default IP for the switch - 192.168.1.3. The web recovery only listens on HTTP (80) and *not* on 443 (HTTPS) unlike the web UI. Return to stock --------------- You can flash the ZyXEL firmware images to return to stock: # sysupgrade -F -n XGS1250-12_Firmware_V1.00(ABWE.1)C0.bix Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Add RTL930X sub-targetBirger Koblitz2022-02-172-0/+222
| | | | | | | Adds the sub-target for the RTL930X-based routers. Adds an initial kernel configuration. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Add SDS configuration routines for the RTL93XX platformsBirger Koblitz2022-02-174-44/+2144
| | | | | | | | Adds configuration routines for the internal SerDes of the RTL930X and RTL931X. Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com> Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Improve MAC config handling for all SoCsBirger Koblitz2022-02-173-34/+205
| | | | | | | | | Adds a rtl931x_phylink_mac_config for the RTL931X and improve the handling of the RTL930X phylink configuration. Add separate handling of the RTL839x since some configurations are different from the RTL838X. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Add support for detecting RTL9303 SoCsBirger Koblitz2022-02-171-0/+4
| | | | | | | Adds support for detecting RTL9303 SoCs as found e.g. in the Ubiquiti USW switch. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Allow PHY-IDs to differ from Port numbersBirger Koblitz2022-02-171-9/+34
| | | | | | | | | We were using the PHY-ids (the reg entries in the PHY sections of the .dts) as the port numbers. Now scan the ports section in the .dts, and use the actual port numbers, following the phy-handle to the PHY properties. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Use SerDes Information from .dts for phylink configBirger Koblitz2022-02-172-5/+27
| | | | | | | | When a port is brought up, read the SDS-id via the phy_device for a given port and use this to configure the SDS when it is brought up. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Remove RTL838X PHY firmware from RTL839X kernelBirger Koblitz2022-02-171-2/+0
| | | | | | | The RTL839X does not have an internal phy and thus does not need to have any firmware as part of the kernel, especially not firmware for the RTL838X. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Improve IRQ request in Ethernet driverBirger Koblitz2022-02-171-5/+4
| | | | | | | Improves the IRQ request code by using platform_get_irq() which provides better error handling. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Adding RTL930X sub-targetBirger Koblitz2022-02-172-89/+34
| | | | | | This adds the RTL931X sub-target in the realtek target Makefile. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Use new CEVT timerBirger Koblitz2022-02-172-2/+4
| | | | | | | | Selects the new CEVT timer for Realtek instead of the previous timer driver. While we are at it, we explicitily state we do not use the I2C driver of the RTL9300. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Replace the RTL9300 generic timer with a CEVT timerBirger Koblitz2022-02-174-224/+266
| | | | | | | | | | | | | | The RTL9300 has a broken R4K MIPS timer interrupt, however, the R4K clocksource works. We replace the RTL9300 timer with a Clock Event Timer (CEVT), which is VSMP aware and can be instantiated as part of brining a VSMTP cpu up instead of the R4K CEVT source. For this we place the RTL9300 CEVT timer in arch/mips/kernel together with other MIPS CEVT timers, initialize the SoC IRQs from a modified smp-mt.c and instantiate each timer as part of the MIPS time setup in arch/mips/include/asm/time.h instead of the R4K CEVT, similarly as is done by other MIPS CEVT timers. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Fix RTL931X Ethernet driverBirger Koblitz2022-02-171-21/+167
| | | | | | | | | | Various fixes to enable Ethernet on the RTL931X: - Network start and stop sequence for RTL931X HW - MDIO access on RTL931X SoC - Chip initialization - SerDes setup Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Fix Ethernet driver IRQ service routine for SMPBirger Koblitz2022-02-171-5/+0
| | | | | | | Do not lock the register structure in IRQ context. It is not necessary and leads to lockups under SMP load. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: fix RTL839X receive tag decodingBirger Koblitz2022-02-171-4/+5
| | | | | | Correct offset in RX tag structure. Correct offload decision flagging. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Add SerDes access functions for RTL931XBirger Koblitz2022-02-172-0/+52
| | | | | | Adds RTL931X SerDes access functions as needed by the Ethernet driver. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Fix RTL931X-specific Ethernet driver functionsBirger Koblitz2022-02-173-30/+47
| | | | | | | Fix the update counter of the RX ring, add SDS access functions for RTL931X. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: rename rtl838x_reg structureBirger Koblitz2022-02-172-6/+6
| | | | | | | | Rename the SoC-specific rtl838x_reg structure in the Ethernet driver to avoid confusion with the structure of the same name in the DSA driver. New name is: rtl838x_eth_reg Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Fix RTL839x TX CPU-TagBirger Koblitz2022-02-171-2/+2
| | | | | | | | | | Setting bits 20 and 23 in a u16 is obviously wrong. According to https://www.svanheule.net/realtek/cypress/cputag cpu_tag[2] starts at bit 48 in the cpu-tag structure, so bit 43 is bit 5 in cpu_tag[2] and bit 40 is bit 8 in cpu_tag[2]. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-31 11:42:37 +0000