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* ipq40xx: net: phy: qca807x: fix GPIO driverRobert Marko2021-03-051-0/+1
| | | | | | | | | | | While rebasing into setting bits instead of magic values, I accidentally forgot to actually set the force bit. Without it using the pins as GPIO-s did not actually work. Fixes: b5c93ed ("ipq40xx: add Qualcomm QCA807x driver") Signed-off-by: Robert Marko <robert.marko@sartura.hr>
* ipq40xx: net: ethernet: edma: use generic PHY printRobert Marko2020-12-231-2/+2
| | | | | | | | | | | | | Lets use the generic upstream phy_print_status() instead of doing something similar by hand. Before: ess_edma c080000.edma: eth1: GMAC Link is up with phy_speed=1000 After: ess_edma c080000.edma eth1: Link is Up - 1Gbps/Full - flow control rx/tx Signed-off-by: Robert Marko <robert.marko@sartura.hr>
* ipq40xx: net: ethernet: edma: use generic ksettings functionsRobert Marko2020-12-231-56/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since we now have a proper PHY driver for QCA807x and AR803x has already been supported properly there is no need for the driver to be poking on PHY registers for ethtool ops. So, lets simply use the generic phy_ethtool_ksettings_get/phy_ethtool_ksettings_set functions. This also has the advantage of properly populating stuff other than speeds like, transceiver type, MDI-X etc. ethtool before: root@OpenWrt:/# ethtool eth1 Settings for eth1: Supported ports: [ TP MII ] Supported link modes: 10baseT/Half 10baseT/Full 100baseT/Half 100baseT/Full 1000baseT/Full 1000baseX/Full Supported pause frame use: Symmetric Receive-only Supports auto-negotiation: Yes Supported FEC modes: Not reported Advertised link modes: 10baseT/Half 10baseT/Full 100baseT/Half 100baseT/Full 1000baseT/Full 1000baseX/Full Advertised pause frame use: Symmetric Receive-only Advertised auto-negotiation: Yes Advertised FEC modes: Not reported Link partner advertised link modes: 10baseT/Half 10baseT/Full 100baseT/Half 100baseT/Full 1000baseT/Full Link partner advertised pause frame use: No Link partner advertised auto-negotiation: No Link partner advertised FEC modes: Not reported Speed: 1000Mb/s Duplex: Full Port: Twisted Pair PHYAD: 4 Transceiver: internal Auto-negotiation: on MDI-X: Unknown Supports Wake-on: d Wake-on: d Current message level: 0x00000000 (0) Link detected: yes ethtool after: root@OpenWrt:/# ethtool eth1 Settings for eth1: Supported ports: [ TP MII ] Supported link modes: 10baseT/Half 10baseT/Full 100baseT/Half 100baseT/Full 1000baseT/Full 1000baseX/Full Supported pause frame use: Symmetric Receive-only Supports auto-negotiation: Yes Supported FEC modes: Not reported Advertised link modes: 10baseT/Half 10baseT/Full 100baseT/Half 100baseT/Full 1000baseT/Full 1000baseX/Full Advertised pause frame use: Symmetric Receive-only Advertised auto-negotiation: Yes Advertised FEC modes: Not reported Link partner advertised link modes: 10baseT/Half 10baseT/Full 100baseT/Half 100baseT/Full 1000baseT/Full Link partner advertised pause frame use: Symmetric Receive-only Link partner advertised auto-negotiation: Yes Link partner advertised FEC modes: Not reported Speed: 1000Mb/s Duplex: Full Port: Twisted Pair PHYAD: 4 Transceiver: external Auto-negotiation: on MDI-X: off (auto) Supports Wake-on: d Wake-on: d Current message level: 0x00000000 (0) Link detected: yes Signed-off-by: Robert Marko <robert.marko@sartura.hr>
* ipq40xx: net: ethernet: edma: fix link detectionRobert Marko2020-12-231-0/+4
| | | | | | | PHY needs to be soft reset before starting it from ethernet driver as AR40xx calibration will leave it in unwanted state. Signed-off-by: Robert Marko <robert.marko@sartura.hr>
* ipq40xx: net: phy: ar40xx: remove PHY handlingRobert Marko2020-12-231-225/+16
| | | | | | | | | | | | | | | Since we now have proper PHY driver for the QCA807x PHY-s, lets remove PHY handling from AR40xx. This removes PHY driver, PHY GPIO driver and PHY init code. AR40xx still needs to handle PSGMII calibration as that requires R/W from the switch, so I am unable to move it into PHY driver. This also converted the AR40xx driver to use OF_MDIO to find the MDIO bus as it now cant be set through the PHY driver. So lets depend on OF_MDIO in KConfig. Signed-off-by: Robert Marko <robert.marko@sartura.hr>
* ipq40xx: add Qualcomm QCA807x driverRobert Marko2020-12-231-0/+828
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds driver for the Qualcomm QCA8072 and QCA8075 PHY-s. They are 2 or 5 port IEEE 802.3 clause 22 compliant 10BASE-Te, 100BASE-TX and 1000BASE-T PHY-s. They feature 2 SerDes, one for PSGMII or QSGMII connection with MAC, while second one is SGMII for connection to MAC or fiber. Both models have a combo port that supports 1000BASE-X and 100BASE-FX fiber. Each PHY inside of QCA807x series has 2 digitally controlled output only pins that natively drive LED-s. But some vendors used these to driver generic LED-s controlled by user space, so lets enable registering each PHY as GPIO controller and add driver for it. This also adds the ability to specify DT properties so that 1000 Base-T LED will also be lit up for 100 and 10 Base connections. This is usually done by U-boot, but boards running mainline U-boot are not configuring this yet. These PHY-s are commonly used in Qualcomm IPQ40xx, IPQ60xx and IPQ807x boards. Signed-off-by: Robert Marko <robert.marko@sartura.hr>
* ipq40xx: edma: convert to of_mdio_find_bus()Robert Marko2020-12-231-21/+4
| | | | | | | | | | | | | | With the reworked MDIO driver, EDMA will fail to get the MII BUS as it used the MII BUS stored inside the MDIO structure private data. This obviously does not work with the modernized driver, so lets switch to using a purpose build of_mdio_find_bus() which will return the MII BUS and only requires the MDIO node to be passed. This is easy as we already have the node parsed. Also, since we now require OF_MDIO add that as dependency. Signed-off-by: Robert Marko <robert.marko@sartura.hr>
* ipq40xx: revert usage of VLAN S-TAGDavid Bauer2020-12-142-37/+9
| | | | | | | | | | | This reverts the usage of the S-Tag for separating LAN and WAN port on the embedded switch. Many users complained about not being able to manage C-Tag addition / removal on the switch as well as degraded performance. Fixes: commit 9da2b567605b ("ipq40xx: fix ethernet vlan double tagging") Signed-off-by: David Bauer <mail@david-bauer.net>
* ipq40xx: enable RX hash / CTAG TX offloading for single-phyDavid Bauer2020-11-011-0/+9
| | | | | | | | | | | | This re-enables offloading features disabled by commit 9da2b567605b ("ipq40xx: fix ethernet vlan double tagging"). Single-PHY devices use port-based VLANs on the switch, therefore no S-TAG magic is involved here. Re-enabling these features restores throughput back to 950 Mbit/s. Reported-by: Jannis Pinter <jannis@pinterjann.is> Signed-off-by: David Bauer <mail@david-bauer.net>
* ipq40xx: remove support for kernel 4.19Adrian Schmutzler2020-10-198-0/+7229
The target uses 5.4 as default kernel since 03/2020. Kernel 4.19 support is not really maintained anymore, it does not seem to be needed, and removing it will make upcoming driver updates easier. Thus, remove it. Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>