| Commit message (Collapse) | Author | Age | Files | Lines |
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Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
SVN-Revision: 36453
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Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
SVN-Revision: 36363
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Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
SVN-Revision: 36332
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Update ehci/ohci driver registration to conform to the new platform
drivers.
This fixes missing USB host support in 3.8.x
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 36309
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init and is useful only for testing
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
SVN-Revision: 36241
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Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
SVN-Revision: 36215
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Also refresh the related generic/platform patches.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
SVN-Revision: 36039
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memory pressure
SVN-Revision: 35953
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xmit handler
SVN-Revision: 35952
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SVN-Revision: 35951
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descriptor entries
SVN-Revision: 35950
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SVN-Revision: 35949
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SVN-Revision: 35943
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When an rx interrupt comes in, rx interrupts are disabled and NAPI
polling is scheduled. During the NAPI poll, the driver first processes
received frames in the ring, then fills the dma descriptor slots with
new buffers and calls tx complete, before finally re-enabling rx
interrupts and completing NAPI (if below the budget).
If the hardware rx queue overflows before the napi complete is called,
the hardware will not throw any further rx interrupts and rx processing
stops completely.
Fix this by keeping NAPI polling scheduled until it completes a poll
without receiving any packets, and also handle NAPI completion before
refilling rx or completing tx.
SVN-Revision: 35942
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SVN-Revision: 35941
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performance
SVN-Revision: 35917
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SVN-Revision: 35916
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ethernet cpu affinity (improves lan<->wlan bridging performance)
SVN-Revision: 35915
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SVN-Revision: 35908
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It breaks PCIe IRQ mapping and possibly other things
SVN-Revision: 35842
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Required to actually be able to mount squashfs xz compressed
filesystems.
Signed-off-by: Florian Fainelli <florian@openwrt.org>
SVN-Revision: 35156
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This makes the PCI bus topology more standard for devices behind a bridge
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 35079
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This makes the PCI bus topology more standard for devices behind a bridge
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 35078
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L2 cache via L2X0 cache controller available on some ARM boards can
provide a performance boost in some situations but decrease performance
in others. This adds a kernel cmdline to disable L2X0 for cns3xxx based
boards.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 34874
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Signed-off-by: Florian Fainelli <florian@openwrt.org>
SVN-Revision: 34568
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function. This removes those from the dwc_otg driver and removes the patch
that comments out the linkage of udc-core so that the dwc_otg driver can
co-exist happily with other USB Device Controllers.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Florian Fainelli <florian@openwrt.org>
SVN-Revision: 34475
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Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Florian Fainelli <florian@openwrt.org>
SVN-Revision: 34474
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The removed symbols are present in the generic configuration.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
SVN-Revision: 34403
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SVN-Revision: 34174
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SVN-Revision: 34173
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SVN-Revision: 34169
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SVN-Revision: 34168
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SVN-Revision: 34167
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boards with old u-boot
SVN-Revision: 34163
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SVN-Revision: 34162
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SVN-Revision: 34161
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Combine two pcie patches (2nd patch undid the 1st patch) together
and refresh the other affected patches
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 34132
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SVN-Revision: 34120
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Many Laguna products have on-board GPS with Pulse-per-second (PPS)
support. This patch adds kernel support (statically) and adds
the platform data in laguna board support.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 34115
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SMP already selects HAVE_ARM_TWD and HAVE_ARM_SCU,
ARCH_CNS3XXX already selects MIGHT_HAVE_PCI
SVN-Revision: 34114
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SVN-Revision: 34113
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SVN-Revision: 34102
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SVN-Revision: 34101
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SVN-Revision: 34095
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SVN-Revision: 34094
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ARM Linux PCI/PCIe hardware intialization needs to occur before device_init
as it does not support hotplug. I have modeled the cns3xxx PCIe init after
other ARM platforms. Registering it early resolves resource issues occuring
during bus enumeration that occur when a device driver is linked static in
the kernel.
Instead of passing in a bitmask to enable the 2 available ports, link detect
is used to enable ports that have a valid link.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 34044
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Update header file appropriately and disable read for ownership
Note that the FIQ support implements a workaround that provides a performance
boost over the traditional upstream workaround which ensures cache lines
are exclusive on driver CPU using 'read for ownership'.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
target/linux/cns3xxx/config-3.3 | 2 +-
target/linux/cns3xxx/patches-3.3/460-cns3xxx_fiq_support.patch | 9 ++++-----
2 files changed, 5 insertions(+), 6 deletions(-)
SVN-Revision: 33827
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SVN-Revision: 33825
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Properly terminate the correct platform resource for laguna UARTs
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 33721
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level monitoring and control of Gateworks boards. It is used on several product families spanning several different target architectures (ixp4xx, cns3xxx, davinci).
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 33720
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