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-rw-r--r--toolchain/gcc/patches/10.1.0/110-Fix-MIPS-PR-84790.patch20
1 files changed, 20 insertions, 0 deletions
diff --git a/toolchain/gcc/patches/10.1.0/110-Fix-MIPS-PR-84790.patch b/toolchain/gcc/patches/10.1.0/110-Fix-MIPS-PR-84790.patch
new file mode 100644
index 0000000000..c7e60e3157
--- /dev/null
+++ b/toolchain/gcc/patches/10.1.0/110-Fix-MIPS-PR-84790.patch
@@ -0,0 +1,20 @@
+Fix https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84790.
+MIPS16 functions have a static assembler prologue which clobbers
+registers v0 and v1. Add these register clobbers to function call
+instructions.
+
+--- a/gcc/config/mips/mips.c
++++ b/gcc/config/mips/mips.c
+@@ -3131,6 +3131,12 @@ mips_emit_call_insn (rtx pattern, rtx or
+ emit_insn (gen_update_got_version ());
+ }
+
++ if (TARGET_MIPS16 && TARGET_USE_GOT)
++ {
++ clobber_reg (&CALL_INSN_FUNCTION_USAGE (insn), MIPS16_PIC_TEMP);
++ clobber_reg (&CALL_INSN_FUNCTION_USAGE (insn), MIPS_PROLOGUE_TEMP (word_mode));
++ }
++
+ if (TARGET_MIPS16
+ && TARGET_EXPLICIT_RELOCS
+ && TARGET_CALL_CLOBBERED_GP)