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-rw-r--r--target/linux/lantiq/patches-5.15/0001-MIPS-lantiq-add-pcie-driver.patch2
-rw-r--r--target/linux/lantiq/patches-5.15/0151-lantiq-ifxmips_pcie-use-of.patch36
2 files changed, 25 insertions, 13 deletions
diff --git a/target/linux/lantiq/patches-5.15/0001-MIPS-lantiq-add-pcie-driver.patch b/target/linux/lantiq/patches-5.15/0001-MIPS-lantiq-add-pcie-driver.patch
index bf3d848f41d..1c5f69131e4 100644
--- a/target/linux/lantiq/patches-5.15/0001-MIPS-lantiq-add-pcie-driver.patch
+++ b/target/linux/lantiq/patches-5.15/0001-MIPS-lantiq-add-pcie-driver.patch
@@ -3913,6 +3913,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+#define IFX_RCU_AHB_BE_PCIE_M 0x00000001 /* Configure AHB master port that connects to PCIe RC in big endian */
+#define IFX_RCU_AHB_BE_PCIE_S 0x00000010 /* Configure AHB slave port that connects to PCIe RC in little endian */
+#define IFX_RCU_AHB_BE_XBAR_M 0x00000002 /* Configure AHB master port that connects to XBAR in big endian */
++#define IFX_RCU_AHB_BE_XBAR_S 0x00000008 /* Configure AHB slave port that connects to XBAR in big endian */
+#define CONFIG_IFX_PCIE_PHY_36MHZ_MODE
+
+#define IFX_PMU1_MODULE_PCIE_PHY (0)
@@ -4159,7 +4160,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+}
+
+#endif /* IFXMIPS_PCIE_VR9_H */
-+
--- a/arch/mips/pci/pci-legacy.c
+++ b/arch/mips/pci/pci-legacy.c
@@ -305,3 +305,30 @@ char *__init pcibios_setup(char *str)
diff --git a/target/linux/lantiq/patches-5.15/0151-lantiq-ifxmips_pcie-use-of.patch b/target/linux/lantiq/patches-5.15/0151-lantiq-ifxmips_pcie-use-of.patch
index 0b99b91bd91..a11ec3ec984 100644
--- a/target/linux/lantiq/patches-5.15/0151-lantiq-ifxmips_pcie-use-of.patch
+++ b/target/linux/lantiq/patches-5.15/0151-lantiq-ifxmips_pcie-use-of.patch
@@ -39,7 +39,7 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
#include "ifxmips_pcie.h"
#include "ifxmips_pcie_reg.h"
-@@ -40,6 +47,10 @@
+@@ -40,6 +47,11 @@
static DEFINE_SPINLOCK(ifx_pcie_lock);
u32 g_pcie_debug_flag = PCIE_MSG_ANY & (~PCIE_MSG_CFG);
@@ -47,10 +47,11 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
+static struct phy *ltq_pcie_phy;
+static struct reset_control *ltq_pcie_reset;
+static struct regmap *ltq_rcu_regmap;
++static bool switch_pcie_endianess;
static ifx_pcie_irq_t pcie_irqs[IFX_PCIE_CORE_NR] = {
{
-@@ -82,6 +93,22 @@ void ifx_pcie_debug(const char *fmt, ...
+@@ -82,6 +94,22 @@ void ifx_pcie_debug(const char *fmt, ...
printk("%s", buf);
}
@@ -73,7 +74,7 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
static inline int pcie_ltssm_enable(int pcie_port)
{
-@@ -988,10 +1015,22 @@ int ifx_pcie_bios_plat_dev_init(struct
+@@ -988,10 +1016,26 @@ int ifx_pcie_bios_plat_dev_init(struct
static int
pcie_rc_initialize(int pcie_port)
{
@@ -88,6 +89,10 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
+#ifdef CONFIG_IFX_PCIE_HW_SWAP
+ regmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_PCIE_S,
+ IFX_RCU_AHB_BE_PCIE_S);
++ if (switch_pcie_endianess) {
++ regmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_XBAR_S,
++ IFX_RCU_AHB_BE_XBAR_S);
++ }
+#else
+ regmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_PCIE_S,
+ 0x0);
@@ -98,7 +103,7 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
pcie_ep_gpio_rst_init(pcie_port);
-@@ -1000,26 +1039,21 @@ pcie_rc_initialize(int pcie_port)
+@@ -1000,26 +1044,21 @@ pcie_rc_initialize(int pcie_port)
* reset PCIe PHY will solve this issue
*/
for (i = 0; i < IFX_PCIE_PHY_LOOP_CNT; i++) {
@@ -135,7 +140,7 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
/* Enable PCIe PHY and Clock */
pcie_core_pmu_setup(pcie_port);
-@@ -1035,6 +1069,10 @@ pcie_rc_initialize(int pcie_port)
+@@ -1035,6 +1074,10 @@ pcie_rc_initialize(int pcie_port)
/* Once link is up, break out */
if (pcie_app_loigc_setup(pcie_port) == 0)
break;
@@ -146,7 +151,7 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
}
if (i >= IFX_PCIE_PHY_LOOP_CNT) {
printk(KERN_ERR "%s link up failed!!!!!\n", __func__);
-@@ -1045,17 +1083,67 @@ pcie_rc_initialize(int pcie_port)
+@@ -1045,17 +1088,74 @@ pcie_rc_initialize(int pcie_port)
return 0;
}
@@ -199,6 +204,13 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
+ return PTR_ERR(ltq_pcie_reset);
+ }
+
++ if (of_property_read_bool(node, "lantiq,switch-pcie-endianess")) {
++ switch_pcie_endianess = true;
++ dev_info(&pdev->dev, "switch pcie endianess requested\n");
++ } else {
++ switch_pcie_endianess = false;
++ }
++
+ ltq_rcu_regmap = syscon_regmap_lookup_by_phandle(node, "lantiq,rcu");
+ if (IS_ERR(ltq_rcu_regmap))
+ return PTR_ERR(ltq_rcu_regmap);
@@ -216,7 +228,7 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
for (pcie_port = startup_port; pcie_port < IFX_PCIE_CORE_NR; pcie_port++){
if (pcie_rc_initialize(pcie_port) == 0) {
IFX_PCIE_PRINT(PCIE_MSG_INIT, "%s: ifx_pcie_cfg_base 0x%p\n",
-@@ -1067,6 +1155,7 @@ static int __init ifx_pcie_bios_init(voi
+@@ -1067,6 +1167,7 @@ static int __init ifx_pcie_bios_init(voi
return -ENOMEM;
}
ifx_pcie_controller[pcie_port].pcic.io_map_base = (unsigned long)io_map_base;
@@ -224,7 +236,7 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
register_pci_controller(&ifx_pcie_controller[pcie_port].pcic);
/* XXX, clear error status */
-@@ -1083,6 +1172,30 @@ static int __init ifx_pcie_bios_init(voi
+@@ -1083,6 +1184,30 @@ static int __init ifx_pcie_bios_init(voi
return 0;
}
@@ -266,7 +278,7 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
#define IFX_REG_R32 ltq_r32
#define IFX_REG_W32 ltq_w32
#define CONFIG_IFX_PCIE_HW_SWAP
-@@ -53,21 +51,6 @@
+@@ -54,21 +52,6 @@
#define OUT ((volatile u32*)(IFX_GPIO + 0x0070))
@@ -288,7 +300,7 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
static inline void pcie_ahb_pmu_setup(void)
{
/* Enable AHB bus master/slave */
-@@ -79,24 +62,6 @@ static inline void pcie_ahb_pmu_setup(vo
+@@ -80,24 +63,6 @@ static inline void pcie_ahb_pmu_setup(vo
//AHBS_PMU_SETUP(IFX_PMU_ENABLE);
}
@@ -313,7 +325,7 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
static inline void pcie_phy_pmu_enable(int pcie_port)
{
struct clk *clk;
-@@ -115,17 +80,6 @@ static inline void pcie_phy_pmu_disable(
+@@ -116,17 +81,6 @@ static inline void pcie_phy_pmu_disable(
// PCIE_PHY_PMU_SETUP(IFX_PMU_DISABLE);
}
@@ -331,7 +343,7 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
static inline void pcie_pdi_pmu_enable(int pcie_port)
{
/* Enable PDI to access PCIe PHY register */
-@@ -135,65 +89,6 @@ static inline void pcie_pdi_pmu_enable(i
+@@ -136,65 +90,6 @@ static inline void pcie_pdi_pmu_enable(i
//PDI_PMU_SETUP(IFX_PMU_ENABLE);
}
generated by cgit v1.2.3 (git 2.25.1) at 2026-01-15 21:07:59 +0000