diff options
Diffstat (limited to 'target')
3 files changed, 182 insertions, 0 deletions
diff --git a/target/linux/realtek/dts-5.10/rtl8382_panasonic_m16eg-pn28160k.dts b/target/linux/realtek/dts-5.10/rtl8382_panasonic_m16eg-pn28160k.dts new file mode 100644 index 0000000000..c3b29a87ff --- /dev/null +++ b/target/linux/realtek/dts-5.10/rtl8382_panasonic_m16eg-pn28160k.dts @@ -0,0 +1,171 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "rtl838x.dtsi" +#include "rtl83xx_panasonic_mxxeg-pn28xx0k.dtsi" + +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + compatible = "panasonic,m16eg-pn28160k", "realtek,rtl8382-soc"; + model = "Panasonic Switch-M16eG PN28160K"; + + aliases { + led-boot = &led_status_eco_green; + led-failsafe = &led_status_eco_amber; + led-running = &led_status_eco_green; + led-upgrade = &led_status_eco_green; + }; + + /* + * sfp0/1 are "combo" port with each TP port (23/24), and they are + * connected to the RTL8218FB. Currently, there is no support for + * the chip and only TP ports work by the RTL8218D support. + */ + sfp0: sfp-p23 { + compatible = "sff,sfp"; + i2c-bus = <&i2c0>; + tx-fault-gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; + tx-disable-gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; + los-gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>; + }; + + sfp1: sfp-p24 { + compatible = "sff,sfp"; + i2c-bus = <&i2c1>; + tx-fault-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; + tx-disable-gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; + mod-def0-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>; + los-gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + }; +}; + +&leds { + led_status_eco_amber: led-5 { + label = "amber:status_eco"; + gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_AMBER>; + function = LED_FUNCTION_STATUS; + function-enumerator = <1>; + }; + + led_status_eco_green: led-6 { + label = "green:status_eco"; + gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_STATUS; + function-enumerator = <2>; + }; +}; + +&i2c_gpio_0 { + scl-gpios = <&gpio0 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + +&i2c_gpio_1 { + scl-gpios = <&gpio0 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio0 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + +&gpio2 { + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio0>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + + /* + * GPIO12 (IO1_4): RTL8218FB + * + * This GPIO pin should be specified as "reset-gpio" in mdio node, but + * RTL8218FB phy won't be configured on RTL8218D support in the current + * phy driver. So, ethernet ports on the phy will be broken after hard- + * resetting. + * (RTL8218FB phy will be detected as RTL8218D by the phy driver) + * At the moment, configure this GPIO pin as gpio-hog to avoid breaking + * by resetting. + */ + ext_switch_reset { + gpio-hog; + gpios = <12 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "ext-switch-reset"; + }; +}; + +&i2c_switch { + i2c0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + i2c1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; +}; + +ðernet0 { + mdio-bus { + compatible = "realtek,rtl838x-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + INTERNAL_PHY(8) + INTERNAL_PHY(9) + INTERNAL_PHY(10) + INTERNAL_PHY(11) + INTERNAL_PHY(12) + INTERNAL_PHY(13) + INTERNAL_PHY(14) + INTERNAL_PHY(15) + + /* RTL8218FB */ + EXTERNAL_PHY(16) + EXTERNAL_PHY(17) + EXTERNAL_PHY(18) + EXTERNAL_PHY(19) + EXTERNAL_PHY(20) + EXTERNAL_PHY(21) + EXTERNAL_PHY(22) + EXTERNAL_PHY(23) + }; +}; + +&switch0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + SWITCH_PORT(8, 1, internal) + SWITCH_PORT(9, 2, internal) + SWITCH_PORT(10, 3, internal) + SWITCH_PORT(11, 4, internal) + SWITCH_PORT(12, 5, internal) + SWITCH_PORT(13, 6, internal) + SWITCH_PORT(14, 7, internal) + SWITCH_PORT(15, 8, internal) + + SWITCH_PORT(16, 9, qsgmii) + SWITCH_PORT(17, 10, qsgmii) + SWITCH_PORT(18, 11, qsgmii) + SWITCH_PORT(19, 12, qsgmii) + SWITCH_PORT(20, 13, qsgmii) + SWITCH_PORT(21, 14, qsgmii) + SWITCH_PORT(22, 15, qsgmii) + SWITCH_PORT(23, 16, qsgmii) + + port@28 { + ethernet = <ðernet0>; + reg = <28>; + phy-mode = "internal"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; +}; diff --git a/target/linux/realtek/dts-5.10/rtl83xx_panasonic_mxxeg-pn28xx0k.dtsi b/target/linux/realtek/dts-5.10/rtl83xx_panasonic_mxxeg-pn28xx0k.dtsi index 48aa1849d6..fb2aa18d21 100644 --- a/target/linux/realtek/dts-5.10/rtl83xx_panasonic_mxxeg-pn28xx0k.dtsi +++ b/target/linux/realtek/dts-5.10/rtl83xx_panasonic_mxxeg-pn28xx0k.dtsi @@ -94,6 +94,7 @@ /* * GPIO14 (IO1_6): Shift Register RESET (port LED) * - Switch-M8eG PN28080K: 3x 74HC164 + * - Switch-M16eG PN28160K: 4x 74HC164 * - Switch-M24eG PN28240K: 6x 74HC164 * - Switch-M48eG PN28480K: 12x 74HC164 */ diff --git a/target/linux/realtek/image/rtl838x.mk b/target/linux/realtek/image/rtl838x.mk index 60eda5359d..cbd41ce841 100644 --- a/target/linux/realtek/image/rtl838x.mk +++ b/target/linux/realtek/image/rtl838x.mk @@ -138,6 +138,16 @@ define Device/netgear_gs310tp-v1 endef TARGET_DEVICES += netgear_gs310tp-v1 +define Device/panasonic_m16eg-pn28160k + SOC := rtl8382 + IMAGE_SIZE := 16384k + DEVICE_VENDOR := Panasonic + DEVICE_MODEL := Switch-M16eG + DEVICE_VARIANT := PN28160K + DEVICE_PACKAGES := kmod-i2c-mux-pca954x +endef +TARGET_DEVICES += panasonic_m16eg-pn28160k + define Device/panasonic_m8eg-pn28080k SOC := rtl8380 IMAGE_SIZE := 16384k |