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-rw-r--r--target/linux/ar71xx/patches-4.4/106-01-MIPS-ath79-fix-AR724X_PLL_REG_PCIE_CONFIG-offset.patch29
-rw-r--r--target/linux/ar71xx/patches-4.4/106-02-MIPS-ath79-do-AR724x-PCIe-root-complex-init.patch113
-rw-r--r--target/linux/ar71xx/patches-4.4/601-MIPS-ath79-add-more-register-defines.patch16
-rw-r--r--target/linux/ar71xx/patches-4.4/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch22
-rw-r--r--target/linux/ar71xx/patches-4.4/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch16
-rw-r--r--target/linux/ar71xx/patches-4.4/622-MIPS-ath79-add-more-register-defines-for-QCA956x-SoC.patch4
-rw-r--r--target/linux/ar71xx/patches-4.4/820-MIPS-ath79-add_gpio_function2_setup.patch4
-rw-r--r--target/linux/ar71xx/patches-4.4/920-usb-chipidea-AR933x-platform-support.patch4
8 files changed, 175 insertions, 33 deletions
diff --git a/target/linux/ar71xx/patches-4.4/106-01-MIPS-ath79-fix-AR724X_PLL_REG_PCIE_CONFIG-offset.patch b/target/linux/ar71xx/patches-4.4/106-01-MIPS-ath79-fix-AR724X_PLL_REG_PCIE_CONFIG-offset.patch
new file mode 100644
index 0000000000..e785b30eff
--- /dev/null
+++ b/target/linux/ar71xx/patches-4.4/106-01-MIPS-ath79-fix-AR724X_PLL_REG_PCIE_CONFIG-offset.patch
@@ -0,0 +1,29 @@
+From 0f15814bcdf59f10b708a3fba636acb089e9a4f1 Mon Sep 17 00:00:00 2001
+From: Mathias Kresin <dev@kresin.me>
+Date: Thu, 30 Mar 2017 15:34:39 +0200
+Subject: [PATCH] MIPS: ath79: fix AR724X_PLL_REG_PCIE_CONFIG offset
+
+According to the QCA u-boot source the "PCIE Phase Lock Loop
+Configuration (PCIE_PLL_CONFIG)" register is for all SoCs except the
+QCA955X and QCA956X at offset 0x10.
+
+Since the PCIE PLL config register is only defined for the AR724x fix
+only this value. The value is wrong since the day it was added and isn't
+yet used by any driver.
+
+Signed-off-by: Mathias Kresin <dev@kresin.me>
+---
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -167,7 +167,7 @@
+ #define AR71XX_AHB_DIV_MASK 0x7
+
+ #define AR724X_PLL_REG_CPU_CONFIG 0x00
+-#define AR724X_PLL_REG_PCIE_CONFIG 0x18
++#define AR724X_PLL_REG_PCIE_CONFIG 0x10
+
+ #define AR724X_PLL_FB_SHIFT 0
+ #define AR724X_PLL_FB_MASK 0x3ff
diff --git a/target/linux/ar71xx/patches-4.4/106-02-MIPS-ath79-do-AR724x-PCIe-root-complex-init.patch b/target/linux/ar71xx/patches-4.4/106-02-MIPS-ath79-do-AR724x-PCIe-root-complex-init.patch
new file mode 100644
index 0000000000..d3948b8353
--- /dev/null
+++ b/target/linux/ar71xx/patches-4.4/106-02-MIPS-ath79-do-AR724x-PCIe-root-complex-init.patch
@@ -0,0 +1,113 @@
+From 460f382c278fe66059a773c41cbcd0db86d53983 Mon Sep 17 00:00:00 2001
+From: Mathias Kresin <dev@kresin.me>
+Date: Thu, 13 Apr 2017 09:47:42 +0200
+Subject: [PATCH] MIPS: pci-ar724x: get PCIe controller out of reset
+
+The ar724x pci driver expects the PCIe controller to be brought out of
+reset by the bootloader.
+
+At least the AVM Fritz 300E bootloader doesn't take care of releasing
+the different PCIe controller related resets which causes an endless
+hang as soon as either the PCIE Reset register (0x180f0018) or the PCI
+Application Control register (0x180f0000) is read from.
+
+Do the full "PCIE Root Complex Initialization Sequence" if the PCIe
+host controller is still in reset during probing.
+
+The QCA u-boot sleeps 10ms after the PCIE Application Control bit is
+set to ready. It has been shown that 10ms might not be enough time if
+PCIe should be used right after setting the bit. During my tests it
+took up to 20ms till the link was up. Giving the link up to 100ms
+should work for all cases.
+
+Signed-off-by: Mathias Kresin <dev@kresin.me>
+---
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 3 ++
+ arch/mips/pci/pci-ar724x.c | 42 ++++++++++++++++++++++++++
+ 2 files changed, 45 insertions(+)
+
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -169,6 +169,9 @@
+ #define AR724X_PLL_REG_CPU_CONFIG 0x00
+ #define AR724X_PLL_REG_PCIE_CONFIG 0x10
+
++#define AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS BIT(16)
++#define AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET BIT(25)
++
+ #define AR724X_PLL_FB_SHIFT 0
+ #define AR724X_PLL_FB_MASK 0x3ff
+ #define AR724X_PLL_REF_DIV_SHIFT 10
+--- a/arch/mips/pci/pci-ar724x.c
++++ b/arch/mips/pci/pci-ar724x.c
+@@ -12,14 +12,18 @@
+ #include <linux/irq.h>
+ #include <linux/pci.h>
+ #include <linux/module.h>
++#include <linux/delay.h>
+ #include <linux/platform_device.h>
+ #include <asm/mach-ath79/ath79.h>
+ #include <asm/mach-ath79/ar71xx_regs.h>
+
++#define AR724X_PCI_REG_APP 0x0
+ #define AR724X_PCI_REG_RESET 0x18
+ #define AR724X_PCI_REG_INT_STATUS 0x4c
+ #define AR724X_PCI_REG_INT_MASK 0x50
+
++#define AR724X_PCI_APP_LTSSM_ENABLE BIT(0)
++
+ #define AR724X_PCI_RESET_LINK_UP BIT(0)
+
+ #define AR724X_PCI_INT_DEV0 BIT(14)
+@@ -325,6 +329,37 @@ static void ar724x_pci_irq_init(struct a
+ apc);
+ }
+
++static void ar724x_pci_hw_init(struct ar724x_pci_controller *apc)
++{
++ u32 ppl, app;
++ int wait = 0;
++
++ /* deassert PCIe host controller and PCIe PHY reset */
++ ath79_device_reset_clear(AR724X_RESET_PCIE);
++ ath79_device_reset_clear(AR724X_RESET_PCIE_PHY);
++
++ /* remove the reset of the PCIE PLL */
++ ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
++ ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET;
++ ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
++
++ /* deassert bypass for the PCIE PLL */
++ ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
++ ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS;
++ ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
++
++ /* set PCIE Application Control to ready */
++ app = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_APP);
++ app |= AR724X_PCI_APP_LTSSM_ENABLE;
++ __raw_writel(app, apc->ctrl_base + AR724X_PCI_REG_APP);
++
++ /* wait up to 100ms for PHY link up */
++ do {
++ mdelay(10);
++ wait++;
++ } while (wait < 10 && !ar724x_pci_check_link(apc));
++}
++
+ static int ar724x_pci_probe(struct platform_device *pdev)
+ {
+ struct ar724x_pci_controller *apc;
+@@ -383,6 +418,13 @@ static int ar724x_pci_probe(struct platf
+ apc->pci_controller.io_resource = &apc->io_res;
+ apc->pci_controller.mem_resource = &apc->mem_res;
+
++ /*
++ * Do the full PCIE Root Complex Initialization Sequence if the PCIe
++ * host controller is in reset.
++ */
++ if (ath79_reset_rr(AR724X_RESET_REG_RESET_MODULE) & AR724X_RESET_PCIE)
++ ar724x_pci_hw_init(apc);
++
+ apc->link_up = ar724x_pci_check_link(apc);
+ if (!apc->link_up)
+ dev_warn(&pdev->dev, "PCIe link is down\n");
diff --git a/target/linux/ar71xx/patches-4.4/601-MIPS-ath79-add-more-register-defines.patch b/target/linux/ar71xx/patches-4.4/601-MIPS-ath79-add-more-register-defines.patch
index e4d82acf5e..d0f5b78901 100644
--- a/target/linux/ar71xx/patches-4.4/601-MIPS-ath79-add-more-register-defines.patch
+++ b/target/linux/ar71xx/patches-4.4/601-MIPS-ath79-add-more-register-defines.patch
@@ -66,9 +66,9 @@
+#define AR71XX_ETH1_PLL_SHIFT 19
+
#define AR724X_PLL_REG_CPU_CONFIG 0x00
- #define AR724X_PLL_REG_PCIE_CONFIG 0x18
+ #define AR724X_PLL_REG_PCIE_CONFIG 0x10
-@@ -193,6 +212,8 @@
+@@ -196,6 +215,8 @@
#define AR724X_DDR_DIV_SHIFT 22
#define AR724X_DDR_DIV_MASK 0x3
@@ -77,7 +77,7 @@
#define AR913X_PLL_REG_CPU_CONFIG 0x00
#define AR913X_PLL_REG_ETH_CONFIG 0x04
#define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14
-@@ -205,6 +226,9 @@
+@@ -208,6 +229,9 @@
#define AR913X_AHB_DIV_SHIFT 19
#define AR913X_AHB_DIV_MASK 0x1
@@ -87,7 +87,7 @@
#define AR933X_PLL_CPU_CONFIG_REG 0x00
#define AR933X_PLL_CLOCK_CTRL_REG 0x08
-@@ -226,6 +250,8 @@
+@@ -229,6 +253,8 @@
#define AR934X_PLL_CPU_CONFIG_REG 0x00
#define AR934X_PLL_DDR_CONFIG_REG 0x04
#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08
@@ -96,7 +96,7 @@
#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
-@@ -258,9 +284,13 @@
+@@ -261,9 +287,13 @@
#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
@@ -110,7 +110,7 @@
#define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
#define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
-@@ -385,16 +415,83 @@
+@@ -388,16 +418,83 @@
#define AR913X_RESET_USB_HOST BIT(5)
#define AR913X_RESET_USB_PHY BIT(4)
@@ -194,7 +194,7 @@
#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
-@@ -536,8 +633,22 @@
+@@ -539,8 +636,22 @@
#define AR71XX_GPIO_REG_INT_ENABLE 0x24
#define AR71XX_GPIO_REG_FUNC 0x28
@@ -217,7 +217,7 @@
#define AR71XX_GPIO_COUNT 16
#define AR7240_GPIO_COUNT 18
#define AR7241_GPIO_COUNT 20
-@@ -567,4 +678,235 @@
+@@ -570,4 +681,235 @@
#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
#define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
diff --git a/target/linux/ar71xx/patches-4.4/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch b/target/linux/ar71xx/patches-4.4/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch
index 64ebf59366..d117f94021 100644
--- a/target/linux/ar71xx/patches-4.4/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch
+++ b/target/linux/ar71xx/patches-4.4/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch
@@ -459,7 +459,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
/*
* PLL block
*/
-@@ -286,6 +307,44 @@
+@@ -289,6 +310,44 @@
#define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL BIT(6)
@@ -504,7 +504,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
#define QCA955X_PLL_CPU_CONFIG_REG 0x00
#define QCA955X_PLL_DDR_CONFIG_REG 0x04
#define QCA955X_PLL_CLK_CTRL_REG 0x08
-@@ -362,6 +421,10 @@
+@@ -365,6 +424,10 @@
#define AR934X_RESET_REG_BOOTSTRAP 0xb0
#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
@@ -515,7 +515,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
#define QCA955X_RESET_REG_RESET_MODULE 0x1c
#define QCA955X_RESET_REG_BOOTSTRAP 0xb0
#define QCA955X_RESET_REG_EXT_INT_STATUS 0xac
-@@ -457,6 +520,27 @@
+@@ -460,6 +523,27 @@
#define AR934X_RESET_MBOX BIT(1)
#define AR934X_RESET_I2S BIT(0)
@@ -543,7 +543,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
#define QCA955X_RESET_HOST BIT(31)
#define QCA955X_RESET_SLIC BIT(30)
#define QCA955X_RESET_HDMA BIT(29)
-@@ -510,6 +594,13 @@
+@@ -513,6 +597,13 @@
#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
#define AR934X_BOOTSTRAP_DDR1 BIT(0)
@@ -557,7 +557,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
#define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4)
#define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
-@@ -530,6 +621,24 @@
+@@ -533,6 +624,24 @@
AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
AR934X_PCIE_WMAC_INT_PCIE_RC3)
@@ -582,7 +582,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
#define QCA955X_EXT_INT_WMAC_MISC BIT(0)
#define QCA955X_EXT_INT_WMAC_TX BIT(1)
#define QCA955X_EXT_INT_WMAC_RXLP BIT(2)
-@@ -572,6 +681,8 @@
+@@ -575,6 +684,8 @@
#define REV_ID_MAJOR_AR9341 0x0120
#define REV_ID_MAJOR_AR9342 0x1120
#define REV_ID_MAJOR_AR9344 0x2120
@@ -591,7 +591,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
#define REV_ID_MAJOR_QCA9556 0x0130
#define REV_ID_MAJOR_QCA9558 0x1130
-@@ -594,6 +705,8 @@
+@@ -597,6 +708,8 @@
#define AR934X_REV_ID_REVISION_MASK 0xf
@@ -600,7 +600,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
#define QCA955X_REV_ID_REVISION_MASK 0xf
/*
-@@ -641,6 +754,25 @@
+@@ -644,6 +757,25 @@
#define AR934X_GPIO_REG_OUT_FUNC5 0x40
#define AR934X_GPIO_REG_FUNC 0x6c
@@ -626,7 +626,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
#define QCA955X_GPIO_REG_OUT_FUNC0 0x2c
#define QCA955X_GPIO_REG_OUT_FUNC1 0x30
#define QCA955X_GPIO_REG_OUT_FUNC2 0x34
-@@ -655,6 +787,7 @@
+@@ -658,6 +790,7 @@
#define AR913X_GPIO_COUNT 22
#define AR933X_GPIO_COUNT 30
#define AR934X_GPIO_COUNT 23
@@ -634,7 +634,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
#define QCA955X_GPIO_COUNT 24
/*
-@@ -678,6 +811,24 @@
+@@ -681,6 +814,24 @@
#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
#define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
@@ -659,7 +659,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17)
#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16)
#define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13)
-@@ -884,6 +1035,16 @@
+@@ -887,6 +1038,16 @@
#define AR934X_ETH_CFG_RDV_DELAY_SHIFT 16
/*
diff --git a/target/linux/ar71xx/patches-4.4/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch b/target/linux/ar71xx/patches-4.4/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch
index d8bb248a14..1f3a19886d 100644
--- a/target/linux/ar71xx/patches-4.4/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch
+++ b/target/linux/ar71xx/patches-4.4/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch
@@ -522,7 +522,7 @@
* DDR_CTRL block
*/
#define AR71XX_DDR_REG_PCI_WIN0 0x7c
-@@ -382,6 +406,49 @@
+@@ -385,6 +409,49 @@
#define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
#define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
@@ -572,7 +572,7 @@
/*
* USB_CONFIG block
*/
-@@ -429,6 +496,11 @@
+@@ -432,6 +499,11 @@
#define QCA955X_RESET_REG_BOOTSTRAP 0xb0
#define QCA955X_RESET_REG_EXT_INT_STATUS 0xac
@@ -584,7 +584,7 @@
#define MISC_INT_ETHSW BIT(12)
#define MISC_INT_TIMER4 BIT(10)
#define MISC_INT_TIMER3 BIT(9)
-@@ -603,6 +675,8 @@
+@@ -606,6 +678,8 @@
#define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4)
@@ -593,7 +593,7 @@
#define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
#define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1)
#define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)
-@@ -670,6 +744,37 @@
+@@ -673,6 +747,37 @@
QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \
QCA955X_EXT_INT_PCIE_RC2_INT3)
@@ -631,7 +631,7 @@
#define REV_ID_MAJOR_MASK 0xfff0
#define REV_ID_MAJOR_AR71XX 0x00a0
#define REV_ID_MAJOR_AR913X 0x00b0
-@@ -685,6 +790,8 @@
+@@ -688,6 +793,8 @@
#define REV_ID_MAJOR_QCA9533_V2 0x0160
#define REV_ID_MAJOR_QCA9556 0x0130
#define REV_ID_MAJOR_QCA9558 0x1130
@@ -640,7 +640,7 @@
#define AR71XX_REV_ID_MINOR_MASK 0x3
#define AR71XX_REV_ID_MINOR_AR7130 0x0
-@@ -709,6 +816,8 @@
+@@ -712,6 +819,8 @@
#define QCA955X_REV_ID_REVISION_MASK 0xf
@@ -649,7 +649,7 @@
/*
* SPI block
*/
-@@ -781,6 +890,19 @@
+@@ -784,6 +893,19 @@
#define QCA955X_GPIO_REG_OUT_FUNC5 0x40
#define QCA955X_GPIO_REG_FUNC 0x6c
@@ -669,7 +669,7 @@
#define AR71XX_GPIO_COUNT 16
#define AR7240_GPIO_COUNT 18
#define AR7241_GPIO_COUNT 20
-@@ -789,6 +911,7 @@
+@@ -792,6 +914,7 @@
#define AR934X_GPIO_COUNT 23
#define QCA953X_GPIO_COUNT 18
#define QCA955X_GPIO_COUNT 24
diff --git a/target/linux/ar71xx/patches-4.4/622-MIPS-ath79-add-more-register-defines-for-QCA956x-SoC.patch b/target/linux/ar71xx/patches-4.4/622-MIPS-ath79-add-more-register-defines-for-QCA956x-SoC.patch
index 6573b298a5..cab2f6f9cb 100644
--- a/target/linux/ar71xx/patches-4.4/622-MIPS-ath79-add-more-register-defines-for-QCA956x-SoC.patch
+++ b/target/linux/ar71xx/patches-4.4/622-MIPS-ath79-add-more-register-defines-for-QCA956x-SoC.patch
@@ -11,7 +11,7 @@
#define QCA956X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
#define QCA956X_GMAC_SIZE 0x64
-@@ -411,6 +415,7 @@
+@@ -414,6 +418,7 @@
#define QCA956X_PLL_DDR_CONFIG_REG 0x08
#define QCA956X_PLL_DDR_CONFIG1_REG 0x0c
#define QCA956X_PLL_CLK_CTRL_REG 0x10
@@ -19,7 +19,7 @@
#define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
#define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
-@@ -1193,4 +1198,16 @@
+@@ -1196,4 +1201,16 @@
#define QCA955X_ETH_CFG_TXE_DELAY_MASK 0x3
#define QCA955X_ETH_CFG_TXE_DELAY_SHIFT 20
diff --git a/target/linux/ar71xx/patches-4.4/820-MIPS-ath79-add_gpio_function2_setup.patch b/target/linux/ar71xx/patches-4.4/820-MIPS-ath79-add_gpio_function2_setup.patch
index 4d72a6c67d..a773e57dec 100644
--- a/target/linux/ar71xx/patches-4.4/820-MIPS-ath79-add_gpio_function2_setup.patch
+++ b/target/linux/ar71xx/patches-4.4/820-MIPS-ath79-add_gpio_function2_setup.patch
@@ -48,7 +48,7 @@ functions on the Arduino Yun.
void __iomem *reg = ath79_gpio_get_function_reg();
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-@@ -862,6 +862,7 @@
+@@ -865,6 +865,7 @@
#define AR71XX_GPIO_REG_INT_PENDING 0x20
#define AR71XX_GPIO_REG_INT_ENABLE 0x24
#define AR71XX_GPIO_REG_FUNC 0x28
@@ -56,7 +56,7 @@ functions on the Arduino Yun.
#define AR934X_GPIO_REG_OUT_FUNC0 0x2c
#define AR934X_GPIO_REG_OUT_FUNC1 0x30
-@@ -986,6 +987,8 @@
+@@ -989,6 +990,8 @@
#define AR724X_GPIO_FUNC_UART_EN BIT(1)
#define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0)
diff --git a/target/linux/ar71xx/patches-4.4/920-usb-chipidea-AR933x-platform-support.patch b/target/linux/ar71xx/patches-4.4/920-usb-chipidea-AR933x-platform-support.patch
index 1aa4120624..1a78af0779 100644
--- a/target/linux/ar71xx/patches-4.4/920-usb-chipidea-AR933x-platform-support.patch
+++ b/target/linux/ar71xx/patches-4.4/920-usb-chipidea-AR933x-platform-support.patch
@@ -1,6 +1,6 @@
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-@@ -656,6 +656,7 @@
+@@ -659,6 +659,7 @@
#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18)
#define AR933X_BOOTSTRAP_EEPBUSY BIT(4)
@@ -8,7 +8,7 @@
#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
-@@ -685,6 +686,8 @@
+@@ -688,6 +689,8 @@
#define QCA956X_BOOTSTRAP_REF_CLK_40 BIT(2)