diff options
Diffstat (limited to 'target/linux/sunxi/patches-3.12/106-dt-sun7i-add-mod0-clk.patch')
| -rw-r--r-- | target/linux/sunxi/patches-3.12/106-dt-sun7i-add-mod0-clk.patch | 136 |
1 files changed, 0 insertions, 136 deletions
diff --git a/target/linux/sunxi/patches-3.12/106-dt-sun7i-add-mod0-clk.patch b/target/linux/sunxi/patches-3.12/106-dt-sun7i-add-mod0-clk.patch deleted file mode 100644 index fbd30c65e7..0000000000 --- a/target/linux/sunxi/patches-3.12/106-dt-sun7i-add-mod0-clk.patch +++ /dev/null @@ -1,136 +0,0 @@ -From 8cf7164b32f2ce228b0c8116fd712484f67c65b5 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar> -Date: Wed, 4 Sep 2013 21:28:49 -0300 -Subject: [PATCH] ARM: sun7i: dt: mod0 clocks -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This commit adds all the mod0 clocks available on A20 to its device -tree. This list was created by looking at AW's code release. - -Signed-off-by: Emilio López <emilio@elopez.com.ar> -Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> ---- - arch/arm/boot/dts/sun7i-a20.dtsi | 105 +++++++++++++++++++++++++++++++++++++++ - 1 file changed, 105 insertions(+) - -diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi -index 0af287e..0596e82 100644 ---- a/arch/arm/boot/dts/sun7i-a20.dtsi -+++ b/arch/arm/boot/dts/sun7i-a20.dtsi -@@ -174,6 +174,111 @@ - "apb1_uart2", "apb1_uart3", "apb1_uart4", - "apb1_uart5", "apb1_uart6", "apb1_uart7"; - }; -+ -+ nand: nand@01c20080 { -+ #clock-cells = <0>; -+ compatible = "allwinner,sun4i-mod0-clk"; -+ reg = <0x01c20080 0x4>; -+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; -+ }; -+ -+ ms: ms@01c20084 { -+ #clock-cells = <0>; -+ compatible = "allwinner,sun4i-mod0-clk"; -+ reg = <0x01c20084 0x4>; -+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; -+ }; -+ -+ mmc0: mmc0@01c20088 { -+ #clock-cells = <0>; -+ compatible = "allwinner,sun4i-mod0-clk"; -+ reg = <0x01c20088 0x4>; -+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; -+ }; -+ -+ mmc1: mmc1@01c2008c { -+ #clock-cells = <0>; -+ compatible = "allwinner,sun4i-mod0-clk"; -+ reg = <0x01c2008c 0x4>; -+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; -+ }; -+ -+ mmc2: mmc2@01c20090 { -+ #clock-cells = <0>; -+ compatible = "allwinner,sun4i-mod0-clk"; -+ reg = <0x01c20090 0x4>; -+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; -+ }; -+ -+ mmc3: mmc3@01c20094 { -+ #clock-cells = <0>; -+ compatible = "allwinner,sun4i-mod0-clk"; -+ reg = <0x01c20094 0x4>; -+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; -+ }; -+ -+ ts: ts@01c20098 { -+ #clock-cells = <0>; -+ compatible = "allwinner,sun4i-mod0-clk"; -+ reg = <0x01c20098 0x4>; -+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; -+ }; -+ -+ ss: ss@01c2009c { -+ #clock-cells = <0>; -+ compatible = "allwinner,sun4i-mod0-clk"; -+ reg = <0x01c2009c 0x4>; -+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; -+ }; -+ -+ spi0: spi0@01c200a0 { -+ #clock-cells = <0>; -+ compatible = "allwinner,sun4i-mod0-clk"; -+ reg = <0x01c200a0 0x4>; -+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; -+ }; -+ -+ spi1: spi1@01c200a4 { -+ #clock-cells = <0>; -+ compatible = "allwinner,sun4i-mod0-clk"; -+ reg = <0x01c200a4 0x4>; -+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; -+ }; -+ -+ spi2: spi2@01c200a8 { -+ #clock-cells = <0>; -+ compatible = "allwinner,sun4i-mod0-clk"; -+ reg = <0x01c200a8 0x4>; -+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; -+ }; -+ -+ pata: pata@01c200ac { -+ #clock-cells = <0>; -+ compatible = "allwinner,sun4i-mod0-clk"; -+ reg = <0x01c200ac 0x4>; -+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; -+ }; -+ -+ ir0: ir0@01c200b0 { -+ #clock-cells = <0>; -+ compatible = "allwinner,sun4i-mod0-clk"; -+ reg = <0x01c200b0 0x4>; -+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; -+ }; -+ -+ ir1: ir1@01c200b4 { -+ #clock-cells = <0>; -+ compatible = "allwinner,sun4i-mod0-clk"; -+ reg = <0x01c200b4 0x4>; -+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; -+ }; -+ -+ spi3: spi3@01c200d4 { -+ #clock-cells = <0>; -+ compatible = "allwinner,sun4i-mod0-clk"; -+ reg = <0x01c200d4 0x4>; -+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; -+ }; - }; - - soc@01c00000 { --- -1.8.5.1 - |