diff options
Diffstat (limited to 'target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl930x.c')
-rw-r--r-- | target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl930x.c | 294 |
1 files changed, 147 insertions, 147 deletions
diff --git a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl930x.c b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl930x.c index 6cd0c6b814..384b33b0ba 100644 --- a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl930x.c +++ b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl930x.c @@ -26,15 +26,15 @@ extern struct rtl83xx_soc_info soc_info; /* Definition of the RTL930X-specific template field IDs as used in the PIE */ enum template_field_id { - TEMPLATE_FIELD_SPM0 = 0, // Source portmask ports 0-15 - TEMPLATE_FIELD_SPM1 = 1, // Source portmask ports 16-31 - TEMPLATE_FIELD_DMAC0 = 2, // Destination MAC [15:0] - TEMPLATE_FIELD_DMAC1 = 3, // Destination MAC [31:16] - TEMPLATE_FIELD_DMAC2 = 4, // Destination MAC [47:32] - TEMPLATE_FIELD_SMAC0 = 5, // Source MAC [15:0] - TEMPLATE_FIELD_SMAC1 = 6, // Source MAC [31:16] - TEMPLATE_FIELD_SMAC2 = 7, // Source MAC [47:32] - TEMPLATE_FIELD_ETHERTYPE = 8, // Ethernet frame type field + TEMPLATE_FIELD_SPM0 = 0, /* Source portmask ports 0-15 */ + TEMPLATE_FIELD_SPM1 = 1, /* Source portmask ports 16-31 */ + TEMPLATE_FIELD_DMAC0 = 2, /* Destination MAC [15:0] */ + TEMPLATE_FIELD_DMAC1 = 3, /* Destination MAC [31:16] */ + TEMPLATE_FIELD_DMAC2 = 4, /* Destination MAC [47:32] */ + TEMPLATE_FIELD_SMAC0 = 5, /* Source MAC [15:0] */ + TEMPLATE_FIELD_SMAC1 = 6, /* Source MAC [31:16] */ + TEMPLATE_FIELD_SMAC2 = 7, /* Source MAC [47:32] */ + TEMPLATE_FIELD_ETHERTYPE = 8, /* Ethernet frame type field */ TEMPLATE_FIELD_OTAG = 9, TEMPLATE_FIELD_ITAG = 10, TEMPLATE_FIELD_SIP0 = 11, @@ -71,7 +71,7 @@ enum template_field_id { TEMPLATE_FIELD_SNAP_OUI = 42, TEMPLATE_FIELD_FWD_VID = 43, TEMPLATE_FIELD_RANGE_CHK = 44, - TEMPLATE_FIELD_VLAN_GMSK = 45, // VLAN Group Mask/IP range check + TEMPLATE_FIELD_VLAN_GMSK = 45, /* VLAN Group Mask/IP range check */ TEMPLATE_FIELD_DLP = 46, TEMPLATE_FIELD_META_DATA = 47, TEMPLATE_FIELD_SRC_FWD_VID = 48, @@ -83,9 +83,9 @@ enum template_field_id { */ #define TEMPLATE_FIELD_VLAN TEMPLATE_FIELD_ITAG -// Number of fixed templates predefined in the RTL9300 SoC +/* Number of fixed templates predefined in the RTL9300 SoC */ #define N_FIXED_TEMPLATES 5 -// RTL9300 specific predefined templates +/* RTL9300 specific predefined templates */ static enum template_field_id fixed_templates[N_FIXED_TEMPLATES][N_FIXED_FIELDS] = { { @@ -152,7 +152,7 @@ static inline int rtl930x_l2_port_new_salrn(int p) static inline int rtl930x_l2_port_new_sa_fwd(int p) { - // TODO: The definition of the fields changed, because of the master-cpu in a stack + /* TODO: The definition of the fields changed, because of the master-cpu in a stack */ return RTL930X_L2_PORT_NEW_SA_FWD(p); } @@ -164,7 +164,7 @@ inline static int rtl930x_trk_mbr_ctr(int group) static void rtl930x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info) { u32 v, w; - // Read VLAN table (1) via register 0 + /* Read VLAN table (1) via register 0 */ struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 1); rtl_table_read(r, vlan); @@ -179,7 +179,7 @@ static void rtl930x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info) info->hash_uc_fid = !!(w & BIT(28)); info->fid = ((v & 0x7) << 3) | ((w >> 29) & 0x7); - // Read UNTAG table via table register 2 + /* Read UNTAG table via table register 2 */ r = rtl_table_get(RTL9300_TBL_2, 0); rtl_table_read(r, vlan); v = sw_r32(rtl_table_data(r, 0)); @@ -191,7 +191,7 @@ static void rtl930x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info) static void rtl930x_vlan_set_tagged(u32 vlan, struct rtl838x_vlan_info *info) { u32 v, w; - // Access VLAN table (1) via register 0 + /* Access VLAN table (1) via register 0 */ struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 1); v = info->tagged_ports << 3; @@ -245,7 +245,7 @@ static void rtl930x_vlan_set_untagged(u32 vlan, u64 portmask) /* Sets the L2 forwarding to be based on either the inner VLAN tag or the outer */ static void rtl930x_vlan_fwd_on_inner(int port, bool is_set) { - // Always set all tag modes to fwd based on either inner or outer tag + /* Always set all tag modes to fwd based on either inner or outer tag */ if (is_set) sw_w32_mask(0, 0xf, RTL930X_VLAN_PORT_FWD + (port << 2)); else @@ -260,11 +260,11 @@ static void rtl930x_vlan_profile_setup(int profile) p[0] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile)); p[1] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile) + 4); - // Enable routing of Ipv4/6 Unicast and IPv4/6 Multicast traffic + /* Enable routing of Ipv4/6 Unicast and IPv4/6 Multicast traffic */ p[0] |= BIT(17) | BIT(16) | BIT(13) | BIT(12); - p[2] = 0x1fffffff; // L2 unknown MC flooding portmask all ports, including the CPU-port - p[3] = 0x1fffffff; // IPv4 unknown MC flooding portmask - p[4] = 0x1fffffff; // IPv6 unknown MC flooding portmask + p[2] = 0x1fffffff; /* L2 unknown MC flooding portmask all ports, including the CPU-port */ + p[3] = 0x1fffffff; /* IPv4 unknown MC flooding portmask */ + p[4] = 0x1fffffff; /* IPv6 unknown MC flooding portmask */ sw_w32(p[0], RTL930X_VLAN_PROFILE_SET(profile)); sw_w32(p[1], RTL930X_VLAN_PROFILE_SET(profile) + 4); @@ -275,13 +275,13 @@ static void rtl930x_vlan_profile_setup(int profile) static void rtl930x_l2_learning_setup(void) { - // Portmask for flooding broadcast traffic + /* Portmask for flooding broadcast traffic */ sw_w32(0x1fffffff, RTL930X_L2_BC_FLD_PMSK); - // Portmask for flooding unicast traffic with unknown destination + /* Portmask for flooding unicast traffic with unknown destination */ sw_w32(0x1fffffff, RTL930X_L2_UNKN_UC_FLD_PMSK); - // Limit learning to maximum: 32k entries, after that just flood (bits 0-1) + /* Limit learning to maximum: 32k entries, after that just flood (bits 0-1) */ sw_w32((0x7fff << 2) | 0, RTL930X_L2_LRN_CONSTRT_CTRL); } @@ -366,7 +366,7 @@ static u32 rtl930x_l2_hash_key(struct rtl838x_switch_priv *priv, u64 seed) h1 ^ (seed & 0x7ff)); - // Algorithm choice for block 0 + /* Algorithm choice for block 0 */ if (sw_r32(RTL930X_L2_CTRL) & BIT(0)) h = k1; else @@ -398,7 +398,7 @@ static void rtl930x_fill_l2_entry(u32 r[], struct rtl838x_l2_entry *e) e->is_ip_mc = false; e->is_ipv6_mc = false; - // TODO: Is there not a function to copy directly MAC memory? + /* TODO: Is there not a function to copy directly MAC memory? */ e->mac[0] = (r[0] >> 24); e->mac[1] = (r[0] >> 16); e->mac[2] = (r[0] >> 8); @@ -414,7 +414,7 @@ static void rtl930x_fill_l2_entry(u32 r[], struct rtl838x_l2_entry *e) e->type = L2_UNICAST; e->is_static = !!(r[2] & BIT(14)); e->port = (r[2] >> 20) & 0x3ff; - // Check for trunk port + /* Check for trunk port */ if (r[2] & BIT(30)) { e->is_trunk = true; e->stack_dev = (e->port >> 9) & 1; @@ -430,7 +430,7 @@ static void rtl930x_fill_l2_entry(u32 r[], struct rtl838x_l2_entry *e) e->suspended = !!(r[2] & BIT(13)); e->age = (r[2] >> 17) & 3; e->valid = true; - // the UC_VID field in hardware is used for the VID or for the route id + /* the UC_VID field in hardware is used for the VID or for the route id */ if (e->next_hop) { e->nh_route_id = r[2] & 0x7ff; e->vid = 0; @@ -455,7 +455,7 @@ static void rtl930x_fill_l2_row(u32 r[], struct rtl838x_l2_entry *e) return; } - r[2] = BIT(31); // Set valid bit + r[2] = BIT(31); /* Set valid bit */ r[0] = ((u32)e->mac[0]) << 24 | ((u32)e->mac[1]) << 16 | @@ -482,12 +482,12 @@ static void rtl930x_fill_l2_row(u32 r[], struct rtl838x_l2_entry *e) r[2] |= e->block_sa ? BIT(17) : 0; r[2] |= e->suspended ? BIT(13) : 0; r[2] |= (e->age & 0x3) << 17; - // the UC_VID field in hardware is used for the VID or for the route id + /* the UC_VID field in hardware is used for the VID or for the route id */ if (e->next_hop) r[2] |= e->nh_route_id & 0x7ff; else r[2] |= e->vid & 0xfff; - } else { // L2_MULTICAST + } else { /* L2_MULTICAST */ r[2] |= (e->mc_portmask_index & 0x3ff) << 16; r[2] |= e->mc_mac_index & 0x7ff; } @@ -519,7 +519,7 @@ static u64 rtl930x_read_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2 hash &= 0xffff; } - idx = (0 << 14) | (hash << 2) | pos; // Search SRAM, with hash and at pos in bucket + idx = (0 << 14) | (hash << 2) | pos; /* Search SRAM, with hash and at pos in bucket */ pr_debug("%s: NOW hash %08x, pos: %d\n", __func__, hash, pos); rtl_table_read(q, idx); @@ -544,7 +544,7 @@ static u64 rtl930x_read_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2 seed = rtl930x_l2_hash_seed(mac, e->rvid); pr_debug("%s: mac %016llx, seed %016llx\n", __func__, mac, seed); - // return vid with concatenated mac as unique id + /* return vid with concatenated mac as unique id */ return seed; } @@ -552,7 +552,7 @@ static void rtl930x_write_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_ { u32 r[3]; struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 0); - u32 idx = (0 << 14) | (hash << 2) | pos; // Access SRAM, with hash and at pos in bucket + u32 idx = (0 << 14) | (hash << 2) | pos; /* Access SRAM, with hash and at pos in bucket */ int i; pr_debug("%s: hash %d, pos %d\n", __func__, hash, pos); @@ -584,14 +584,14 @@ static u64 rtl930x_read_cam(int idx, struct rtl838x_l2_entry *e) if (!e->valid) return 0; - // return mac with concatenated vid as unique id + /* return mac with concatenated vid as unique id */ return ((u64)r[0] << 28) | ((r[1] & 0xffff0000) >> 4) | e->vid; } static void rtl930x_write_cam(int idx, struct rtl838x_l2_entry *e) { u32 r[3]; - struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 1); // Access L2 Table 1 + struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 1); /* Access L2 Table 1 */ int i; rtl930x_fill_l2_row(r, e); @@ -606,7 +606,7 @@ static void rtl930x_write_cam(int idx, struct rtl838x_l2_entry *e) static u64 rtl930x_read_mcast_pmask(int idx) { u32 portmask; - // Read MC_PORTMASK (2) via register RTL9300_TBL_L2 + /* Read MC_PORTMASK (2) via register RTL9300_TBL_L2 */ struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 2); rtl_table_read(q, idx); @@ -623,7 +623,7 @@ static void rtl930x_write_mcast_pmask(int idx, u64 portmask) { u32 pm = portmask; - // Access MC_PORTMASK (2) via register RTL9300_TBL_L2 + /* Access MC_PORTMASK (2) via register RTL9300_TBL_L2 */ struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 2); pr_debug("%s: Index idx %d has portmask %08x\n", __func__, idx, pm); @@ -790,16 +790,16 @@ int rtl930x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val) mutex_lock(&smi_lock); - // Set PHY to access + /* Set PHY to access */ sw_w32(BIT(port), RTL930X_SMI_ACCESS_PHY_CTRL_0); - // Set data to write + /* Set data to write */ sw_w32_mask(0xffff << 16, val << 16, RTL930X_SMI_ACCESS_PHY_CTRL_2); - // Set MMD device number and register to write to + /* Set MMD device number and register to write to */ sw_w32(devnum << 16 | (regnum & 0xffff), RTL930X_SMI_ACCESS_PHY_CTRL_3); - v = BIT(2) | BIT(1) | BIT(0); // WRITE | MMD-access | EXEC + v = BIT(2) | BIT(1) | BIT(0); /* WRITE | MMD-access | EXEC */ sw_w32(v, RTL930X_SMI_ACCESS_PHY_CTRL_1); do { @@ -819,19 +819,19 @@ int rtl930x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val) mutex_lock(&smi_lock); - // Set PHY to access + /* Set PHY to access */ sw_w32_mask(0xffff << 16, port << 16, RTL930X_SMI_ACCESS_PHY_CTRL_2); - // Set MMD device number and register to write to + /* Set MMD device number and register to write to */ sw_w32(devnum << 16 | (regnum & 0xffff), RTL930X_SMI_ACCESS_PHY_CTRL_3); - v = BIT(1) | BIT(0); // MMD-access | EXEC + v = BIT(1) | BIT(0); /* MMD-access | EXEC */ sw_w32(v, RTL930X_SMI_ACCESS_PHY_CTRL_1); do { v = sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_1); } while (v & BIT(0)); - // There is no error-checking via BIT 25 of v, as it does not seem to be set correctly + /* There is no error-checking via BIT 25 of v, as it does not seem to be set correctly */ *val = (sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_2) & 0xffff); pr_debug("%s: port %d, regnum: %x, val: %x (err %d)\n", __func__, port, regnum, *val, err); @@ -868,7 +868,7 @@ u32 rtl930x_hash(struct rtl838x_switch_priv *priv, u64 seed) h1 ^ (seed & 0x7ff)); - // Algorithm choice for block 0 + /* Algorithm choice for block 0 */ if (sw_r32(RTL930X_L2_CTRL) & BIT(0)) h = k1; else @@ -893,17 +893,17 @@ void rtl930x_port_eee_set(struct rtl838x_switch_priv *priv, int port, bool enabl { u32 v; - // This works only for Ethernet ports, and on the RTL930X, ports from 26 are SFP + /* This works only for Ethernet ports, and on the RTL930X, ports from 26 are SFP */ if (port >= 26) return; pr_debug("In %s: setting port %d to %d\n", __func__, port, enable); v = enable ? 0x3f : 0x0; - // Set EEE/EEEP state for 100, 500, 1000MBit and 2.5, 5 and 10GBit + /* Set EEE/EEEP state for 100, 500, 1000MBit and 2.5, 5 and 10GBit */ sw_w32_mask(0, v << 10, rtl930x_mac_force_mode_ctrl(port)); - // Set TX/RX EEE state + /* Set TX/RX EEE state */ v = enable ? 0x3 : 0x0; sw_w32(v, RTL930X_EEE_CTRL(port)); @@ -951,7 +951,7 @@ int rtl930x_eee_port_ability(struct rtl838x_switch_priv *priv, struct ethtool_ee e->lp_advertised |= ADVERTISED_10000baseT_Full; } - // Read 2x to clear latched state + /* Read 2x to clear latched state */ a = sw_r32(RTL930X_EEEP_PORT_CTRL(port)); a = sw_r32(RTL930X_EEEP_PORT_CTRL(port)); pr_info("%s RTL930X_EEEP_PORT_CTRL: %08x\n", __func__, a); @@ -965,7 +965,7 @@ static void rtl930x_init_eee(struct rtl838x_switch_priv *priv, bool enable) pr_info("Setting up EEE, state: %d\n", enable); - // Setup EEE on all ports + /* Setup EEE on all ports */ for (i = 0; i < priv->cpu_port; i++) { if (priv->ports[i].phy) rtl930x_port_eee_set(priv, i, enable); @@ -1062,11 +1062,11 @@ static void rtl930x_route_read(int idx, struct rtl83xx_route *rt) bool host_route, default_route; struct in6_addr ip6_m; - // Read L3_PREFIX_ROUTE_IPUC table (2) via register RTL9300_TBL_1 + /* Read L3_PREFIX_ROUTE_IPUC table (2) via register RTL9300_TBL_1 */ struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 2); rtl_table_read(r, idx); - // The table has a size of 11 registers + /* The table has a size of 11 registers */ rt->attr.valid = !!(sw_r32(rtl_table_data(r, 0)) & BIT(31)); if (!rt->attr.valid) goto out; @@ -1080,7 +1080,7 @@ static void rtl930x_route_read(int idx, struct rtl83xx_route *rt) pr_info("%s: host route %d, default_route %d\n", __func__, host_route, default_route); switch (rt->attr.type) { - case 0: // IPv4 Unicast route + case 0: /* IPv4 Unicast route */ rt->dst_ip = sw_r32(rtl_table_data(r, 4)); ip4_m = sw_r32(rtl_table_data(r, 9)); pr_info("%s: Read ip4 mask: %08x\n", __func__, ip4_m); @@ -1089,7 +1089,7 @@ static void rtl930x_route_read(int idx, struct rtl83xx_route *rt) if (rt->prefix_len < 0) rt->prefix_len = inet_mask_len(ip4_m); break; - case 2: // IPv6 Unicast route + case 2: /* IPv6 Unicast route */ ipv6_addr_set(&rt->dst_ip6, sw_r32(rtl_table_data(r, 1)), sw_r32(rtl_table_data(r, 2)), sw_r32(rtl_table_data(r, 3)), sw_r32(rtl_table_data(r, 4))); @@ -1102,8 +1102,8 @@ static void rtl930x_route_read(int idx, struct rtl83xx_route *rt) rt->prefix_len = find_last_bit((unsigned long int *)&ip6_m.s6_addr32, 128); break; - case 1: // IPv4 Multicast route - case 3: // IPv6 Multicast route + case 1: /* IPv4 Multicast route */ + case 3: /* IPv6 Multicast route */ pr_warn("%s: route type not supported\n", __func__); goto out; } @@ -1128,7 +1128,7 @@ out: static void rtl930x_net6_mask(int prefix_len, struct in6_addr *ip6_m) { int o, b; - // Define network mask + /* Define network mask */ o = prefix_len >> 3; b = prefix_len & 0x7; memset(ip6_m->s6_addr, 0xff, o); @@ -1141,30 +1141,30 @@ static void rtl930x_net6_mask(int prefix_len, struct in6_addr *ip6_m) static void rtl930x_host_route_read(int idx, struct rtl83xx_route *rt) { u32 v; - // Read L3_HOST_ROUTE_IPUC table (1) via register RTL9300_TBL_1 + /* Read L3_HOST_ROUTE_IPUC table (1) via register RTL9300_TBL_1 */ struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 1); idx = ((idx / 6) * 8) + (idx % 6); pr_debug("In %s, physical index %d\n", __func__, idx); rtl_table_read(r, idx); - // The table has a size of 5 (for UC, 11 for MC) registers + /* The table has a size of 5 (for UC, 11 for MC) registers */ v = sw_r32(rtl_table_data(r, 0)); rt->attr.valid = !!(v & BIT(31)); if (!rt->attr.valid) goto out; rt->attr.type = (v >> 29) & 0x3; switch (rt->attr.type) { - case 0: // IPv4 Unicast route + case 0: /* IPv4 Unicast route */ rt->dst_ip = sw_r32(rtl_table_data(r, 4)); break; - case 2: // IPv6 Unicast route + case 2: /* IPv6 Unicast route */ ipv6_addr_set(&rt->dst_ip6, sw_r32(rtl_table_data(r, 3)), sw_r32(rtl_table_data(r, 2)), sw_r32(rtl_table_data(r, 1)), sw_r32(rtl_table_data(r, 0))); break; - case 1: // IPv4 Multicast route - case 3: // IPv6 Multicast route + case 1: /* IPv4 Multicast route */ + case 3: /* IPv6 Multicast route */ pr_warn("%s: route type not supported\n", __func__); goto out; } @@ -1193,9 +1193,9 @@ out: static void rtl930x_host_route_write(int idx, struct rtl83xx_route *rt) { u32 v; - // Access L3_HOST_ROUTE_IPUC table (1) via register RTL9300_TBL_1 + /* Access L3_HOST_ROUTE_IPUC table (1) via register RTL9300_TBL_1 */ struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 1); - // The table has a size of 5 (for UC, 11 for MC) registers + /* The table has a size of 5 (for UC, 11 for MC) registers */ idx = ((idx / 6) * 8) + (idx % 6); @@ -1205,7 +1205,7 @@ static void rtl930x_host_route_write(int idx, struct rtl83xx_route *rt) rt->attr.dst_null); pr_debug("%s: GW: %pI4, prefix_len: %d\n", __func__, &rt->dst_ip, rt->prefix_len); - v = BIT(31); // Entry is valid + v = BIT(31); /* Entry is valid */ v |= (rt->attr.type & 0x3) << 29; v |= rt->attr.hit ? BIT(20) : 0; v |= rt->attr.dst_null ? BIT(19) : 0; @@ -1218,20 +1218,20 @@ static void rtl930x_host_route_write(int idx, struct rtl83xx_route *rt) sw_w32(v, rtl_table_data(r, 0)); switch (rt->attr.type) { - case 0: // IPv4 Unicast route + case 0: /* IPv4 Unicast route */ sw_w32(0, rtl_table_data(r, 1)); sw_w32(0, rtl_table_data(r, 2)); sw_w32(0, rtl_table_data(r, 3)); sw_w32(rt->dst_ip, rtl_table_data(r, 4)); break; - case 2: // IPv6 Unicast route + case 2: /* IPv6 Unicast route */ sw_w32(rt->dst_ip6.s6_addr32[0], rtl_table_data(r, 1)); sw_w32(rt->dst_ip6.s6_addr32[1], rtl_table_data(r, 2)); sw_w32(rt->dst_ip6.s6_addr32[2], rtl_table_data(r, 3)); sw_w32(rt->dst_ip6.s6_addr32[3], rtl_table_data(r, 4)); break; - case 1: // IPv4 Multicast route - case 3: // IPv6 Multicast route + case 1: /* IPv4 Multicast route */ + case 3: /* IPv6 Multicast route */ pr_warn("%s: route type not supported\n", __func__); goto out; } @@ -1251,16 +1251,16 @@ static int rtl930x_route_lookup_hw(struct rtl83xx_route *rt) struct in6_addr ip6_m; int i; - if (rt->attr.type == 1 || rt->attr.type == 3) // Hardware only supports UC routes + if (rt->attr.type == 1 || rt->attr.type == 3) /* Hardware only supports UC routes */ return -1; sw_w32_mask(0x3 << 19, rt->attr.type, RTL930X_L3_HW_LU_KEY_CTRL); - if (rt->attr.type) { // IPv6 + if (rt->attr.type) { /* IPv6 */ rtl930x_net6_mask(rt->prefix_len, &ip6_m); for (i = 0; i < 4; i++) sw_w32(rt->dst_ip6.s6_addr32[0] & ip6_m.s6_addr32[0], RTL930X_L3_HW_LU_KEY_IP_CTRL + (i << 2)); - } else { // IPv4 + } else { /* IPv4 */ ip4_m = inet_make_mask(rt->prefix_len); sw_w32(0, RTL930X_L3_HW_LU_KEY_IP_CTRL); sw_w32(0, RTL930X_L3_HW_LU_KEY_IP_CTRL + 4); @@ -1270,17 +1270,17 @@ static int rtl930x_route_lookup_hw(struct rtl83xx_route *rt) sw_w32(v, RTL930X_L3_HW_LU_KEY_IP_CTRL + 12); } - // Execute CAM lookup in SoC + /* Execute CAM lookup in SoC */ sw_w32(BIT(15), RTL930X_L3_HW_LU_CTRL); - // Wait until execute bit clears and result is ready + /* Wait until execute bit clears and result is ready */ do { v = sw_r32(RTL930X_L3_HW_LU_CTRL); } while (v & BIT(15)); pr_info("%s: found: %d, index: %d\n", __func__, !!(v & BIT(14)), v & 0x1ff); - // Test if search successful (BIT 14 set) + /* Test if search successful (BIT 14 set) */ if (v & BIT(14)) return v & 0x1ff; @@ -1293,7 +1293,7 @@ static int rtl930x_find_l3_slot(struct rtl83xx_route *rt, bool must_exist) u32 hash; struct rtl83xx_route route_entry; - // IPv6 entries take up 3 slots + /* IPv6 entries take up 3 slots */ slot_width = (rt->attr.type == 0) || (rt->attr.type == 2) ? 1 : 3; for (t = 0; t < 2; t++) { @@ -1328,8 +1328,8 @@ static void rtl930x_route_write(int idx, struct rtl83xx_route *rt) { u32 v, ip4_m; struct in6_addr ip6_m; - // Access L3_PREFIX_ROUTE_IPUC table (2) via register RTL9300_TBL_1 - // The table has a size of 11 registers (20 for MC) + /* Access L3_PREFIX_ROUTE_IPUC table (2) via register RTL9300_TBL_1 */ + /* The table has a size of 11 registers (20 for MC) */ struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 2); pr_debug("%s: index %d is valid: %d\n", __func__, idx, rt->attr.valid); @@ -1350,32 +1350,32 @@ static void rtl930x_route_write(int idx, struct rtl83xx_route *rt) v |= rt->attr.dst_null ? BIT(6) : 0; v |= rt->attr.qos_as ? BIT(6) : 0; v |= rt->attr.qos_prio & 0x7; - v |= rt->prefix_len == 0 ? BIT(20) : 0; // set default route bit + v |= rt->prefix_len == 0 ? BIT(20) : 0; /* set default route bit */ - // set bit mask for entry type always to 0x3 + /* set bit mask for entry type always to 0x3 */ sw_w32(0x3 << 29, rtl_table_data(r, 5)); switch (rt->attr.type) { - case 0: // IPv4 Unicast route + case 0: /* IPv4 Unicast route */ sw_w32(0, rtl_table_data(r, 1)); sw_w32(0, rtl_table_data(r, 2)); sw_w32(0, rtl_table_data(r, 3)); sw_w32(rt->dst_ip, rtl_table_data(r, 4)); - v |= rt->prefix_len == 32 ? BIT(21) : 0; // set host-route bit + v |= rt->prefix_len == 32 ? BIT(21) : 0; /* set host-route bit */ ip4_m = inet_make_mask(rt->prefix_len); sw_w32(0, rtl_table_data(r, 6)); sw_w32(0, rtl_table_data(r, 7)); sw_w32(0, rtl_table_data(r, 8)); sw_w32(ip4_m, rtl_table_data(r, 9)); break; - case 2: // IPv6 Unicast route + case 2: /* IPv6 Unicast route */ sw_w32(rt->dst_ip6.s6_addr32[0], rtl_table_data(r, 1)); sw_w32(rt->dst_ip6.s6_addr32[1], rtl_table_data(r, 2)); sw_w32(rt->dst_ip6.s6_addr32[2], rtl_table_data(r, 3)); sw_w32(rt->dst_ip6.s6_addr32[3], rtl_table_data(r, 4)); - v |= rt->prefix_len == 128 ? BIT(21) : 0; // set host-route bit + v |= rt->prefix_len == 128 ? BIT(21) : 0; /* set host-route bit */ rtl930x_net6_mask(rt->prefix_len, &ip6_m); @@ -1384,8 +1384,8 @@ static void rtl930x_route_write(int idx, struct rtl83xx_route *rt) sw_w32(ip6_m.s6_addr32[2], rtl_table_data(r, 8)); sw_w32(ip6_m.s6_addr32[3], rtl_table_data(r, 9)); break; - case 1: // IPv4 Multicast route - case 3: // IPv6 Multicast route + case 1: /* IPv4 Multicast route */ + case 3: /* IPv6 Multicast route */ pr_warn("%s: route type not supported\n", __func__); rtl_table_release(r); return; @@ -1409,11 +1409,11 @@ static void rtl930x_route_write(int idx, struct rtl83xx_route *rt) static void rtl930x_get_l3_nexthop(int idx, u16 *dmac_id, u16 *interface) { u32 v; - // Read L3_NEXTHOP table (3) via register RTL9300_TBL_1 + /* Read L3_NEXTHOP table (3) via register RTL9300_TBL_1 */ struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 3); rtl_table_read(r, idx); - // The table has a size of 1 register + /* The table has a size of 1 register */ v = sw_r32(rtl_table_data(r, 0)); rtl_table_release(r); @@ -1442,7 +1442,7 @@ static int rtl930x_l3_mtu_add(struct rtl838x_switch_priv *priv, int mtu) int i, free_mtu; int mtu_id; - // Try to find an existing mtu-value or a free slot + /* Try to find an existing mtu-value or a free slot */ free_mtu = MAX_INTF_MTUS; for (i = 0; i < MAX_INTF_MTUS && priv->intf_mtus[i] != mtu; i++) { if ((!priv->intf_mtu_count[i]) && (free_mtu == MAX_INTF_MTUS)) @@ -1458,7 +1458,7 @@ static int rtl930x_l3_mtu_add(struct rtl838x_switch_priv *priv, int mtu) priv->intf_mtus[i] = mtu; pr_info("Writing MTU %d to slot %d\n", priv->intf_mtus[i], i); - // Set MTU-value of the slot TODO: distinguish between IPv4/IPv6 routes / slots + /* Set MTU-value of the slot TODO: distinguish between IPv4/IPv6 routes / slots */ sw_w32_mask(0xffff << ((i % 2) * 16), priv->intf_mtus[i] << ((i % 2) * 16), RTL930X_L3_IP_MTU_CTRL(i)); sw_w32_mask(0xffff << ((i % 2) * 16), priv->intf_mtus[i] << ((i % 2) * 16), @@ -1473,9 +1473,9 @@ static int rtl930x_l3_mtu_add(struct rtl838x_switch_priv *priv, int mtu) static int rtl930x_l3_intf_add(struct rtl838x_switch_priv *priv, struct rtl838x_l3_intf *intf) { int i, intf_id, mtu_id; - // number of MTU-values < 16384 + /* number of MTU-values < 16384 */ - // Use the same IPv6 mtu as the ip4 mtu for this route if unset + /* Use the same IPv6 mtu as the ip4 mtu for this route if unset */ intf->ip6_mtu = intf->ip6_mtu ? intf->ip6_mtu : intf->ip4_mtu; mtu_id = rtl930x_l3_mtu_add(priv, intf->ip4_mtu); @@ -1510,7 +1510,7 @@ static int rtl930x_l3_intf_add(struct rtl838x_switch_priv *priv, struct rtl838x_ */ static void rtl930x_set_l3_nexthop(int idx, u16 dmac_id, u16 interface) { - // Access L3_NEXTHOP table (3) via register RTL9300_TBL_1 + /* Access L3_NEXTHOP table (3) via register RTL9300_TBL_1 */ struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 3); pr_info("%s: Writing to L3_NEXTHOP table, index %d, dmac_id %d, interface %d\n", @@ -1685,7 +1685,7 @@ static void rtl930x_write_pie_templated(u32 r[], struct pie_rule *pr, enum templ pr_info("%s: unknown field %d\n", __func__, field_type); } - // On the RTL9300, the mask fields are not word aligned! + /* On the RTL9300, the mask fields are not word aligned! */ if (!(i % 2)) { r[5 - i / 2] = data; r[12 - i / 2] |= ((u32)data_m << 8); @@ -1787,15 +1787,15 @@ static void rtl930x_write_pie_fixed_fields(u32 r[], struct pie_rule *pr) static void rtl930x_write_pie_action(u32 r[], struct pie_rule *pr) { - // Either drop or forward + /* Either drop or forward */ if (pr->drop) { - r[14] |= BIT(24) | BIT(25) | BIT(26); // Do Green, Yellow and Red drops - // Actually DROP, not PERMIT in Green / Yellow / Red + r[14] |= BIT(24) | BIT(25) | BIT(26); /* Do Green, Yellow and Red drops */ + /* Actually DROP, not PERMIT in Green / Yellow / Red */ r[14] |= BIT(23) | BIT(22) | BIT(20); } else { r[14] |= pr->fwd_sel ? BIT(27) : 0; r[14] |= pr->fwd_act << 18; - r[14] |= BIT(14); // We overwrite any drop + r[14] |= BIT(14); /* We overwrite any drop */ } if (pr->phase == PHASE_VACL) r[14] |= pr->fwd_sa_lrn ? BIT(15) : 0; @@ -1844,7 +1844,7 @@ void rtl930x_pie_rule_dump_raw(u32 r[]) static int rtl930x_pie_rule_write(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr) { - // Access IACL table (2) via register 0 + /* Access IACL table (2) via register 0 */ struct table_reg *q = rtl_table_get(RTL9300_TBL_0, 2); u32 r[19]; int i; @@ -1868,7 +1868,7 @@ static int rtl930x_pie_rule_write(struct rtl838x_switch_priv *priv, int idx, str rtl930x_write_pie_action(r, pr); -// rtl930x_pie_rule_dump_raw(r); +/* rtl930x_pie_rule_dump_raw(r); */ for (i = 0; i < 19; i++) sw_w32(r[i], rtl_table_data(q, i)); @@ -1929,7 +1929,7 @@ static int rtl930x_pie_verify_template(struct rtl838x_switch_priv *priv, if (ether_addr_to_u64(pr->dmac) && !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_DMAC0)) return -1; - // TODO: Check more + /* TODO: Check more */ i = find_first_zero_bit(&priv->pie_use_bm[block * 4], PIE_BLOCK_SIZE); @@ -1976,7 +1976,7 @@ static int rtl930x_pie_rule_add(struct rtl838x_switch_priv *priv, struct pie_rul set_bit(idx, priv->pie_use_bm); pr->valid = true; - pr->tid = j; // Mapped to template number + pr->tid = j; /* Mapped to template number */ pr->tid_m = 0x1; pr->id = idx; @@ -1995,10 +1995,10 @@ static int rtl930x_pie_rule_del(struct rtl838x_switch_priv *priv, int index_from pr_debug("%s: from %d to %d\n", __func__, index_from, index_to); mutex_lock(&priv->reg_mutex); - // Write from-to and execute bit into control register + /* Write from-to and execute bit into control register */ sw_w32(v, RTL930X_PIE_CLR_CTRL); - // Wait until command has completed + /* Wait until command has completed */ do { } while (sw_r32(RTL930X_PIE_CLR_CTRL) & BIT(0)); @@ -2022,35 +2022,35 @@ static void rtl930x_pie_init(struct rtl838x_switch_priv *priv) mutex_init(&priv->pie_mutex); pr_info("%s\n", __func__); - // Enable ACL lookup on all ports, including CPU_PORT + /* Enable ACL lookup on all ports, including CPU_PORT */ for (i = 0; i <= priv->cpu_port; i++) sw_w32(1, RTL930X_ACL_PORT_LOOKUP_CTRL(i)); - // Include IPG in metering + /* Include IPG in metering */ sw_w32_mask(0, 1, RTL930X_METER_GLB_CTRL); - // Delete all present rules, block size is 128 on all SoC families + /* Delete all present rules, block size is 128 on all SoC families */ rtl930x_pie_rule_del(priv, 0, priv->n_pie_blocks * 128 - 1); - // Assign blocks 0-7 to VACL phase (bit = 0), blocks 8-15 to IACL (bit = 1) + /* Assign blocks 0-7 to VACL phase (bit = 0), blocks 8-15 to IACL (bit = 1) */ sw_w32(0xff00, RTL930X_PIE_BLK_PHASE_CTRL); - // Enable predefined templates 0, 1 for first quarter of all blocks + /* Enable predefined templates 0, 1 for first quarter of all blocks */ template_selectors = 0 | (1 << 4); for (i = 0; i < priv->n_pie_blocks / 4; i++) sw_w32(template_selectors, RTL930X_PIE_BLK_TMPLTE_CTRL(i)); - // Enable predefined templates 2, 3 for second quarter of all blocks + /* Enable predefined templates 2, 3 for second quarter of all blocks */ template_selectors = 2 | (3 << 4); for (i = priv->n_pie_blocks / 4; i < priv->n_pie_blocks / 2; i++) sw_w32(template_selectors, RTL930X_PIE_BLK_TMPLTE_CTRL(i)); - // Enable predefined templates 0, 1 for third half of all blocks + /* Enable predefined templates 0, 1 for third half of all blocks */ template_selectors = 0 | (1 << 4); for (i = priv->n_pie_blocks / 2; i < priv->n_pie_blocks * 3 / 4; i++) sw_w32(template_selectors, RTL930X_PIE_BLK_TMPLTE_CTRL(i)); - // Enable predefined templates 2, 3 for fourth quater of all blocks + /* Enable predefined templates 2, 3 for fourth quater of all blocks */ template_selectors = 2 | (3 << 4); for (i = priv->n_pie_blocks * 3 / 4; i < priv->n_pie_blocks; i++) sw_w32(template_selectors, RTL930X_PIE_BLK_TMPLTE_CTRL(i)); @@ -2066,10 +2066,10 @@ static void rtl930x_pie_init(struct rtl838x_switch_priv *priv) static void rtl930x_set_l3_egress_intf(int idx, struct rtl838x_l3_intf *intf) { u32 u, v; - // Read L3_EGR_INTF table (4) via register RTL9300_TBL_1 + /* Read L3_EGR_INTF table (4) via register RTL9300_TBL_1 */ struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 4); - // The table has 2 registers + /* The table has 2 registers */ u = (intf->vid & 0xfff) << 9; u |= (intf->smac_idx & 0x3f) << 3; u |= (intf->ip4_mtu_id & 0x7); @@ -2097,11 +2097,11 @@ static void rtl930x_set_l3_egress_intf(int idx, struct rtl838x_l3_intf *intf) static void rtl930x_get_l3_router_mac(u32 idx, struct rtl93xx_rt_mac *m) { u32 v, w; - // Read L3_ROUTER_MAC table (0) via register RTL9300_TBL_1 + /* Read L3_ROUTER_MAC table (0) via register RTL9300_TBL_1 */ struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 0); rtl_table_read(r, idx); - // The table has a size of 7 registers, 64 entries + /* The table has a size of 7 registers, 64 entries */ v = sw_r32(rtl_table_data(r, 0)); w = sw_r32(rtl_table_data(r, 3)); m->valid = !!(v & BIT(20)); @@ -2109,7 +2109,7 @@ static void rtl930x_get_l3_router_mac(u32 idx, struct rtl93xx_rt_mac *m) goto out; m->p_type = !!(v & BIT(19)); - m->p_id = (v >> 13) & 0x3f; // trunk id of port + m->p_id = (v >> 13) & 0x3f; /* trunk id of port */ m->vid = v & 0xfff; m->vid_mask = w & 0xfff; m->action = sw_r32(rtl_table_data(r, 6)) & 0x7; @@ -2117,7 +2117,7 @@ static void rtl930x_get_l3_router_mac(u32 idx, struct rtl93xx_rt_mac *m) (sw_r32(rtl_table_data(r, 4))); m->mac = ((((u64)sw_r32(rtl_table_data(r, 1))) << 32) & 0xffffffffffffULL) | (sw_r32(rtl_table_data(r, 2))); - // Bits L3_INTF and BMSK_L3_INTF are 0 + /* Bits L3_INTF and BMSK_L3_INTF are 0 */ out: rtl_table_release(r); @@ -2130,13 +2130,13 @@ out: static void rtl930x_set_l3_router_mac(u32 idx, struct rtl93xx_rt_mac *m) { u32 v, w; - // Read L3_ROUTER_MAC table (0) via register RTL9300_TBL_1 + /* Read L3_ROUTER_MAC table (0) via register RTL9300_TBL_1 */ struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 0); - // The table has a size of 7 registers, 64 entries - v = BIT(20); // mac entry valid, port type is 0: individual + /* The table has a size of 7 registers, 64 entries */ + v = BIT(20); /* mac entry valid, port type is 0: individual */ v |= (m->p_id & 0x3f) << 13; - v |= (m->vid & 0xfff); // Set the interface_id to the vlan id + v |= (m->vid & 0xfff); /* Set the interface_id to the vlan id */ w = m->vid_mask; w |= (m->p_id_mask & 0x3f) << 13; @@ -2144,11 +2144,11 @@ static void rtl930x_set_l3_router_mac(u32 idx, struct rtl93xx_rt_mac *m) sw_w32(v, rtl_table_data(r, 0)); sw_w32(w, rtl_table_data(r, 3)); - // Set MAC address, L3_INTF (bit 12 in register 1) needs to be 0 + /* Set MAC address, L3_INTF (bit 12 in register 1) needs to be 0 */ sw_w32((u32)(m->mac), rtl_table_data(r, 2)); sw_w32(m->mac >> 32, rtl_table_data(r, 1)); - // Set MAC address mask, BMSK_L3_INTF (bit 12 in register 5) needs to be 0 + /* Set MAC address mask, BMSK_L3_INTF (bit 12 in register 5) needs to be 0 */ sw_w32((u32)(m->mac_mask >> 32), rtl_table_data(r, 4)); sw_w32((u32)m->mac_mask, rtl_table_data(r, 5)); @@ -2170,11 +2170,11 @@ static void rtl930x_set_l3_router_mac(u32 idx, struct rtl93xx_rt_mac *m) static u64 rtl930x_get_l3_egress_mac(u32 idx) { u64 mac; - // Read L3_EGR_INTF_MAC table (2) via register RTL9300_TBL_2 + /* Read L3_EGR_INTF_MAC table (2) via register RTL9300_TBL_2 */ struct table_reg *r = rtl_table_get(RTL9300_TBL_2, 2); rtl_table_read(r, idx); - // The table has a size of 2 registers + /* The table has a size of 2 registers */ mac = sw_r32(rtl_table_data(r, 0)); mac <<= 32; mac |= sw_r32(rtl_table_data(r, 1)); @@ -2189,10 +2189,10 @@ static u64 rtl930x_get_l3_egress_mac(u32 idx) */ static void rtl930x_set_l3_egress_mac(u32 idx, u64 mac) { - // Access L3_EGR_INTF_MAC table (2) via register RTL9300_TBL_2 + /* Access L3_EGR_INTF_MAC table (2) via register RTL9300_TBL_2 */ struct table_reg *r = rtl_table_get(RTL9300_TBL_2, 2); - // The table has a size of 2 registers + /* The table has a size of 2 registers */ sw_w32(mac >> 32, rtl_table_data(r, 0)); sw_w32(mac, rtl_table_data(r, 1)); @@ -2211,11 +2211,11 @@ int rtl930x_l3_setup(struct rtl838x_switch_priv *priv) { int i; - // Setup MTU with id 0 for default interface + /* Setup MTU with id 0 for default interface */ for (i = 0; i < MAX_INTF_MTUS; i++) priv->intf_mtu_count[i] = priv->intf_mtus[i] = 0; - priv->intf_mtu_count[0] = 0; // Needs to stay forever + priv->intf_mtu_count[0] = 0; /* Needs to stay forever */ priv->intf_mtus[0] = DEFAULT_MTU; sw_w32_mask(0xffff, DEFAULT_MTU, RTL930X_L3_IP_MTU_CTRL(0)); sw_w32_mask(0xffff, DEFAULT_MTU, RTL930X_L3_IP6_MTU_CTRL(0)); @@ -2228,13 +2228,13 @@ int rtl930x_l3_setup(struct rtl838x_switch_priv *priv) sw_w32_mask(0xffff0000, DEFAULT_MTU << 16, RTL930X_L3_IP_MTU_CTRL(1)); sw_w32_mask(0xffff0000, DEFAULT_MTU << 16, RTL930X_L3_IP6_MTU_CTRL(1)); - // Clear all source port MACs + /* Clear all source port MACs */ for (i = 0; i < MAX_SMACS; i++) rtl930x_set_l3_egress_mac(L3_EGRESS_DMACS + i, 0ULL); - // Configure the default L3 hash algorithm - sw_w32_mask(BIT(2), 0, RTL930X_L3_HOST_TBL_CTRL); // Algorithm selection 0 = 0 - sw_w32_mask(0, BIT(3), RTL930X_L3_HOST_TBL_CTRL); // Algorithm selection 1 = 1 + /* Configure the default L3 hash algorithm */ + sw_w32_mask(BIT(2), 0, RTL930X_L3_HOST_TBL_CTRL); /* Algorithm selection 0 = 0 */ + sw_w32_mask(0, BIT(3), RTL930X_L3_HOST_TBL_CTRL); /* Algorithm selection 1 = 1 */ pr_info("L3_IPUC_ROUTE_CTRL %08x, IPMC_ROUTE %08x, IP6UC_ROUTE %08x, IP6MC_ROUTE %08x\n", sw_r32(RTL930X_L3_IPUC_ROUTE_CTRL), sw_r32(RTL930X_L3_IPMC_ROUTE_CTRL), @@ -2253,13 +2253,13 @@ int rtl930x_l3_setup(struct rtl838x_switch_priv *priv) sw_r32(RTL930X_L3_IPUC_ROUTE_CTRL), sw_r32(RTL930X_L3_IPMC_ROUTE_CTRL), sw_r32(RTL930X_L3_IP6UC_ROUTE_CTRL), sw_r32(RTL930X_L3_IP6MC_ROUTE_CTRL)); - // Trap non-ip traffic to the CPU-port (e.g. ARP so we stay reachable) + /* Trap non-ip traffic to the CPU-port (e.g. ARP so we stay reachable) */ sw_w32_mask(0x3 << 8, 0x1 << 8, RTL930X_L3_IP_ROUTE_CTRL); pr_info("L3_IP_ROUTE_CTRL %08x\n", sw_r32(RTL930X_L3_IP_ROUTE_CTRL)); - // PORT_ISO_RESTRICT_ROUTE_CTRL ? + /* PORT_ISO_RESTRICT_ROUTE_CTRL? */ - // Do not use prefix route 0 because of HW limitations + /* Do not use prefix route 0 because of HW limitations */ set_bit(0, priv->route_use_bm); return 0; @@ -2269,7 +2269,7 @@ static u32 rtl930x_packet_cntr_read(int counter) { u32 v; - // Read LOG table (3) via register RTL9300_TBL_0 + /* Read LOG table (3) via register RTL9300_TBL_0 */ struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 3); pr_debug("In %s, id %d\n", __func__, counter); @@ -2277,7 +2277,7 @@ static u32 rtl930x_packet_cntr_read(int counter) pr_debug("Registers: %08x %08x\n", sw_r32(rtl_table_data(r, 0)), sw_r32(rtl_table_data(r, 1))); - // The table has a size of 2 registers + /* The table has a size of 2 registers */ if (counter % 2) v = sw_r32(rtl_table_data(r, 0)); else @@ -2290,11 +2290,11 @@ static u32 rtl930x_packet_cntr_read(int counter) static void rtl930x_packet_cntr_clear(int counter) { - // Access LOG table (3) via register RTL9300_TBL_0 + /* Access LOG table (3) via register RTL9300_TBL_0 */ struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 3); pr_info("In %s, id %d\n", __func__, counter); - // The table has a size of 2 registers + /* The table has a size of 2 registers */ if (counter % 2) sw_w32(0, rtl_table_data(r, 0)); else @@ -2447,10 +2447,10 @@ static void rtl930x_led_init(struct rtl838x_switch_priv *priv) sw_w32(v, RTL930X_LED_SET0_0_CTRL - i * 8); } - // Set LED mode to serial (0x1) + /* Set LED mode to serial (0x1) */ sw_w32_mask(0x3, 0x1, RTL930X_LED_GLB_CTRL); - // Set port type masks + /* Set port type masks */ sw_w32(pm, RTL930X_LED_PORT_COPR_MASK_CTRL); sw_w32(pm, RTL930X_LED_PORT_FIB_MASK_CTRL); sw_w32(pm, RTL930X_LED_PORT_COMBO_MASK_CTRL); @@ -2477,7 +2477,7 @@ const struct rtl838x_reg rtl930x_reg = { .l2_ctrl_1 = RTL930X_L2_AGE_CTRL, .l2_port_aging_out = RTL930X_L2_PORT_AGE_CTRL, .set_ageing_time = rtl930x_set_ageing_time, - .smi_poll_ctrl = RTL930X_SMI_POLL_CTRL, // TODO: Difference to RTL9300_SMI_PRVTE_POLLING_CTRL + .smi_poll_ctrl = RTL930X_SMI_POLL_CTRL, /* TODO: Difference to RTL9300_SMI_PRVTE_POLLING_CTRL */ .l2_tbl_flush_ctrl = RTL930X_L2_TBL_FLUSH_CTRL, .exec_tbl0_cmd = rtl930x_exec_tbl0_cmd, .exec_tbl1_cmd = rtl930x_exec_tbl1_cmd, |