diff options
Diffstat (limited to 'target/linux/ramips/patches-5.4/0101-staging-mt7621-pci-enable-clock-bit-for-each-port.patch')
| -rw-r--r-- | target/linux/ramips/patches-5.4/0101-staging-mt7621-pci-enable-clock-bit-for-each-port.patch | 74 |
1 files changed, 0 insertions, 74 deletions
diff --git a/target/linux/ramips/patches-5.4/0101-staging-mt7621-pci-enable-clock-bit-for-each-port.patch b/target/linux/ramips/patches-5.4/0101-staging-mt7621-pci-enable-clock-bit-for-each-port.patch deleted file mode 100644 index 3939280a16..0000000000 --- a/target/linux/ramips/patches-5.4/0101-staging-mt7621-pci-enable-clock-bit-for-each-port.patch +++ /dev/null @@ -1,74 +0,0 @@ -From 550fabd71d7fcdfe099bbf41e00e28719737161e Mon Sep 17 00:00:00 2001 -From: Sergio Paracuellos <sergio.paracuellos@gmail.com> -Date: Tue, 10 Mar 2020 12:34:59 +0100 -Subject: [PATCH] staging: mt7621-pci: enable clock bit for each port - -The clock related code concerns me from the very beginning because -there are some set ups got from legacy driver that are not documented -anywhere. According to the programming guide 0x7c is 'CPE_ROSC_SEL1' -register and 0x80 is 'CPU_CPE_CN'. I do think this set up is not needed -at all and the proper thing to do is just enable the clock bit for each -pcie port. Hence remove useless code and do the right thing which is -setting up the clock bit for each port enabled. - -Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> -Link: https://lore.kernel.org/r/20200310113459.30539-1-sergio.paracuellos@gmail.com -Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> ---- - drivers/staging/mt7621-pci/pci-mt7621.c | 17 ++++++----------- - 1 file changed, 6 insertions(+), 11 deletions(-) - ---- a/drivers/staging/mt7621-pci/pci-mt7621.c -+++ b/drivers/staging/mt7621-pci/pci-mt7621.c -@@ -45,8 +45,6 @@ - - /* rt_sysc_membase relative registers */ - #define RALINK_CLKCFG1 0x30 --#define RALINK_PCIE_CLK_GEN 0x7c --#define RALINK_PCIE_CLK_GEN1 0x80 - - /* Host-PCI bridge registers */ - #define RALINK_PCI_PCICFG_ADDR 0x0000 -@@ -85,10 +83,6 @@ - #define PCIE_PORT_CLK_EN(x) BIT(24 + (x)) - #define PCIE_PORT_LINKUP BIT(0) - --#define PCIE_CLK_GEN_EN BIT(31) --#define PCIE_CLK_GEN_DIS 0 --#define PCIE_CLK_GEN1_DIS GENMASK(30, 24) --#define PCIE_CLK_GEN1_EN (BIT(27) | BIT(25)) - #define MEMORY_BASE 0x0 - #define PERST_MODE_MASK GENMASK(11, 10) - #define PERST_MODE_GPIO BIT(10) -@@ -233,6 +227,11 @@ static inline bool mt7621_pcie_port_is_l - return (pcie_port_read(port, RALINK_PCI_STATUS) & PCIE_PORT_LINKUP) != 0; - } - -+static inline void mt7621_pcie_port_clk_enable(struct mt7621_pcie_port *port) -+{ -+ rt_sysc_m32(0, PCIE_PORT_CLK_EN(port->slot), RALINK_CLKCFG1); -+} -+ - static inline void mt7621_pcie_port_clk_disable(struct mt7621_pcie_port *port) - { - rt_sysc_m32(PCIE_PORT_CLK_EN(port->slot), 0, RALINK_CLKCFG1); -@@ -501,11 +500,6 @@ static void mt7621_pcie_init_ports(struc - } - } - -- rt_sysc_m32(0x30, 2 << 4, SYSC_REG_SYSTEM_CONFIG1); -- rt_sysc_m32(PCIE_CLK_GEN_EN, PCIE_CLK_GEN_DIS, RALINK_PCIE_CLK_GEN); -- rt_sysc_m32(PCIE_CLK_GEN1_DIS, PCIE_CLK_GEN1_EN, RALINK_PCIE_CLK_GEN1); -- rt_sysc_m32(PCIE_CLK_GEN_DIS, PCIE_CLK_GEN_EN, RALINK_PCIE_CLK_GEN); -- msleep(50); - reset_control_deassert(pcie->rst); - } - -@@ -542,6 +536,7 @@ static void mt7621_pcie_enable_ports(str - - list_for_each_entry(port, &pcie->ports, list) { - if (port->enabled) { -+ mt7621_pcie_port_clk_enable(port); - mt7621_pcie_enable_port(port); - dev_info(dev, "PCIE%d enabled\n", num_slots_enabled); - num_slots_enabled++; |