diff options
Diffstat (limited to 'target/linux/ramips/dts/mt7620a_sitecom_wlr-4100-v1-002.dts')
| -rw-r--r-- | target/linux/ramips/dts/mt7620a_sitecom_wlr-4100-v1-002.dts | 196 |
1 files changed, 196 insertions, 0 deletions
diff --git a/target/linux/ramips/dts/mt7620a_sitecom_wlr-4100-v1-002.dts b/target/linux/ramips/dts/mt7620a_sitecom_wlr-4100-v1-002.dts new file mode 100644 index 0000000000..614a6103b8 --- /dev/null +++ b/target/linux/ramips/dts/mt7620a_sitecom_wlr-4100-v1-002.dts @@ -0,0 +1,196 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "mt7620a.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> + +/ { + compatible = "sitecom,wlr-4100-v1-002", "ralink,mt7620a-soc"; + model = "Sitecom WLR-4100 v1 002"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + aliases { + led-boot = &led_power; + led-failsafe = &led_power; + led-running = &led_power; + led-upgrade = &led_power; + }; + + leds { + compatible = "gpio-leds"; + + led_power: power { + label = "amber:power"; + gpios = <&gpio0 9 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + wifi { + label = "blue:wifi"; + gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy1tpt"; + }; + + wps { + label = "white:wps"; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + }; + }; + + keys { + compatible = "gpio-keys"; + + wps { + label = "wps"; + gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; + linux,code = <KEY_WPS_BUTTON>; + }; + + reset { + label = "reset"; + gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; + linux,code = <KEY_RESTART>; + }; + }; + + gpio_export { + compatible = "gpio-export"; + #size-cells = <0>; + + usb-power { + gpio-export,name = "usb-power"; + gpio-export,output = <1>; + gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + compatible = "denx,uimage"; + label = "firmware"; + reg = <0x50000 0x790000>; + }; + + partition@7e0000 { + label = "backup"; + reg = <0x7e0000 0x10000>; + read-only; + }; + + partition@7f0000 { + label = "storage"; + reg = <0x7f0000 0x10000>; + read-only; + }; + }; + }; +}; + +ðernet { + pinctrl-names = "default"; + pinctrl-0 = <&rgmii1_pins &mdio_pins>; + + nvmem-cells = <&macaddr_factory_4>; + nvmem-cell-names = "mac-address"; + + port@5 { + status = "okay"; + + phy-mode = "rgmii"; + mediatek,fixed-link = <1000 1 1 1>; + }; + + mdio-bus { + status = "okay"; + + ethernet-phy@0 { + reg = <0>; + phy-mode = "rgmii"; + + qca,ar8327-initvals = < + 0x04 0x06200000 /* PORT0 PAD MODE CTRL */ + 0x08 0x01000000 /* PORT5 PAD MODE CTRL RX delay EN all ports 0, 5, 6 */ + 0x7c 0x0000007e /* PORT0_STATUS */ + 0x94 0x00000000 /* PORT6_STATUS */ + >; + }; + }; +}; + +&gsw { + mediatek,ephy-base = /bits/ 8 <8>; +}; + +&ehci { + status = "okay"; +}; + +&ohci { + status = "okay"; +}; + +&wmac { + status = "okay"; + + ralink,mtd-eeprom = <&factory 0x0>; +}; + +&state_default { + gpio { + groups = "uartf", "i2c", "wled", "spi refclk"; + function = "gpio"; + }; +}; + +&factory { + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_factory_4: macaddr@4 { + reg = <0x4 0x6>; + }; +}; |