diff options
Diffstat (limited to 'target/linux/orion/patches/006-add_a_separate_BRIDGE_INT_TIMER1_CLR_define.patch')
| -rw-r--r-- | target/linux/orion/patches/006-add_a_separate_BRIDGE_INT_TIMER1_CLR_define.patch | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/target/linux/orion/patches/006-add_a_separate_BRIDGE_INT_TIMER1_CLR_define.patch b/target/linux/orion/patches/006-add_a_separate_BRIDGE_INT_TIMER1_CLR_define.patch new file mode 100644 index 0000000000..75daedd84c --- /dev/null +++ b/target/linux/orion/patches/006-add_a_separate_BRIDGE_INT_TIMER1_CLR_define.patch @@ -0,0 +1,37 @@ +From: Ke Wei <kewei@marvell.com> + +Some Feroceon-based SoCs have an MBUS bridge interrupt controller +that requires writing a one instead of a zero to clear edge +interrupt sources such as timer expiry. + +This patch adds a new BRIDGE_INT_TIMER1_CLR define, which platform +code can set to either ~BRIDGE_INT_TIMER1 (write-zero-to-clear) or +BRIDGE_INT_TIMER1 (write-one-to-clear) depending on the platform. + +Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> +--- + arch/arm/plat-orion/time.c | 2 +- + include/asm-arm/arch-orion5x/orion5x.h | 1 + + 2 files changed, 2 insertions(+), 1 deletions(-) + +--- a/arch/arm/plat-orion/time.c ++++ b/arch/arm/plat-orion/time.c +@@ -74,7 +74,7 @@ + /* + * Clear and enable clockevent timer interrupt. + */ +- writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE); ++ writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE); + + u = readl(BRIDGE_MASK); + u |= BRIDGE_INT_TIMER1; +--- a/include/asm-arm/arch-orion5x/orion5x.h ++++ b/include/asm-arm/arch-orion5x/orion5x.h +@@ -152,6 +152,7 @@ + #define BRIDGE_MASK ORION5X_BRIDGE_REG(0x114) + #define BRIDGE_INT_TIMER0 0x0002 + #define BRIDGE_INT_TIMER1 0x0004 ++#define BRIDGE_INT_TIMER1_CLR ~0x0004 + #define MAIN_IRQ_CAUSE ORION5X_BRIDGE_REG(0x200) + #define MAIN_IRQ_MASK ORION5X_BRIDGE_REG(0x204) + |