diff options
Diffstat (limited to 'target/linux/mvebu')
5 files changed, 0 insertions, 353 deletions
diff --git a/target/linux/mvebu/patches-5.4/523-Revert-PCI-aardvark-Convert-to-use-pci_host_probe.patch b/target/linux/mvebu/patches-5.4/523-Revert-PCI-aardvark-Convert-to-use-pci_host_probe.patch deleted file mode 100644 index e1318e825a..0000000000 --- a/target/linux/mvebu/patches-5.4/523-Revert-PCI-aardvark-Convert-to-use-pci_host_probe.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 5e79c0c381eb085a2aa2da175eedea1950f07520 Mon Sep 17 00:00:00 2001 -From: Tomasz Maciej Nowak <tomek_n@o2.pl> -Date: Tue, 30 Apr 2019 15:37:34 +0200 -Subject: [PATCH] Revert "PCI: aardvark: Convert to use pci_host_probe()" - -This reverts commit c8e144f8ab00e6c4a070a932ef9c57db09aa41cf. ---- - drivers/pci/controller/pci-aardvark.c | 12 +++++++++++- - 1 file changed, 11 insertions(+), 1 deletion(-) - ---- a/drivers/pci/controller/pci-aardvark.c -+++ b/drivers/pci/controller/pci-aardvark.c -@@ -999,6 +999,7 @@ static int advk_pcie_probe(struct platfo - struct device *dev = &pdev->dev; - struct advk_pcie *pcie; - struct resource *res; -+ struct pci_bus *bus, *child; - struct pci_host_bridge *bridge; - int ret, irq; - -@@ -1054,13 +1055,22 @@ static int advk_pcie_probe(struct platfo - bridge->map_irq = of_irq_parse_and_map_pci; - bridge->swizzle_irq = pci_common_swizzle; - -- ret = pci_host_probe(bridge); -+ ret = pci_scan_root_bus_bridge(bridge); - if (ret < 0) { - advk_pcie_remove_msi_irq_domain(pcie); - advk_pcie_remove_irq_domain(pcie); - return ret; - } - -+ bus = bridge->bus; -+ -+ pci_bus_size_bridges(bus); -+ pci_bus_assign_resources(bus); -+ -+ list_for_each_entry(child, &bus->children, node) -+ pcie_bus_configure_settings(child); -+ -+ pci_bus_add_devices(bus); - return 0; - } - diff --git a/target/linux/mvebu/patches-5.4/524-PCI-aardvark-set-host-and-device-to-the-same-MAX-payload-size.patch b/target/linux/mvebu/patches-5.4/524-PCI-aardvark-set-host-and-device-to-the-same-MAX-payload-size.patch deleted file mode 100644 index c6cfe3783c..0000000000 --- a/target/linux/mvebu/patches-5.4/524-PCI-aardvark-set-host-and-device-to-the-same-MAX-payload-size.patch +++ /dev/null @@ -1,138 +0,0 @@ -From patchwork Thu Sep 28 12:58:34 2017 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [v2, - 3/7] PCI: aardvark: set host and device to the same MAX payload size -X-Patchwork-Submitter: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> -X-Patchwork-Id: 819587 -Message-Id: <20170928125838.11887-4-thomas.petazzoni@free-electrons.com> -To: Bjorn Helgaas <bhelgaas@google.com>, linux-pci@vger.kernel.org -Cc: Jason Cooper <jason@lakedaemon.net>, Andrew Lunn <andrew@lunn.ch>, - Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>, Gregory Clement - <gregory.clement@free-electrons.com>, - Nadav Haklai <nadavh@marvell.com>, Hanna Hawa <hannah@marvell.com>, - Yehuda Yitschak <yehuday@marvell.com>, - linux-arm-kernel@lists.infradead.org, Antoine Tenart - <antoine.tenart@free-electrons.com>, =?utf-8?q?Miqu=C3=A8l_Raynal?= - <miquel.raynal@free-electrons.com>, Victor Gu <xigu@marvell.com>, - Thomas Petazzoni <thomas.petazzoni@free-electrons.com> -Date: Thu, 28 Sep 2017 14:58:34 +0200 -From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> -List-Id: <linux-pci.vger.kernel.org> - -From: Victor Gu <xigu@marvell.com> - -Since the Aardvark does not implement a PCIe root bus, the Linux PCIe -subsystem will not align the MAX payload size between the host and the -device. This patch ensures that the host and device have the same MAX -payload size, fixing a number of problems with various PCIe devices. - -This is part of fixing bug -https://bugzilla.kernel.org/show_bug.cgi?id=196339, this commit was -reported as the user to be important to get a Intel 7260 mini-PCIe -WiFi card working. - -Fixes: Fixes: 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver") -Signed-off-by: Victor Gu <xigu@marvell.com> -Reviewed-by: Evan Wang <xswang@marvell.com> -Reviewed-by: Nadav Haklai <nadavh@marvell.com> -[Thomas: tweak commit log.] -Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> ---- - drivers/pci/controller/pci-aardvark.c | 60 ++++++++++++++++++++++++++++++++++++++++- - 1 file changed, 59 insertions(+), 1 deletion(-) - ---- a/drivers/pci/controller/pci-aardvark.c -+++ b/drivers/pci/controller/pci-aardvark.c -@@ -33,9 +33,11 @@ - #define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8 - #define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4) - #define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT 5 -+#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ 0x2 - #define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11) - #define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12 - #define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ 0x2 -+#define PCIE_CORE_MPS_UNIT_BYTE 128 - #define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0 - #define PCIE_CORE_LINK_L0S_ENTRY BIT(0) - #define PCIE_CORE_LINK_TRAINING BIT(5) -@@ -276,7 +278,8 @@ static void advk_pcie_setup_hw(struct ad - - /* Set PCIe Device Control and Status 1 PF0 register */ - reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE | -- (7 << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) | -+ (PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ << -+ PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) | - PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE | - (PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ << - PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT); -@@ -994,6 +997,58 @@ out_release_res: - return err; - } - -+static int advk_pcie_find_smpss(struct pci_dev *dev, void *data) -+{ -+ u8 *smpss = data; -+ -+ if (!dev) -+ return 0; -+ -+ if (!pci_is_pcie(dev)) -+ return 0; -+ -+ if (*smpss > dev->pcie_mpss) -+ *smpss = dev->pcie_mpss; -+ -+ return 0; -+} -+ -+static int advk_pcie_bus_configure_mps(struct pci_dev *dev, void *data) -+{ -+ int mps; -+ -+ if (!dev) -+ return 0; -+ -+ if (!pci_is_pcie(dev)) -+ return 0; -+ -+ mps = PCIE_CORE_MPS_UNIT_BYTE << *(u8 *)data; -+ pcie_set_mps(dev, mps); -+ -+ return 0; -+} -+ -+static void advk_pcie_configure_mps(struct pci_bus *bus, struct advk_pcie *pcie) -+{ -+ u8 smpss = PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ; -+ u32 reg; -+ -+ /* Find the minimal supported MAX payload size */ -+ advk_pcie_find_smpss(bus->self, &smpss); -+ pci_walk_bus(bus, advk_pcie_find_smpss, &smpss); -+ -+ /* Configure RC MAX payload size */ -+ reg = advk_readl(pcie, PCIE_CORE_DEV_CTRL_STATS_REG); -+ reg &= ~PCI_EXP_DEVCTL_PAYLOAD; -+ reg |= smpss << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT; -+ advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG); -+ -+ /* Configure device MAX payload size */ -+ advk_pcie_bus_configure_mps(bus->self, &smpss); -+ pci_walk_bus(bus, advk_pcie_bus_configure_mps, &smpss); -+} -+ - static int advk_pcie_probe(struct platform_device *pdev) - { - struct device *dev = &pdev->dev; -@@ -1070,6 +1125,9 @@ static int advk_pcie_probe(struct platfo - list_for_each_entry(child, &bus->children, node) - pcie_bus_configure_settings(child); - -+ /* Configure the MAX pay load size */ -+ advk_pcie_configure_mps(bus, pcie); -+ - pci_bus_add_devices(bus); - return 0; - } diff --git a/target/linux/mvebu/patches-5.4/526-PCI-aardvark-disable-LOS-state-by-default.patch b/target/linux/mvebu/patches-5.4/526-PCI-aardvark-disable-LOS-state-by-default.patch deleted file mode 100644 index f865965ed4..0000000000 --- a/target/linux/mvebu/patches-5.4/526-PCI-aardvark-disable-LOS-state-by-default.patch +++ /dev/null @@ -1,55 +0,0 @@ -From patchwork Thu Sep 28 12:58:36 2017 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [v2,5/7] PCI: aardvark: disable LOS state by default -X-Patchwork-Submitter: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> -X-Patchwork-Id: 819590 -Message-Id: <20170928125838.11887-6-thomas.petazzoni@free-electrons.com> -To: Bjorn Helgaas <bhelgaas@google.com>, linux-pci@vger.kernel.org -Cc: Jason Cooper <jason@lakedaemon.net>, Andrew Lunn <andrew@lunn.ch>, - Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>, Gregory Clement - <gregory.clement@free-electrons.com>, - Nadav Haklai <nadavh@marvell.com>, Hanna Hawa <hannah@marvell.com>, - Yehuda Yitschak <yehuday@marvell.com>, - linux-arm-kernel@lists.infradead.org, Antoine Tenart - <antoine.tenart@free-electrons.com>, =?utf-8?q?Miqu=C3=A8l_Raynal?= - <miquel.raynal@free-electrons.com>, Victor Gu <xigu@marvell.com>, - Thomas Petazzoni <thomas.petazzoni@free-electrons.com> -Date: Thu, 28 Sep 2017 14:58:36 +0200 -From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> -List-Id: <linux-pci.vger.kernel.org> - -From: Victor Gu <xigu@marvell.com> - -Some PCIe devices do not support LOS, and will cause timeouts if the -root complex forces the LOS state. This patch disables the LOS state -by default. - -This is part of fixing bug -https://bugzilla.kernel.org/show_bug.cgi?id=196339, this commit was -reported as the user to be important to get a Intel 7260 mini-PCIe -WiFi card working. - -Fixes: 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver") -Signed-off-by: Victor Gu <xigu@marvell.com> -Reviewed-by: Evan Wang <xswang@marvell.com> -Reviewed-by: Nadav Haklai <nadavh@marvell.com> -[Thomas: tweak commit log.] -Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> ---- - drivers/pci/controller/pci-aardvark.c | 3 +-- - 1 file changed, 1 insertion(+), 2 deletions(-) - ---- a/drivers/pci/controller/pci-aardvark.c -+++ b/drivers/pci/controller/pci-aardvark.c -@@ -347,8 +347,7 @@ static void advk_pcie_setup_hw(struct ad - - advk_pcie_wait_for_link(pcie); - -- reg = PCIE_CORE_LINK_L0S_ENTRY | -- (1 << PCIE_CORE_LINK_WIDTH_SHIFT); -+ reg = (1 << PCIE_CORE_LINK_WIDTH_SHIFT); - advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG); - - reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); diff --git a/target/linux/mvebu/patches-5.4/527-PCI-aardvark-allow-to-specify-link-capability.patch b/target/linux/mvebu/patches-5.4/527-PCI-aardvark-allow-to-specify-link-capability.patch deleted file mode 100644 index 739292c1bf..0000000000 --- a/target/linux/mvebu/patches-5.4/527-PCI-aardvark-allow-to-specify-link-capability.patch +++ /dev/null @@ -1,43 +0,0 @@ -From f70b629e488cc3f2a325ac35476f4f7ae502c5d0 Mon Sep 17 00:00:00 2001 -From: Tomasz Maciej Nowak <tmn505@gmail.com> -Date: Thu, 14 Jun 2018 14:24:40 +0200 -Subject: [PATCH 1/2] PCI: aardvark: allow to specify link capability - -Use DT of_pci_get_max_link_speed() facility to allow specifying link -capability. If none or unspecified value is given it falls back to gen2, -which is default for Armada 3700 SoC. - -Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com> ---- - drivers/pci/controller/pci-aardvark.c | 11 +++++++++-- - 1 file changed, 9 insertions(+), 2 deletions(-) - ---- a/drivers/pci/controller/pci-aardvark.c -+++ b/drivers/pci/controller/pci-aardvark.c -@@ -256,6 +256,8 @@ static void advk_pcie_wait_for_retrain(s - - static void advk_pcie_setup_hw(struct advk_pcie *pcie) - { -+ struct device *dev = &pcie->pdev->dev; -+ struct device_node *node = dev->of_node; - u32 reg; - - /* Set to Direct mode */ -@@ -290,10 +292,15 @@ static void advk_pcie_setup_hw(struct ad - PCIE_CORE_CTRL2_TD_ENABLE; - advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); - -- /* Set GEN2 */ -+ /* Set GEN */ - reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); - reg &= ~PCIE_GEN_SEL_MSK; -- reg |= SPEED_GEN_2; -+ if (of_pci_get_max_link_speed(node) == 1) -+ reg |= SPEED_GEN_1; -+ else if (of_pci_get_max_link_speed(node) == 3) -+ reg |= SPEED_GEN_3; -+ else -+ reg |= SPEED_GEN_2; - advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); - - /* Set lane X1 */ diff --git a/target/linux/mvebu/patches-5.4/528-arm64-dts-armada-3720-espressobin-set-max-link-to-ge.patch b/target/linux/mvebu/patches-5.4/528-arm64-dts-armada-3720-espressobin-set-max-link-to-ge.patch deleted file mode 100644 index d3a8f58f18..0000000000 --- a/target/linux/mvebu/patches-5.4/528-arm64-dts-armada-3720-espressobin-set-max-link-to-ge.patch +++ /dev/null @@ -1,73 +0,0 @@ -From 33f8fdcedb01680427328d710594facef7a0092c Mon Sep 17 00:00:00 2001 -From: Tomasz Maciej Nowak <tmn505@gmail.com> -Date: Thu, 14 Jun 2018 14:40:26 +0200 -Subject: [PATCH 2/2] arm64: dts: armada-3720-espressobin: set max link to gen1 - -Since the beginning there's been an issue with initializing the Atheros -based MiniPCIe wireless cards. Here's an example of kerenel log: - - OF: PCI: host bridge /soc/pcie@d0070000 ranges: - OF: PCI: MEM 0xe8000000..0xe8ffffff -> 0xe8000000 - OF: PCI: IO 0xe9000000..0xe900ffff -> 0xe9000000 - advk-pcie d0070000.pcie: link up - advk-pcie d0070000.pcie: PCI host bridge to bus 0000:00 - pci_bus 0000:00: root bus resource [bus 00-ff] - pci_bus 0000:00: root bus resource [mem0xe8000000-0xe8ffffff] - pci_bus 0000:00: root bus resource [io 0x0000-0xffff](bus address [0xe9000000-0xe900ffff]) - pci 0000:00:00.0: BAR 0: assigned [mem0xe8000000-0xe801ffff 64bit] - pci 0000:00:00.0: BAR 6: assigned [mem0xe8020000-0xe802ffff pref] - [...] - advk-pcie d0070000.pcie: Posted PIO Response Status: CA,0xe00 @ 0x3c - advk-pcie d0070000.pcie: Posted PIO Response Status: CA,0xe00 @ 0x44 - advk-pcie d0070000.pcie: Posted PIO Response Status: CA,0xe00 @ 0x4 - ath9k 0000:00:00.0: enabling device (0000 -> 0002) - advk-pcie d0070000.pcie: Posted PIO Response Status: CA,0xe00 @ 0x3c - advk-pcie d0070000.pcie: Posted PIO Response Status: CA,0xe00 @ 0xc - advk-pcie d0070000.pcie: Posted PIO Response Status: CA,0xe00 @ 0x4 - advk-pcie d0070000.pcie: Posted PIO Response Status: CA,0xe00 @ 0x40 - ath9k 0000:00:00.0: request_irq failed - advk-pcie d0070000.pcie: Posted PIO Response Status: CA,0xe00 @ 0x4 - ath9k: probe of 0000:00:00.0 failed with error -22 - -The same happens for ath5k cards, while ath10k card didn't appear at -all (not detected): - - OF: PCI: host bridge /soc/pcie@d0070000 ranges: - OF: PCI: MEM 0xe8000000..0xe8ffffff -> 0xe8000000 - OF: PCI: IO 0xe9000000..0xe900ffff -> 0xe9000000 - advk-pcie d0070000.pcie: link never came up - advk-pcie d0070000.pcie: PCI host bridge to bus 0000:00 - pci_bus 0000:00: root bus resource [bus 00-ff] - pci_bus 0000:00: root bus resource [mem0xe8000000-0xe8ffffff] - pci_bus 0000:00: root bus resource [io 0x0000-0xffff](bus address [0xe9000000-0xe900ffff]) - advk-pcie d0070000.pcie: config read/write timed out - -Following the issue on esppressobin.net forum [1] the workaround seems -to be limiting the speed of PCIe bridge to 1st generation. This fixed -the initialisation of all tested Atheros wireless cards. -The patch in the forum thread swaped registers which would limit speed -for all Armada 3700 based boards. The approach in this patch, in -conjunction with "PCI: aardvark: allow to specify link capability" patch -is less invasive, it only touches the affected board. - -For the record, the iwlwifi and mt76 cards were not affected by this -issue. - -1. http://espressobin.net/forums/topic/which-pcie-wlan-cards-are-supported - -Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com> ---- - arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts -+++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts -@@ -49,6 +49,8 @@ - phys = <&comphy1 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>; -+ -+ max-link-speed = <1>; - }; - - /* J6 */ |