diff options
Diffstat (limited to 'target/linux/layerscape/patches-5.4/302-dts-0074-arm64-dts-fsl-ls1028a-Add-Felix-switch-port-DT-node.patch')
| -rw-r--r-- | target/linux/layerscape/patches-5.4/302-dts-0074-arm64-dts-fsl-ls1028a-Add-Felix-switch-port-DT-node.patch | 102 |
1 files changed, 102 insertions, 0 deletions
diff --git a/target/linux/layerscape/patches-5.4/302-dts-0074-arm64-dts-fsl-ls1028a-Add-Felix-switch-port-DT-node.patch b/target/linux/layerscape/patches-5.4/302-dts-0074-arm64-dts-fsl-ls1028a-Add-Felix-switch-port-DT-node.patch new file mode 100644 index 0000000000..7a1aa87cf2 --- /dev/null +++ b/target/linux/layerscape/patches-5.4/302-dts-0074-arm64-dts-fsl-ls1028a-Add-Felix-switch-port-DT-node.patch @@ -0,0 +1,102 @@ +From f5f011742b6ec9ad1db54de9e8296f1d5a3ede8a Mon Sep 17 00:00:00 2001 +From: Claudiu Manoil <claudiu.manoil@nxp.com> +Date: Fri, 14 Jun 2019 19:24:27 +0300 +Subject: [PATCH] arm64: dts: fsl: ls1028a: Add Felix switch port DT node + +Add the switch device node, available on PF5, so that the +switch port sub-nodes (net devices) can be linked to +corresponding board specific phy nodes (external ports) or +have their link mode defined (internal ports). +The switch device features 6 ports, 4 with external links +and 2 internally facing to the ls1028a SoC and connected via +fixed links to 2 internal enetc ethernet contoller ports. +Add the corresponding enetc internal port device nodes, +mapped to PF2 and PF6 PCIe functions. +And don't forget to enable the 4MB BAR4 in the root complex +ECAM space, where the switch registers are mapped. + +Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com> +--- + arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 58 +++++++++++++++++++++++++- + 1 file changed, 57 insertions(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi ++++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +@@ -750,7 +750,9 @@ + /* PF1: VF0-1 BAR0 - non-prefetchable memory */ + 0x82000000 0x0 0x00000000 0x1 0xf8210000 0x0 0x020000 + /* PF1: VF0-1 BAR2 - prefetchable memory */ +- 0xc2000000 0x0 0x00000000 0x1 0xf8230000 0x0 0x020000>; ++ 0xc2000000 0x0 0x00000000 0x1 0xf8230000 0x0 0x020000 ++ /* BAR4 (PF5) - non-prefetchable memory */ ++ 0x82000000 0x0 0x00000000 0x1 0xfc000000 0x0 0x400000>; + + enetc_port0: ethernet@0,0 { + compatible = "fsl,enetc"; +@@ -766,12 +768,66 @@ + #address-cells = <1>; + #size-cells = <0>; + }; ++ ethernet@0,2 { ++ compatible = "fsl,enetc"; ++ reg = <0x000200 0 0 0 0>; ++ fixed-link { ++ speed = <1000>; ++ full-duplex; ++ }; ++ }; + ethernet@0,4 { + compatible = "fsl,enetc-ptp"; + reg = <0x000400 0 0 0 0>; + clocks = <&clockgen 4 0>; + little-endian; + }; ++ switch@0,5 { ++ compatible = "mscc,felix-switch"; ++ reg = <0x000500 0 0 0 0>; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ /* external ports */ ++ switch_port0: port@0 { ++ reg = <0>; ++ }; ++ switch_port1: port@1 { ++ reg = <1>; ++ }; ++ switch_port2: port@2 { ++ reg = <2>; ++ }; ++ switch_port3: port@3 { ++ reg = <3>; ++ }; ++ /* internal to-cpu ports */ ++ port@4 { ++ reg = <4>; ++ fixed-link { ++ speed = <1000>; ++ full-duplex; ++ }; ++ }; ++ port@5 { ++ reg = <5>; ++ fixed-link { ++ speed = <1000>; ++ full-duplex; ++ }; ++ }; ++ }; ++ }; ++ ethernet@0,6 { ++ compatible = "fsl,enetc"; ++ reg = <0x000600 0 0 0 0>; ++ fixed-link { ++ speed = <1000>; ++ full-duplex; ++ }; ++ }; + }; + + rcpm: rcpm@1e34040 { |