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path: root/target/linux/ipq40xx/patches-5.4/081-clk-fix-apss-cpu-overclocking.patch
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Diffstat (limited to 'target/linux/ipq40xx/patches-5.4/081-clk-fix-apss-cpu-overclocking.patch')
-rw-r--r--target/linux/ipq40xx/patches-5.4/081-clk-fix-apss-cpu-overclocking.patch10
1 files changed, 5 insertions, 5 deletions
diff --git a/target/linux/ipq40xx/patches-5.4/081-clk-fix-apss-cpu-overclocking.patch b/target/linux/ipq40xx/patches-5.4/081-clk-fix-apss-cpu-overclocking.patch
index de99792541..25a2020bd2 100644
--- a/target/linux/ipq40xx/patches-5.4/081-clk-fix-apss-cpu-overclocking.patch
+++ b/target/linux/ipq40xx/patches-5.4/081-clk-fix-apss-cpu-overclocking.patch
@@ -44,7 +44,7 @@ Signed-off-by: John Crispin <john@phrozen.org>
--- a/drivers/clk/qcom/gcc-ipq4019.c
+++ b/drivers/clk/qcom/gcc-ipq4019.c
-@@ -1251,6 +1251,29 @@ static const struct clk_fepll_vco gcc_fe
+@@ -1243,6 +1243,29 @@ static const struct clk_fepll_vco gcc_fe
.reg = 0x2f020,
};
@@ -74,7 +74,7 @@ Signed-off-by: John Crispin <john@phrozen.org>
/*
* Round rate function for APSS CPU PLL Clock divider.
* It looks up the frequency table and returns the next higher frequency
-@@ -1263,7 +1286,7 @@ static long clk_cpu_div_round_rate(struc
+@@ -1255,7 +1278,7 @@ static long clk_cpu_div_round_rate(struc
struct clk_hw *p_hw;
const struct freq_tbl *f;
@@ -83,7 +83,7 @@ Signed-off-by: John Crispin <john@phrozen.org>
if (!f)
return -EINVAL;
-@@ -1286,7 +1309,7 @@ static int clk_cpu_div_set_rate(struct c
+@@ -1278,7 +1301,7 @@ static int clk_cpu_div_set_rate(struct c
u32 mask;
int ret;
@@ -92,7 +92,7 @@ Signed-off-by: John Crispin <john@phrozen.org>
if (!f)
return -EINVAL;
-@@ -1313,6 +1336,7 @@ static unsigned long
+@@ -1305,6 +1328,7 @@ static unsigned long
clk_cpu_div_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
@@ -100,7 +100,7 @@ Signed-off-by: John Crispin <john@phrozen.org>
struct clk_fepll *pll = to_clk_fepll(hw);
u32 cdiv, pre_div;
u64 rate;
-@@ -1333,7 +1357,11 @@ clk_cpu_div_recalc_rate(struct clk_hw *h
+@@ -1325,7 +1349,11 @@ clk_cpu_div_recalc_rate(struct clk_hw *h
rate = clk_fepll_vco_calc_rate(pll, parent_rate) * 2;
do_div(rate, pre_div);