diff options
Diffstat (limited to 'target/linux/generic/backport-5.10/814-v6.4-0013-nvmem-mtk-efuse-Support-postprocessing-for-GPU-speed.patch')
| -rw-r--r-- | target/linux/generic/backport-5.10/814-v6.4-0013-nvmem-mtk-efuse-Support-postprocessing-for-GPU-speed.patch | 120 |
1 files changed, 0 insertions, 120 deletions
diff --git a/target/linux/generic/backport-5.10/814-v6.4-0013-nvmem-mtk-efuse-Support-postprocessing-for-GPU-speed.patch b/target/linux/generic/backport-5.10/814-v6.4-0013-nvmem-mtk-efuse-Support-postprocessing-for-GPU-speed.patch deleted file mode 100644 index abda402bdd..0000000000 --- a/target/linux/generic/backport-5.10/814-v6.4-0013-nvmem-mtk-efuse-Support-postprocessing-for-GPU-speed.patch +++ /dev/null @@ -1,120 +0,0 @@ -From de6e05097f7db066afb0ad4c88b730949f7b7749 Mon Sep 17 00:00:00 2001 -From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> -Date: Tue, 4 Apr 2023 18:21:35 +0100 -Subject: [PATCH] nvmem: mtk-efuse: Support postprocessing for GPU speed - binning data - -On some MediaTek SoCs GPU speed binning data is available for read -in the SoC's eFuse array but it has a format that is incompatible -with what the OPP API expects, as we read a number from 0 to 7 but -opp-supported-hw is expecting a bitmask to enable an OPP entry: -being what we read limited to 0-7, it's straightforward to simply -convert the value to BIT(value) as a post-processing action. - -So, introduce post-processing support and enable it by evaluating -the newly introduced platform data's `uses_post_processing` member, -currently enabled only for MT8186. - -Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> -Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> -Link: https://lore.kernel.org/r/20230404172148.82422-28-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> ---- - drivers/nvmem/mtk-efuse.c | 53 +++++++++++++++++++++++++++++++++++++-- - 1 file changed, 51 insertions(+), 2 deletions(-) - ---- a/drivers/nvmem/mtk-efuse.c -+++ b/drivers/nvmem/mtk-efuse.c -@@ -10,6 +10,11 @@ - #include <linux/io.h> - #include <linux/nvmem-provider.h> - #include <linux/platform_device.h> -+#include <linux/property.h> -+ -+struct mtk_efuse_pdata { -+ bool uses_post_processing; -+}; - - struct mtk_efuse_priv { - void __iomem *base; -@@ -29,6 +34,37 @@ static int mtk_reg_read(void *context, - return 0; - } - -+static int mtk_efuse_gpu_speedbin_pp(void *context, const char *id, int index, -+ unsigned int offset, void *data, size_t bytes) -+{ -+ u8 *val = data; -+ -+ if (val[0] < 8) -+ val[0] = BIT(val[0]); -+ -+ return 0; -+} -+ -+static void mtk_efuse_fixup_cell_info(struct nvmem_device *nvmem, -+ struct nvmem_layout *layout, -+ struct nvmem_cell_info *cell) -+{ -+ size_t sz = strlen(cell->name); -+ -+ /* -+ * On some SoCs, the GPU speedbin is not read as bitmask but as -+ * a number with range [0-7] (max 3 bits): post process to use -+ * it in OPP tables to describe supported-hw. -+ */ -+ if (cell->nbits <= 3 && -+ strncmp(cell->name, "gpu-speedbin", min(sz, strlen("gpu-speedbin"))) == 0) -+ cell->read_post_process = mtk_efuse_gpu_speedbin_pp; -+} -+ -+static struct nvmem_layout mtk_efuse_layout = { -+ .fixup_cell_info = mtk_efuse_fixup_cell_info, -+}; -+ - static int mtk_efuse_probe(struct platform_device *pdev) - { - struct device *dev = &pdev->dev; -@@ -36,6 +72,7 @@ static int mtk_efuse_probe(struct platfo - struct nvmem_device *nvmem; - struct nvmem_config econfig = {}; - struct mtk_efuse_priv *priv; -+ const struct mtk_efuse_pdata *pdata; - - priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); - if (!priv) -@@ -45,20 +82,32 @@ static int mtk_efuse_probe(struct platfo - if (IS_ERR(priv->base)) - return PTR_ERR(priv->base); - -+ pdata = device_get_match_data(dev); - econfig.stride = 1; - econfig.word_size = 1; - econfig.reg_read = mtk_reg_read; - econfig.size = resource_size(res); - econfig.priv = priv; - econfig.dev = dev; -+ if (pdata->uses_post_processing) -+ econfig.layout = &mtk_efuse_layout; - nvmem = devm_nvmem_register(dev, &econfig); - - return PTR_ERR_OR_ZERO(nvmem); - } - -+static const struct mtk_efuse_pdata mtk_mt8186_efuse_pdata = { -+ .uses_post_processing = true, -+}; -+ -+static const struct mtk_efuse_pdata mtk_efuse_pdata = { -+ .uses_post_processing = false, -+}; -+ - static const struct of_device_id mtk_efuse_of_match[] = { -- { .compatible = "mediatek,mt8173-efuse",}, -- { .compatible = "mediatek,efuse",}, -+ { .compatible = "mediatek,mt8173-efuse", .data = &mtk_efuse_pdata }, -+ { .compatible = "mediatek,mt8186-efuse", .data = &mtk_mt8186_efuse_pdata }, -+ { .compatible = "mediatek,efuse", .data = &mtk_efuse_pdata }, - {/* sentinel */}, - }; - MODULE_DEVICE_TABLE(of, mtk_efuse_of_match); |