diff options
Diffstat (limited to 'target/linux/generic-2.6/files/drivers/ssb')
| -rw-r--r-- | target/linux/generic-2.6/files/drivers/ssb/Kconfig | 117 | ||||
| -rw-r--r-- | target/linux/generic-2.6/files/drivers/ssb/Makefile | 18 | ||||
| -rw-r--r-- | target/linux/generic-2.6/files/drivers/ssb/b43_pci_bridge.c | 50 | ||||
| -rw-r--r-- | target/linux/generic-2.6/files/drivers/ssb/driver_chipcommon.c | 445 | ||||
| -rw-r--r-- | target/linux/generic-2.6/files/drivers/ssb/driver_extif.c | 129 | ||||
| -rw-r--r-- | target/linux/generic-2.6/files/drivers/ssb/driver_mipscore.c | 225 | ||||
| -rw-r--r-- | target/linux/generic-2.6/files/drivers/ssb/driver_pcicore.c | 576 | ||||
| -rw-r--r-- | target/linux/generic-2.6/files/drivers/ssb/main.c | 1169 | ||||
| -rw-r--r-- | target/linux/generic-2.6/files/drivers/ssb/pci.c | 790 | ||||
| -rw-r--r-- | target/linux/generic-2.6/files/drivers/ssb/pcihost_wrapper.c | 104 | ||||
| -rw-r--r-- | target/linux/generic-2.6/files/drivers/ssb/pcmcia.c | 287 | ||||
| -rw-r--r-- | target/linux/generic-2.6/files/drivers/ssb/scan.c | 424 | ||||
| -rw-r--r-- | target/linux/generic-2.6/files/drivers/ssb/ssb_private.h | 136 |
13 files changed, 0 insertions, 4470 deletions
diff --git a/target/linux/generic-2.6/files/drivers/ssb/Kconfig b/target/linux/generic-2.6/files/drivers/ssb/Kconfig deleted file mode 100644 index d976660cb7..0000000000 --- a/target/linux/generic-2.6/files/drivers/ssb/Kconfig +++ /dev/null @@ -1,117 +0,0 @@ -menu "Sonics Silicon Backplane" - -config SSB_POSSIBLE - bool - depends on HAS_IOMEM - default y - -config SSB - tristate "Sonics Silicon Backplane support" - depends on SSB_POSSIBLE - help - Support for the Sonics Silicon Backplane bus. - You only need to enable this option, if you are - configuring a kernel for an embedded system with - this bus. - It will be auto-selected if needed in other - environments. - - The module will be called ssb. - - If unsure, say N. - -config SSB_PCIHOST_POSSIBLE - bool - depends on SSB && (PCI = y || PCI = SSB) - default y - -config SSB_PCIHOST - bool "Support for SSB on PCI-bus host" - depends on SSB_PCIHOST_POSSIBLE - default y - help - Support for a Sonics Silicon Backplane on top - of a PCI device. - - If unsure, say Y - -config SSB_PCMCIAHOST_POSSIBLE - bool - depends on SSB && (PCMCIA = y || PCMCIA = SSB) && EXPERIMENTAL - default y - -config SSB_PCMCIAHOST - bool "Support for SSB on PCMCIA-bus host (EXPERIMENTAL)" - depends on SSB_PCMCIAHOST_POSSIBLE - help - Support for a Sonics Silicon Backplane on top - of a PCMCIA device. - - If unsure, say N - -config SSB_SILENT - bool "No SSB kernel messages" - depends on SSB && EMBEDDED - help - This option turns off all Sonics Silicon Backplane printks. - Note that you won't be able to identify problems, once - messages are turned off. - This might only be desired for production kernels on - embedded devices to reduce the kernel size. - - Say N - -config SSB_DEBUG - bool "SSB debugging" - depends on SSB && !SSB_SILENT - help - This turns on additional runtime checks and debugging - messages. Turn this on for SSB troubleshooting. - - If unsure, say N - -config SSB_SERIAL - bool - depends on SSB - # ChipCommon and ExtIf serial support routines. - -config SSB_DRIVER_PCICORE_POSSIBLE - bool - depends on SSB_PCIHOST - default y - -config SSB_DRIVER_PCICORE - bool "SSB PCI core driver" - depends on SSB_DRIVER_PCICORE_POSSIBLE - help - Driver for the Sonics Silicon Backplane attached - Broadcom PCI core. - - If unsure, say Y - -config SSB_PCICORE_HOSTMODE - bool "Hostmode support for SSB PCI core (EXPERIMENTAL)" - depends on SSB_DRIVER_PCICORE && SSB_DRIVER_MIPS && EXPERIMENTAL - help - PCIcore hostmode operation (external PCI bus). - -config SSB_DRIVER_MIPS - bool "SSB Broadcom MIPS core driver (EXPERIMENTAL)" - depends on SSB && MIPS && EXPERIMENTAL - select SSB_SERIAL - help - Driver for the Sonics Silicon Backplane attached - Broadcom MIPS core. - - If unsure, say N - -config SSB_DRIVER_EXTIF - bool "SSB Broadcom EXTIF core driver (EXPERIMENTAL)" - depends on SSB_DRIVER_MIPS && EXPERIMENTAL - help - Driver for the Sonics Silicon Backplane attached - Broadcom EXTIF core. - - If unsure, say N - -endmenu diff --git a/target/linux/generic-2.6/files/drivers/ssb/Makefile b/target/linux/generic-2.6/files/drivers/ssb/Makefile deleted file mode 100644 index 7be3975958..0000000000 --- a/target/linux/generic-2.6/files/drivers/ssb/Makefile +++ /dev/null @@ -1,18 +0,0 @@ -# core -ssb-y += main.o scan.o - -# host support -ssb-$(CONFIG_SSB_PCIHOST) += pci.o pcihost_wrapper.o -ssb-$(CONFIG_SSB_PCMCIAHOST) += pcmcia.o - -# built-in drivers -ssb-y += driver_chipcommon.o -ssb-$(CONFIG_SSB_DRIVER_MIPS) += driver_mipscore.o -ssb-$(CONFIG_SSB_DRIVER_EXTIF) += driver_extif.o -ssb-$(CONFIG_SSB_DRIVER_PCICORE) += driver_pcicore.o - -# b43 pci-ssb-bridge driver -# Not strictly a part of SSB, but kept here for convenience -ssb-$(CONFIG_SSB_PCIHOST) += b43_pci_bridge.o - -obj-$(CONFIG_SSB) += ssb.o diff --git a/target/linux/generic-2.6/files/drivers/ssb/b43_pci_bridge.c b/target/linux/generic-2.6/files/drivers/ssb/b43_pci_bridge.c deleted file mode 100644 index 2d27d6d6d0..0000000000 --- a/target/linux/generic-2.6/files/drivers/ssb/b43_pci_bridge.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Broadcom 43xx PCI-SSB bridge module - * - * This technically is a separate PCI driver module, but - * because of its small size we include it in the SSB core - * instead of creating a standalone module. - * - * Copyright 2007 Michael Buesch <mb@bu3sch.de> - * - * Licensed under the GNU/GPL. See COPYING for details. - */ - -#include <linux/pci.h> -#include <linux/ssb/ssb.h> - -#include "ssb_private.h" - - -static const struct pci_device_id b43_pci_bridge_tbl[] = { - { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4301) }, - { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4307) }, - { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4311) }, - { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4312) }, - { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4318) }, - { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4319) }, - { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4320) }, - { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4321) }, - { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4324) }, - { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4325) }, - { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4328) }, - { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4329) }, - { 0, }, -}; -MODULE_DEVICE_TABLE(pci, b43_pci_bridge_tbl); - -static struct pci_driver b43_pci_bridge_driver = { - .name = "b43-pci-bridge", - .id_table = b43_pci_bridge_tbl, -}; - - -int __init b43_pci_ssb_bridge_init(void) -{ - return ssb_pcihost_register(&b43_pci_bridge_driver); -} - -void __exit b43_pci_ssb_bridge_exit(void) -{ - ssb_pcihost_unregister(&b43_pci_bridge_driver); -} diff --git a/target/linux/generic-2.6/files/drivers/ssb/driver_chipcommon.c b/target/linux/generic-2.6/files/drivers/ssb/driver_chipcommon.c deleted file mode 100644 index 6fbf1c53b6..0000000000 --- a/target/linux/generic-2.6/files/drivers/ssb/driver_chipcommon.c +++ /dev/null @@ -1,445 +0,0 @@ -/* - * Sonics Silicon Backplane - * Broadcom ChipCommon core driver - * - * Copyright 2005, Broadcom Corporation - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de> - * - * Licensed under the GNU/GPL. See COPYING for details. - */ - -#include <linux/ssb/ssb.h> -#include <linux/ssb/ssb_regs.h> -#include <linux/pci.h> - -#include "ssb_private.h" - - -/* Clock sources */ -enum ssb_clksrc { - /* PCI clock */ - SSB_CHIPCO_CLKSRC_PCI, - /* Crystal slow clock oscillator */ - SSB_CHIPCO_CLKSRC_XTALOS, - /* Low power oscillator */ - SSB_CHIPCO_CLKSRC_LOPWROS, -}; - - -static inline u32 chipco_read32(struct ssb_chipcommon *cc, - u16 offset) -{ - return ssb_read32(cc->dev, offset); -} - -static inline void chipco_write32(struct ssb_chipcommon *cc, - u16 offset, - u32 value) -{ - ssb_write32(cc->dev, offset, value); -} - -static inline void chipco_write32_masked(struct ssb_chipcommon *cc, u16 offset, - u32 mask, u32 value) -{ - value &= mask; - value |= chipco_read32(cc, offset) & ~mask; - chipco_write32(cc, offset, value); -} - -void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc, - enum ssb_clkmode mode) -{ - struct ssb_device *ccdev = cc->dev; - struct ssb_bus *bus; - u32 tmp; - - if (!ccdev) - return; - bus = ccdev->bus; - /* chipcommon cores prior to rev6 don't support dynamic clock control */ - if (ccdev->id.revision < 6) - return; - /* chipcommon cores rev10 are a whole new ball game */ - if (ccdev->id.revision >= 10) - return; - if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL)) - return; - - switch (mode) { - case SSB_CLKMODE_SLOW: - tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL); - tmp |= SSB_CHIPCO_SLOWCLKCTL_FSLOW; - chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp); - break; - case SSB_CLKMODE_FAST: - ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */ - tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL); - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW; - tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL; - chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp); - break; - case SSB_CLKMODE_DYNAMIC: - tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL); - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW; - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL; - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL; - if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) != SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL) - tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL; - chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp); - - /* for dynamic control, we have to release our xtal_pu "force on" */ - if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL) - ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0); - break; - default: - SSB_WARN_ON(1); - } -} - -/* Get the Slow Clock Source */ -static enum ssb_clksrc chipco_pctl_get_slowclksrc(struct ssb_chipcommon *cc) -{ - struct ssb_bus *bus = cc->dev->bus; - u32 uninitialized_var(tmp); - - if (cc->dev->id.revision < 6) { - if (bus->bustype == SSB_BUSTYPE_SSB || - bus->bustype == SSB_BUSTYPE_PCMCIA) - return SSB_CHIPCO_CLKSRC_XTALOS; - if (bus->bustype == SSB_BUSTYPE_PCI) { - pci_read_config_dword(bus->host_pci, SSB_GPIO_OUT, &tmp); - if (tmp & 0x10) - return SSB_CHIPCO_CLKSRC_PCI; - return SSB_CHIPCO_CLKSRC_XTALOS; - } - } - if (cc->dev->id.revision < 10) { - tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL); - tmp &= 0x7; - if (tmp == 0) - return SSB_CHIPCO_CLKSRC_LOPWROS; - if (tmp == 1) - return SSB_CHIPCO_CLKSRC_XTALOS; - if (tmp == 2) - return SSB_CHIPCO_CLKSRC_PCI; - } - - return SSB_CHIPCO_CLKSRC_XTALOS; -} - -/* Get maximum or minimum (depending on get_max flag) slowclock frequency. */ -static int chipco_pctl_clockfreqlimit(struct ssb_chipcommon *cc, int get_max) -{ - int uninitialized_var(limit); - enum ssb_clksrc clocksrc; - int divisor = 1; - u32 tmp; - - clocksrc = chipco_pctl_get_slowclksrc(cc); - if (cc->dev->id.revision < 6) { - switch (clocksrc) { - case SSB_CHIPCO_CLKSRC_PCI: - divisor = 64; - break; - case SSB_CHIPCO_CLKSRC_XTALOS: - divisor = 32; - break; - default: - SSB_WARN_ON(1); - } - } else if (cc->dev->id.revision < 10) { - switch (clocksrc) { - case SSB_CHIPCO_CLKSRC_LOPWROS: - break; - case SSB_CHIPCO_CLKSRC_XTALOS: - case SSB_CHIPCO_CLKSRC_PCI: - tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL); - divisor = (tmp >> 16) + 1; - divisor *= 4; - break; - } - } else { - tmp = chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL); - divisor = (tmp >> 16) + 1; - divisor *= 4; - } - - switch (clocksrc) { - case SSB_CHIPCO_CLKSRC_LOPWROS: - if (get_max) - limit = 43000; - else - limit = 25000; - break; - case SSB_CHIPCO_CLKSRC_XTALOS: - if (get_max) - limit = 20200000; - else - limit = 19800000; - break; - case SSB_CHIPCO_CLKSRC_PCI: - if (get_max) - limit = 34000000; - else - limit = 25000000; - break; - } - limit /= divisor; - - return limit; -} - -static void chipco_powercontrol_init(struct ssb_chipcommon *cc) -{ - struct ssb_bus *bus = cc->dev->bus; - - if (bus->chip_id == 0x4321) { - if (bus->chip_rev == 0) - chipco_write32(cc, SSB_CHIPCO_CHIPCTL, 0x3A4); - else if (bus->chip_rev == 1) - chipco_write32(cc, SSB_CHIPCO_CHIPCTL, 0xA4); - } - - if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL)) - return; - - if (cc->dev->id.revision >= 10) { - /* Set Idle Power clock rate to 1Mhz */ - chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL, - (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) & - 0x0000FFFF) | 0x00040000); - } else { - int maxfreq; - - maxfreq = chipco_pctl_clockfreqlimit(cc, 1); - chipco_write32(cc, SSB_CHIPCO_PLLONDELAY, - (maxfreq * 150 + 999999) / 1000000); - chipco_write32(cc, SSB_CHIPCO_FREFSELDELAY, - (maxfreq * 15 + 999999) / 1000000); - } -} - -static void calc_fast_powerup_delay(struct ssb_chipcommon *cc) -{ - struct ssb_bus *bus = cc->dev->bus; - int minfreq; - unsigned int tmp; - u32 pll_on_delay; - - if (bus->bustype != SSB_BUSTYPE_PCI) - return; - if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL)) - return; - - minfreq = chipco_pctl_clockfreqlimit(cc, 0); - pll_on_delay = chipco_read32(cc, SSB_CHIPCO_PLLONDELAY); - tmp = (((pll_on_delay + 2) * 1000000) + (minfreq - 1)) / minfreq; - SSB_WARN_ON(tmp & ~0xFFFF); - - cc->fast_pwrup_delay = tmp; -} - -void ssb_chipcommon_init(struct ssb_chipcommon *cc) -{ - if (!cc->dev) - return; /* We don't have a ChipCommon */ - chipco_powercontrol_init(cc); - ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST); - calc_fast_powerup_delay(cc); -} - -void ssb_chipco_suspend(struct ssb_chipcommon *cc, pm_message_t state) -{ - if (!cc->dev) - return; - ssb_chipco_set_clockmode(cc, SSB_CLKMODE_SLOW); -} - -void ssb_chipco_resume(struct ssb_chipcommon *cc) -{ - if (!cc->dev) - return; - chipco_powercontrol_init(cc); - ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST); -} - -/* Get the processor clock */ -void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc, - u32 *plltype, u32 *n, u32 *m) -{ - *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N); - *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT); - switch (*plltype) { - case SSB_PLLTYPE_2: - case SSB_PLLTYPE_4: - case SSB_PLLTYPE_6: - case SSB_PLLTYPE_7: - *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_MIPS); - break; - case SSB_PLLTYPE_3: - /* 5350 uses m2 to control mips */ - *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_M2); - break; - default: - *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_SB); - break; - } -} - -/* Get the bus clock */ -void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc, - u32 *plltype, u32 *n, u32 *m) -{ - *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N); - *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT); - switch (*plltype) { - case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */ - *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_MIPS); - break; - case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */ - if (cc->dev->bus->chip_id != 0x5365) { - *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_M2); - break; - } - /* Fallthough */ - default: - *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_SB); - } -} - -void ssb_chipco_timing_init(struct ssb_chipcommon *cc, - unsigned long ns) -{ - struct ssb_device *dev = cc->dev; - struct ssb_bus *bus = dev->bus; - u32 tmp; - - /* set register for external IO to control LED. */ - chipco_write32(cc, SSB_CHIPCO_PROG_CFG, 0x11); - tmp = DIV_ROUND_UP(10, ns) << SSB_PROG_WCNT_3_SHIFT; /* Waitcount-3 = 10ns */ - tmp |= DIV_ROUND_UP(40, ns) << SSB_PROG_WCNT_1_SHIFT; /* Waitcount-1 = 40ns */ - tmp |= DIV_ROUND_UP(240, ns); /* Waitcount-0 = 240ns */ - chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp); /* 0x01020a0c for a 100Mhz clock */ - - /* Set timing for the flash */ - tmp = DIV_ROUND_UP(10, ns) << SSB_FLASH_WCNT_3_SHIFT; /* Waitcount-3 = 10nS */ - tmp |= DIV_ROUND_UP(10, ns) << SSB_FLASH_WCNT_1_SHIFT; /* Waitcount-1 = 10nS */ - tmp |= DIV_ROUND_UP(120, ns); /* Waitcount-0 = 120nS */ - if ((bus->chip_id == 0x5365) || - (dev->id.revision < 9)) - chipco_write32(cc, SSB_CHIPCO_FLASH_WAITCNT, tmp); - if ((bus->chip_id == 0x5365) || - (dev->id.revision < 9) || - ((bus->chip_id == 0x5350) && (bus->chip_rev == 0))) - chipco_write32(cc, SSB_CHIPCO_PCMCIA_MEMWAIT, tmp); - - if (bus->chip_id == 0x5350) { - /* Enable EXTIF */ - tmp = DIV_ROUND_UP(10, ns) << SSB_PROG_WCNT_3_SHIFT; /* Waitcount-3 = 10ns */ - tmp |= DIV_ROUND_UP(20, ns) << SSB_PROG_WCNT_2_SHIFT; /* Waitcount-2 = 20ns */ - tmp |= DIV_ROUND_UP(100, ns) << SSB_PROG_WCNT_1_SHIFT; /* Waitcount-1 = 100ns */ - tmp |= DIV_ROUND_UP(120, ns); /* Waitcount-0 = 120ns */ - chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp); /* 0x01020a0c for a 100Mhz clock */ - } -} - -/* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */ -void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks) -{ - /* instant NMI */ - chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks); -} - -u32 ssb_chipco_gpio_in(struct ssb_chipcommon *cc, u32 mask) -{ - return chipco_read32(cc, SSB_CHIPCO_GPIOIN) & mask; -} - -void ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value) -{ - chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value); -} - -void ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value) -{ - chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value); -} - -#ifdef CONFIG_SSB_SERIAL -int ssb_chipco_serial_init(struct ssb_chipcommon *cc, - struct ssb_serial_port *ports) -{ - struct ssb_bus *bus = cc->dev->bus; - int nr_ports = 0; - u32 plltype; - unsigned int irq; - u32 baud_base, div; - u32 i, n; - - plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT); - irq = ssb_mips_irq(cc->dev); - - if (plltype == SSB_PLLTYPE_1) { - /* PLL clock */ - baud_base = ssb_calc_clock_rate(plltype, - chipco_read32(cc, SSB_CHIPCO_CLOCK_N), - chipco_read32(cc, SSB_CHIPCO_CLOCK_M2)); - div = 1; - } else { - if (cc->dev->id.revision >= 11) { - /* Fixed ALP clock */ - baud_base = 20000000; - div = 1; - /* Set the override bit so we don't divide it */ - chipco_write32(cc, SSB_CHIPCO_CORECTL, - SSB_CHIPCO_CORECTL_UARTCLK0); - } else if (cc->dev->id.revision >= 3) { - /* Internal backplane clock */ - baud_base = ssb_clockspeed(bus); - div = chipco_read32(cc, SSB_CHIPCO_CLKDIV) - & SSB_CHIPCO_CLKDIV_UART; - } else { - /* Fixed internal backplane clock */ - baud_base = 88000000; - div = 48; - } - - /* Clock source depends on strapping if UartClkOverride is unset */ - if ((cc->dev->id.revision > 0) && - !(chipco_read32(cc, SSB_CHIPCO_CORECTL) & SSB_CHIPCO_CORECTL_UARTCLK0)) { - if ((cc->capabilities & SSB_CHIPCO_CAP_UARTCLK) == - SSB_CHIPCO_CAP_UARTCLK_INT) { - /* Internal divided backplane clock */ - baud_base /= div; - } else { - /* Assume external clock of 1.8432 MHz */ - baud_base = 1843200; - } - } - } - - /* Determine the registers of the UARTs */ - n = (cc->capabilities & SSB_CHIPCO_CAP_NRUART); - for (i = 0; i < n; i++) { - void __iomem *cc_mmio; - void __iomem *uart_regs; - - cc_mmio = cc->dev->bus->mmio + (cc->dev->core_index * SSB_CORE_SIZE); - uart_regs = cc_mmio + SSB_CHIPCO_UART0_DATA; - /* Offset changed at after rev 0 */ - if (cc->dev->id.revision == 0) - uart_regs += (i * 8); - else - uart_regs += (i * 256); - - nr_ports++; - ports[i].regs = uart_regs; - ports[i].irq = irq; - ports[i].baud_base = baud_base; - ports[i].reg_shift = 0; - } - - return nr_ports; -} -#endif /* CONFIG_SSB_SERIAL */ diff --git a/target/linux/generic-2.6/files/drivers/ssb/driver_extif.c b/target/linux/generic-2.6/files/drivers/ssb/driver_extif.c deleted file mode 100644 index fe55eb8b03..0000000000 --- a/target/linux/generic-2.6/files/drivers/ssb/driver_extif.c +++ /dev/null @@ -1,129 +0,0 @@ -/* - * Sonics Silicon Backplane - * Broadcom EXTIF core driver - * - * Copyright 2005, Broadcom Corporation - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de> - * Copyright 2006, 2007, Felix Fietkau <nbd@openwrt.org> - * Copyright 2007, Aurelien Jarno <aurelien@aurel32.net> - * - * Licensed under the GNU/GPL. See COPYING for details. - */ - -#include <linux/serial.h> -#include <linux/serial_core.h> -#include <linux/serial_reg.h> - -#include "ssb_private.h" - - -static inline u32 extif_read32(struct ssb_extif *extif, u16 offset) -{ - return ssb_read32(extif->dev, offset); -} - -static inline void extif_write32(struct ssb_extif *extif, u16 offset, u32 value) -{ - ssb_write32(extif->dev, offset, value); -} - -static inline void extif_write32_masked(struct ssb_extif *extif, u16 offset, - u32 mask, u32 value) -{ - value &= mask; - value |= extif_read32(extif, offset) & ~mask; - extif_write32(extif, offset, value); -} - -#ifdef CONFIG_SSB_SERIAL -static bool serial_exists(u8 *regs) -{ - u8 save_mcr, msr = 0; - - if (regs) { - save_mcr = regs[UART_MCR]; - regs[UART_MCR] = (UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_RTS); - msr = regs[UART_MSR] & (UART_MSR_DCD | UART_MSR_RI - | UART_MSR_CTS | UART_MSR_DSR); - regs[UART_MCR] = save_mcr; - } - return (msr == (UART_MSR_DCD | UART_MSR_CTS)); -} - -int ssb_extif_serial_init(struct ssb_extif *extif, struct ssb_serial_port *ports) -{ - u32 i, nr_ports = 0; - - /* Disable GPIO interrupt initially */ - extif_write32(extif, SSB_EXTIF_GPIO_INTPOL, 0); - extif_write32(extif, SSB_EXTIF_GPIO_INTMASK, 0); - - for (i = 0; i < 2; i++) { - void __iomem *uart_regs; - - uart_regs = ioremap_nocache(SSB_EUART, 16); - if (uart_regs) { - uart_regs += (i * 8); - - if (serial_exists(uart_regs) && ports) { - extif_write32(extif, SSB_EXTIF_GPIO_INTMASK, 2); - - nr_ports++; - ports[i].regs = uart_regs; - ports[i].irq = 2; - ports[i].baud_base = 13500000; - ports[i].reg_shift = 0; - } - iounmap(uart_regs); - } - } - return nr_ports; -} -#endif /* CONFIG_SSB_SERIAL */ - -void ssb_extif_timing_init(struct ssb_extif *extif, unsigned long ns) -{ - u32 tmp; - - /* Initialize extif so we can get to the LEDs and external UART */ - extif_write32(extif, SSB_EXTIF_PROG_CFG, SSB_EXTCFG_EN); - - /* Set timing for the flash */ - tmp = DIV_ROUND_UP(10, ns) << SSB_PROG_WCNT_3_SHIFT; - tmp |= DIV_ROUND_UP(40, ns) << SSB_PROG_WCNT_1_SHIFT; - tmp |= DIV_ROUND_UP(120, ns); - extif_write32(extif, SSB_EXTIF_PROG_WAITCNT, tmp); - - /* Set programmable interface timing for external uart */ - tmp = DIV_ROUND_UP(10, ns) << SSB_PROG_WCNT_3_SHIFT; - tmp |= DIV_ROUND_UP(20, ns) << SSB_PROG_WCNT_2_SHIFT; - tmp |= DIV_ROUND_UP(100, ns) << SSB_PROG_WCNT_1_SHIFT; - tmp |= DIV_ROUND_UP(120, ns); - extif_write32(extif, SSB_EXTIF_PROG_WAITCNT, tmp); -} - -void ssb_extif_get_clockcontrol(struct ssb_extif *extif, - u32 *pll_type, u32 *n, u32 *m) -{ - *pll_type = SSB_PLLTYPE_1; - *n = extif_read32(extif, SSB_EXTIF_CLOCK_N); - *m = extif_read32(extif, SSB_EXTIF_CLOCK_SB); -} - -u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask) -{ - return extif_read32(extif, SSB_EXTIF_GPIO_IN) & mask; -} - -void ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask, u32 value) -{ - return extif_write32_masked(extif, SSB_EXTIF_GPIO_OUT(0), - mask, value); -} - -void ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask, u32 value) -{ - return extif_write32_masked(extif, SSB_EXTIF_GPIO_OUTEN(0), - mask, value); -} - diff --git a/target/linux/generic-2.6/files/drivers/ssb/driver_mipscore.c b/target/linux/generic-2.6/files/drivers/ssb/driver_mipscore.c deleted file mode 100644 index a9e7eb45b2..0000000000 --- a/target/linux/generic-2.6/files/drivers/ssb/driver_mipscore.c +++ /dev/null @@ -1,225 +0,0 @@ -/* - * Sonics Silicon Backplane - * Broadcom MIPS core driver - * - * Copyright 2005, Broadcom Corporation - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de> - * - * Licensed under the GNU/GPL. See COPYING for details. - */ - -#include <linux/ssb/ssb.h> - -#include <linux/serial.h> -#include <linux/serial_core.h> -#include <linux/serial_reg.h> -#include <linux/time.h> - -#include "ssb_private.h" - - -static inline u32 mips_read32(struct ssb_mipscore *mcore, - u16 offset) -{ - return ssb_read32(mcore->dev, offset); -} - -static inline void mips_write32(struct ssb_mipscore *mcore, - u16 offset, - u32 value) -{ - ssb_write32(mcore->dev, offset, value); -} - -static const u32 ipsflag_irq_mask[] = { - 0, - SSB_IPSFLAG_IRQ1, - SSB_IPSFLAG_IRQ2, - SSB_IPSFLAG_IRQ3, - SSB_IPSFLAG_IRQ4, -}; - -static const u32 ipsflag_irq_shift[] = { - 0, - SSB_IPSFLAG_IRQ1_SHIFT, - SSB_IPSFLAG_IRQ2_SHIFT, - SSB_IPSFLAG_IRQ3_SHIFT, - SSB_IPSFLAG_IRQ4_SHIFT, -}; - -static inline u32 ssb_irqflag(struct ssb_device *dev) -{ - return ssb_read32(dev, SSB_TPSFLAG) & SSB_TPSFLAG_BPFLAG; -} - -/* Get the MIPS IRQ assignment for a specified device. - * If unassigned, 0 is returned. - */ -unsigned int ssb_mips_irq(struct ssb_device *dev) -{ - struct ssb_bus *bus = dev->bus; - u32 irqflag; - u32 ipsflag; - u32 tmp; - unsigned int irq; - - irqflag = ssb_irqflag(dev); - ipsflag = ssb_read32(bus->mipscore.dev, SSB_IPSFLAG); - for (irq = 1; irq <= 4; irq++) { - tmp = ((ipsflag & ipsflag_irq_mask[irq]) >> ipsflag_irq_shift[irq]); - if (tmp == irqflag) - break; - } - if (irq == 5) - irq = 0; - - return irq; -} - -static void clear_irq(struct ssb_bus *bus, unsigned int irq) -{ - struct ssb_device *dev = bus->mipscore.dev; - - /* Clear the IRQ in the MIPScore backplane registers */ - if (irq == 0) { - ssb_write32(dev, SSB_INTVEC, 0); - } else { - ssb_write32(dev, SSB_IPSFLAG, - ssb_read32(dev, SSB_IPSFLAG) | - ipsflag_irq_mask[irq]); - } -} - -static void set_irq(struct ssb_device *dev, unsigned int irq) -{ - unsigned int oldirq = ssb_mips_irq(dev); - struct ssb_bus *bus = dev->bus; - struct ssb_device *mdev = bus->mipscore.dev; - u32 irqflag = ssb_irqflag(dev); - - dev->irq = irq + 2; - - ssb_dprintk(KERN_INFO PFX - "set_irq: core 0x%04x, irq %d => %d\n", - dev->id.coreid, oldirq, irq); - /* clear the old irq */ - if (oldirq == 0) - ssb_write32(mdev, SSB_INTVEC, (~(1 << irqflag) & ssb_read32(mdev, SSB_INTVEC))); - else - clear_irq(bus, oldirq); - - /* assign the new one */ - if (irq == 0) { - ssb_write32(mdev, SSB_INTVEC, ((1 << irqflag) | ssb_read32(mdev, SSB_INTVEC))); - } else { - irqflag <<= ipsflag_irq_shift[irq]; - irqflag |= (ssb_read32(mdev, SSB_IPSFLAG) & ~ipsflag_irq_mask[irq]); - ssb_write32(mdev, SSB_IPSFLAG, irqflag); - } -} - -static void ssb_mips_serial_init(struct ssb_mipscore *mcore) -{ - struct ssb_bus *bus = mcore->dev->bus; - - if (bus->extif.dev) - mcore->nr_serial_ports = ssb_extif_serial_init(&bus->extif, mcore->serial_ports); - else if (bus->chipco.dev) - mcore->nr_serial_ports = ssb_chipco_serial_init(&bus->chipco, mcore->serial_ports); - else - mcore->nr_serial_ports = 0; -} - -static void ssb_mips_flash_detect(struct ssb_mipscore *mcore) -{ - struct ssb_bus *bus = mcore->dev->bus; - - mcore->flash_buswidth = 2; - if (bus->chipco.dev) { - mcore->flash_window = 0x1c000000; - mcore->flash_window_size = 0x02000000; - if ((ssb_read32(bus->chipco.dev, SSB_CHIPCO_FLASH_CFG) - & SSB_CHIPCO_CFG_DS16) == 0) - mcore->flash_buswidth = 1; - } else { - mcore->flash_window = 0x1fc00000; - mcore->flash_window_size = 0x00400000; - } -} - -u32 ssb_cpu_clock(struct ssb_mipscore *mcore) -{ - struct ssb_bus *bus = mcore->dev->bus; - u32 pll_type, n, m, rate = 0; - - if (bus->extif.dev) { - ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m); - } else if (bus->chipco.dev) { - ssb_chipco_get_clockcpu(&bus->chipco, &pll_type, &n, &m); - } else - return 0; - - if ((pll_type == SSB_PLLTYPE_5) || (bus->chip_id == 0x5365)) { - rate = 200000000; - } else { - rate = ssb_calc_clock_rate(pll_type, n, m); - } - - if (pll_type == SSB_PLLTYPE_6) { - rate *= 2; - } - - return rate; -} - -void ssb_mipscore_init(struct ssb_mipscore *mcore) -{ - struct ssb_bus *bus; - struct ssb_device *dev; - unsigned long hz, ns; - unsigned int irq, i; - - if (!mcore->dev) - return; /* We don't have a MIPS core */ - - ssb_dprintk(KERN_INFO PFX "Initializing MIPS core...\n"); - - bus = mcore->dev->bus; - hz = ssb_clockspeed(bus); - if (!hz) - hz = 100000000; - ns = 1000000000 / hz; - - if (bus->extif.dev) - ssb_extif_timing_init(&bus->extif, ns); - else if (bus->chipco.dev) - ssb_chipco_timing_init(&bus->chipco, ns); - - /* Assign IRQs to all cores on the bus, start with irq line 2, because serial usually takes 1 */ - for (irq = 2, i = 0; i < bus->nr_devices; i++) { - dev = &(bus->devices[i]); - dev->irq = ssb_mips_irq(dev) + 2; - switch (dev->id.coreid) { - case SSB_DEV_USB11_HOST: - /* shouldn't need a separate irq line for non-4710, most of them have a proper - * external usb controller on the pci */ - if ((bus->chip_id == 0x4710) && (irq <= 4)) { - set_irq(dev, irq++); - break; - } - /* fallthrough */ - case SSB_DEV_PCI: - case SSB_DEV_ETHERNET: - case SSB_DEV_80211: - case SSB_DEV_USB20_HOST: - /* These devices get their own IRQ line if available, the rest goes on IRQ0 */ - if (irq <= 4) { - set_irq(dev, irq++); - break; - } - } - } - - ssb_mips_serial_init(mcore); - ssb_mips_flash_detect(mcore); -} diff --git a/target/linux/generic-2.6/files/drivers/ssb/driver_pcicore.c b/target/linux/generic-2.6/files/drivers/ssb/driver_pcicore.c deleted file mode 100644 index 2faaa906d5..0000000000 --- a/target/linux/generic-2.6/files/drivers/ssb/driver_pcicore.c +++ /dev/null @@ -1,576 +0,0 @@ -/* - * Sonics Silicon Backplane - * Broadcom PCI-core driver - * - * Copyright 2005, Broadcom Corporation - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de> - * - * Licensed under the GNU/GPL. See COPYING for details. - */ - -#include <linux/ssb/ssb.h> -#include <linux/pci.h> -#include <linux/delay.h> - -#include "ssb_private.h" - - -static inline -u32 pcicore_read32(struct ssb_pcicore *pc, u16 offset) -{ - return ssb_read32(pc->dev, offset); -} - -static inline -void pcicore_write32(struct ssb_pcicore *pc, u16 offset, u32 value) -{ - ssb_write32(pc->dev, offset, value); -} - -/************************************************** - * Code for hostmode operation. - **************************************************/ - -#ifdef CONFIG_SSB_PCICORE_HOSTMODE - -#include <asm/paccess.h> -/* Probe a 32bit value on the bus and catch bus exceptions. - * Returns nonzero on a bus exception. - * This is MIPS specific */ -#define mips_busprobe32(val, addr) get_dbe((val), ((u32 *)(addr))) - -/* Assume one-hot slot wiring */ -#define SSB_PCI_SLOT_MAX 16 - -/* Global lock is OK, as we won't have more than one extpci anyway. */ -static DEFINE_SPINLOCK(cfgspace_lock); -/* Core to access the external PCI config space. Can only have one. */ -static struct ssb_pcicore *extpci_core; - -static u32 ssb_pcicore_pcibus_iobase = 0x100; -static u32 ssb_pcicore_pcibus_membase = SSB_PCI_DMA; - -int pcibios_plat_dev_init(struct pci_dev *d) -{ - struct resource *res; - int pos, size; - u32 *base; - - ssb_printk(KERN_INFO "PCI: Fixing up device %s\n", - pci_name(d)); - - /* Fix up resource bases */ - for (pos = 0; pos < 6; pos++) { - res = &d->resource[pos]; - if (res->flags & IORESOURCE_IO) - base = &ssb_pcicore_pcibus_iobase; - else - base = &ssb_pcicore_pcibus_membase; - if (res->end) { - size = res->end - res->start + 1; - if (*base & (size - 1)) - *base = (*base + size) & ~(size - 1); - res->start = *base; - res->end = res->start + size - 1; - *base += size; - pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start); - } - /* Fix up PCI bridge BAR0 only */ - if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0) - break; - } - /* Fix up interrupt lines */ - d->irq = ssb_mips_irq(extpci_core->dev) + 2; - pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq); - - return 0; -} - -static void __init ssb_fixup_pcibridge(struct pci_dev *dev) -{ - if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0) - return; - - ssb_printk(KERN_INFO "PCI: fixing up bridge\n"); - - /* Enable PCI bridge bus mastering and memory space */ - pci_set_master(dev); - pcibios_enable_device(dev, ~0); - - /* Enable PCI bridge BAR1 prefetch and burst */ - pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3); - - /* Make sure our latency is high enough to handle the devices behind us */ - pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xa8); -} -DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_fixup_pcibridge); - -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - return ssb_mips_irq(extpci_core->dev) + 2; -} - -static u32 get_cfgspace_addr(struct ssb_pcicore *pc, - unsigned int bus, unsigned int dev, - unsigned int func, unsigned int off) -{ - u32 addr = 0; - u32 tmp; - - if (unlikely(pc->cardbusmode && dev > 1)) - goto out; - if (bus == 0) { - /* Type 0 transaction */ - if (unlikely(dev >= SSB_PCI_SLOT_MAX)) - goto out; - /* Slide the window */ - tmp = SSB_PCICORE_SBTOPCI_CFG0; - tmp |= ((1 << (dev + 16)) & SSB_PCICORE_SBTOPCI1_MASK); - pcicore_write32(pc, SSB_PCICORE_SBTOPCI1, tmp); - /* Calculate the address */ - addr = SSB_PCI_CFG; - addr |= ((1 << (dev + 16)) & ~SSB_PCICORE_SBTOPCI1_MASK); - addr |= (func << 8); - addr |= (off & ~3); - } else { - /* Type 1 transaction */ - pcicore_write32(pc, SSB_PCICORE_SBTOPCI1, - SSB_PCICORE_SBTOPCI_CFG1); - /* Calculate the address */ - addr = SSB_PCI_CFG; - addr |= (bus << 16); - addr |= (dev << 11); - addr |= (func << 8); - addr |= (off & ~3); - } -out: - return addr; -} - -static int ssb_extpci_read_config(struct ssb_pcicore *pc, - unsigned int bus, unsigned int dev, - unsigned int func, unsigned int off, - void *buf, int len) -{ - int err = -EINVAL; - u32 addr, val; - void __iomem *mmio; - - SSB_WARN_ON(!pc->hostmode); - if (unlikely(len != 1 && len != 2 && len != 4)) - goto out; - addr = get_cfgspace_addr(pc, bus, dev, func, off); - if (unlikely(!addr)) - goto out; - err = -ENOMEM; - mmio = ioremap_nocache(addr, len); - if (!mmio) - goto out; - - if (mips_busprobe32(val, mmio)) { - val = 0xffffffff; - goto unmap; - } - - val = readl(mmio); - val >>= (8 * (off & 3)); - - switch (len) { - case 1: - *((u8 *)buf) = (u8)val; - break; - case 2: - *((u16 *)buf) = (u16)val; - break; - case 4: - *((u32 *)buf) = (u32)val; - break; - } - err = 0; -unmap: - iounmap(mmio); -out: - return err; -} - -static int ssb_extpci_write_config(struct ssb_pcicore *pc, - unsigned int bus, unsigned int dev, - unsigned int func, unsigned int off, - const void *buf, int len) -{ - int err = -EINVAL; - u32 addr, val = 0; - void __iomem *mmio; - - SSB_WARN_ON(!pc->hostmode); - if (unlikely(len != 1 && len != 2 && len != 4)) - goto out; - addr = get_cfgspace_addr(pc, bus, dev, func, off); - if (unlikely(!addr)) - goto out; - err = -ENOMEM; - mmio = ioremap_nocache(addr, len); - if (!mmio) - goto out; - - if (mips_busprobe32(val, mmio)) { - val = 0xffffffff; - goto unmap; - } - - switch (len) { - case 1: - val = readl(mmio); - val &= ~(0xFF << (8 * (off & 3))); - val |= *((const u8 *)buf) << (8 * (off & 3)); - break; - case 2: - val = readl(mmio); - val &= ~(0xFFFF << (8 * (off & 3))); - val |= *((const u16 *)buf) << (8 * (off & 3)); - break; - case 4: - val = *((const u32 *)buf); - break; - } - writel(val, mmio); - - err = 0; -unmap: - iounmap(mmio); -out: - return err; -} - -static int ssb_pcicore_read_config(struct pci_bus *bus, unsigned int devfn, - int reg, int size, u32 *val) -{ - unsigned long flags; - int err; - - spin_lock_irqsave(&cfgspace_lock, flags); - err = ssb_extpci_read_config(extpci_core, bus->number, PCI_SLOT(devfn), - PCI_FUNC(devfn), reg, val, size); - spin_unlock_irqrestore(&cfgspace_lock, flags); - - return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL; -} - -static int ssb_pcicore_write_config(struct pci_bus *bus, unsigned int devfn, - int reg, int size, u32 val) -{ - unsigned long flags; - int err; - - spin_lock_irqsave(&cfgspace_lock, flags); - err = ssb_extpci_write_config(extpci_core, bus->number, PCI_SLOT(devfn), - PCI_FUNC(devfn), reg, &val, size); - spin_unlock_irqrestore(&cfgspace_lock, flags); - - return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL; -} - -static struct pci_ops ssb_pcicore_pciops = { - .read = ssb_pcicore_read_config, - .write = ssb_pcicore_write_config, -}; - -static struct resource ssb_pcicore_mem_resource = { - .name = "SSB PCIcore external memory", - .start = SSB_PCI_DMA, - .end = SSB_PCI_DMA + SSB_PCI_DMA_SZ - 1, - .flags = IORESOURCE_MEM, -}; - -static struct resource ssb_pcicore_io_resource = { - .name = "SSB PCIcore external I/O", - .start = 0x100, - .end = 0x7FF, - .flags = IORESOURCE_IO, -}; - -static struct pci_controller ssb_pcicore_controller = { - .pci_ops = &ssb_pcicore_pciops, - .io_resource = &ssb_pcicore_io_resource, - .mem_resource = &ssb_pcicore_mem_resource, - .mem_offset = 0x24000000, -}; - -static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc) -{ - u32 val; - - if (WARN_ON(extpci_core)) - return; - extpci_core = pc; - - ssb_dprintk(KERN_INFO PFX "PCIcore in host mode found\n"); - /* Reset devices on the external PCI bus */ - val = SSB_PCICORE_CTL_RST_OE; - val |= SSB_PCICORE_CTL_CLK_OE; - pcicore_write32(pc, SSB_PCICORE_CTL, val); - val |= SSB_PCICORE_CTL_CLK; /* Clock on */ - pcicore_write32(pc, SSB_PCICORE_CTL, val); - udelay(150); /* Assertion time demanded by the PCI standard */ - val |= SSB_PCICORE_CTL_RST; /* Deassert RST# */ - pcicore_write32(pc, SSB_PCICORE_CTL, val); - val = SSB_PCICORE_ARBCTL_INTERN; - pcicore_write32(pc, SSB_PCICORE_ARBCTL, val); - udelay(1); /* Assertion time demanded by the PCI standard */ - - /*TODO cardbus mode */ - - /* 64MB I/O window */ - pcicore_write32(pc, SSB_PCICORE_SBTOPCI0, - SSB_PCICORE_SBTOPCI_IO); - /* 64MB config space */ - pcicore_write32(pc, SSB_PCICORE_SBTOPCI1, - SSB_PCICORE_SBTOPCI_CFG0); - /* 1GB memory window */ - pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, - SSB_PCICORE_SBTOPCI_MEM | SSB_PCI_DMA); - - /* Enable PCI bridge BAR0 prefetch and burst */ - val = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - ssb_extpci_write_config(pc, 0, 0, 0, PCI_COMMAND, &val, 2); - /* Clear error conditions */ - val = 0; - ssb_extpci_write_config(pc, 0, 0, 0, PCI_STATUS, &val, 2); - - /* Enable PCI interrupts */ - pcicore_write32(pc, SSB_PCICORE_IMASK, - SSB_PCICORE_IMASK_INTA); - - /* Ok, ready to run, register it to the system. - * The following needs change, if we want to port hostmode - * to non-MIPS platform. */ - set_io_port_base((unsigned long)ioremap_nocache(SSB_PCI_MEM, 0x04000000)); - /* Give some time to the PCI controller to configure itself with the new - * values. Not waiting at this point causes crashes of the machine. */ - mdelay(10); - register_pci_controller(&ssb_pcicore_controller); -} - -static int pcicore_is_in_hostmode(struct ssb_pcicore *pc) -{ - struct ssb_bus *bus = pc->dev->bus; - u16 chipid_top; - u32 tmp; - - chipid_top = (bus->chip_id & 0xFF00); - if (chipid_top != 0x4700 && - chipid_top != 0x5300) - return 0; - - if (bus->sprom.r1.boardflags_lo & SSB_PCICORE_BFL_NOPCI) - return 0; - - /* The 200-pin BCM4712 package does not bond out PCI. Even when - * PCI is bonded out, some boards may leave the pins floating. */ - if (bus->chip_id == 0x4712) { - if (bus->chip_package == SSB_CHIPPACK_BCM4712S) - return 0; - if (bus->chip_package == SSB_CHIPPACK_BCM4712M) - return 0; - } - if (bus->chip_id == 0x5350) - return 0; - - return !mips_busprobe32(tmp, (bus->mmio + (pc->dev->core_index * SSB_CORE_SIZE))); -} -#endif /* CONFIG_SSB_PCICORE_HOSTMODE */ - - -/************************************************** - * Generic and Clientmode operation code. - **************************************************/ - -static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc) -{ - /* Disable PCI interrupts. */ - ssb_write32(pc->dev, SSB_INTVEC, 0); -} - -void ssb_pcicore_init(struct ssb_pcicore *pc) -{ - struct ssb_device *dev = pc->dev; - struct ssb_bus *bus; - - if (!dev) - return; - bus = dev->bus; - if (!ssb_device_is_enabled(dev)) - ssb_device_enable(dev, 0); - -#ifdef CONFIG_SSB_PCICORE_HOSTMODE - pc->hostmode = pcicore_is_in_hostmode(pc); - if (pc->hostmode) - ssb_pcicore_init_hostmode(pc); -#endif /* CONFIG_SSB_PCICORE_HOSTMODE */ - if (!pc->hostmode) - ssb_pcicore_init_clientmode(pc); -} - -static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address) -{ - pcicore_write32(pc, 0x130, address); - return pcicore_read32(pc, 0x134); -} - -static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data) -{ - pcicore_write32(pc, 0x130, address); - pcicore_write32(pc, 0x134, data); -} - -static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device, - u8 address, u16 data) -{ - const u16 mdio_control = 0x128; - const u16 mdio_data = 0x12C; - u32 v; - int i; - - v = 0x80; /* Enable Preamble Sequence */ - v |= 0x2; /* MDIO Clock Divisor */ - pcicore_write32(pc, mdio_control, v); - - v = (1 << 30); /* Start of Transaction */ - v |= (1 << 28); /* Write Transaction */ - v |= (1 << 17); /* Turnaround */ - v |= (u32)device << 22; - v |= (u32)address << 18; - v |= data; - pcicore_write32(pc, mdio_data, v); - /* Wait for the device to complete the transaction */ - udelay(10); - for (i = 0; i < 10; i++) { - v = pcicore_read32(pc, mdio_control); - if (v & 0x100 /* Trans complete */) - break; - msleep(1); - } - pcicore_write32(pc, mdio_control, 0); -} - -static void ssb_broadcast_value(struct ssb_device *dev, - u32 address, u32 data) -{ - /* This is used for both, PCI and ChipCommon core, so be careful. */ - BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR); - BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA); - - ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address); - ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */ - ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data); - ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */ -} - -static void ssb_commit_settings(struct ssb_bus *bus) -{ - struct ssb_device *dev; - - dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev; - if (WARN_ON(!dev)) - return; - /* This forces an update of the cached registers. */ - ssb_broadcast_value(dev, 0xFD8, 0); -} - -int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc, - struct ssb_device *dev) -{ - struct ssb_device *pdev = pc->dev; - struct ssb_bus *bus; - int err = 0; - u32 tmp; - - might_sleep(); - - if (!pdev) - goto out; - bus = pdev->bus; - - /* Enable interrupts for this device. */ - if (bus->host_pci && - ((pdev->id.revision >= 6) || (pdev->id.coreid == SSB_DEV_PCIE))) { - u32 coremask; - - /* Calculate the "coremask" for the device. */ - coremask = (1 << dev->core_index); - - err = pci_read_config_dword(bus->host_pci, SSB_PCI_IRQMASK, &tmp); - if (err) - goto out; - tmp |= coremask << 8; - err = pci_write_config_dword(bus->host_pci, SSB_PCI_IRQMASK, tmp); - if (err) - goto out; - } else { - u32 intvec; - - intvec = ssb_read32(pdev, SSB_INTVEC); - if ((bus->chip_id & 0xFF00) == 0x4400) { - /* Workaround: On the BCM44XX the BPFLAG routing - * bit is wrong. Use a hardcoded constant. */ - intvec |= 0x00000002; - } else { - tmp = ssb_read32(dev, SSB_TPSFLAG); - tmp &= SSB_TPSFLAG_BPFLAG; - intvec |= tmp; - } - ssb_write32(pdev, SSB_INTVEC, intvec); - } - - /* Setup PCIcore operation. */ - if (pc->setup_done) - goto out; - if (pdev->id.coreid == SSB_DEV_PCI) { - tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2); - tmp |= SSB_PCICORE_SBTOPCI_PREF; - tmp |= SSB_PCICORE_SBTOPCI_BURST; - pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp); - - if (pdev->id.revision < 5) { - tmp = ssb_read32(pdev, SSB_IMCFGLO); - tmp &= ~SSB_IMCFGLO_SERTO; - tmp |= 2; - tmp &= ~SSB_IMCFGLO_REQTO; - tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT; - ssb_write32(pdev, SSB_IMCFGLO, tmp); - ssb_commit_settings(bus); - } else if (pdev->id.revision >= 11) { - tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2); - tmp |= SSB_PCICORE_SBTOPCI_MRM; - pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp); - } - } else { - WARN_ON(pdev->id.coreid != SSB_DEV_PCIE); - //TODO: Better make defines for all these magic PCIE values. - if ((pdev->id.revision == 0) || (pdev->id.revision == 1)) { - /* TLP Workaround register. */ - tmp = ssb_pcie_read(pc, 0x4); - tmp |= 0x8; - ssb_pcie_write(pc, 0x4, tmp); - } - if (pdev->id.revision == 0) { - const u8 serdes_rx_device = 0x1F; - - ssb_pcie_mdio_write(pc, serdes_rx_device, - 2 /* Timer */, 0x8128); - ssb_pcie_mdio_write(pc, serdes_rx_device, - 6 /* CDR */, 0x0100); - ssb_pcie_mdio_write(pc, serdes_rx_device, - 7 /* CDR BW */, 0x1466); - } else if (pdev->id.revision == 1) { - /* DLLP Link Control register. */ - tmp = ssb_pcie_read(pc, 0x100); - tmp |= 0x40; - ssb_pcie_write(pc, 0x100, tmp); - } - } - pc->setup_done = 1; -out: - return err; -} -EXPORT_SYMBOL(ssb_pcicore_dev_irqvecs_enable); diff --git a/target/linux/generic-2.6/files/drivers/ssb/main.c b/target/linux/generic-2.6/files/drivers/ssb/main.c deleted file mode 100644 index 9028ed5715..0000000000 --- a/target/linux/generic-2.6/files/drivers/ssb/main.c +++ /dev/null @@ -1,1169 +0,0 @@ -/* - * Sonics Silicon Backplane - * Subsystem core - * - * Copyright 2005, Broadcom Corporation - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de> - * - * Licensed under the GNU/GPL. See COPYING for details. - */ - -#include "ssb_private.h" - -#include <linux/delay.h> -#include <linux/io.h> -#include <linux/ssb/ssb.h> -#include <linux/ssb/ssb_regs.h> -#include <linux/dma-mapping.h> -#include <linux/pci.h> - -#include <pcmcia/cs_types.h> -#include <pcmcia/cs.h> -#include <pcmcia/cistpl.h> -#include <pcmcia/ds.h> - - -MODULE_DESCRIPTION("Sonics Silicon Backplane driver"); -MODULE_LICENSE("GPL"); - - -/* Temporary list of yet-to-be-attached buses */ -static LIST_HEAD(attach_queue); -/* List if running buses */ -static LIST_HEAD(buses); -/* Software ID counter */ -static unsigned int next_busnumber; -/* buses_mutes locks the two buslists and the next_busnumber. - * Don't lock this directly, but use ssb_buses_[un]lock() below. */ -static DEFINE_MUTEX(buses_mutex); - -/* There are differences in the codeflow, if the bus is - * initialized from early boot, as various needed services - * are not available early. This is a mechanism to delay - * these initializations to after early boot has finished. - * It's also used to avoid mutex locking, as that's not - * available and needed early. */ -static bool ssb_is_early_boot = 1; - -static void ssb_buses_lock(void); -static void ssb_buses_unlock(void); - - -#ifdef CONFIG_SSB_PCIHOST -struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev) -{ - struct ssb_bus *bus; - - ssb_buses_lock(); - list_for_each_entry(bus, &buses, list) { - if (bus->bustype == SSB_BUSTYPE_PCI && - bus->host_pci == pdev) - goto found; - } - bus = NULL; -found: - ssb_buses_unlock(); - - return bus; -} -#endif /* CONFIG_SSB_PCIHOST */ - -static struct ssb_device *ssb_device_get(struct ssb_device *dev) -{ - if (dev) - get_device(dev->dev); - return dev; -} - -static void ssb_device_put(struct ssb_device *dev) -{ - if (dev) - put_device(dev->dev); -} - -static int ssb_bus_resume(struct ssb_bus *bus) -{ - int err; - - ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1); - err = ssb_pcmcia_init(bus); - if (err) { - /* No need to disable XTAL, as we don't have one on PCMCIA. */ - return err; - } - ssb_chipco_resume(&bus->chipco); - - return 0; -} - -static int ssb_device_resume(struct device *dev) -{ - struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); - struct ssb_driver *ssb_drv; - struct ssb_bus *bus; - int err = 0; - - bus = ssb_dev->bus; - if (bus->suspend_cnt == bus->nr_devices) { - err = ssb_bus_resume(bus); - if (err) - return err; - } - bus->suspend_cnt--; - if (dev->driver) { - ssb_drv = drv_to_ssb_drv(dev->driver); - if (ssb_drv && ssb_drv->resume) - err = ssb_drv->resume(ssb_dev); - if (err) - goto out; - } -out: - return err; -} - -static void ssb_bus_suspend(struct ssb_bus *bus, pm_message_t state) -{ - ssb_chipco_suspend(&bus->chipco, state); - ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0); - - /* Reset HW state information in memory, so that HW is - * completely reinitialized on resume. */ - bus->mapped_device = NULL; -#ifdef CONFIG_SSB_DRIVER_PCICORE - bus->pcicore.setup_done = 0; -#endif -#ifdef CONFIG_SSB_DEBUG - bus->powered_up = 0; -#endif -} - -static int ssb_device_suspend(struct device *dev, pm_message_t state) -{ - struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); - struct ssb_driver *ssb_drv; - struct ssb_bus *bus; - int err = 0; - - if (dev->driver) { - ssb_drv = drv_to_ssb_drv(dev->driver); - if (ssb_drv && ssb_drv->suspend) - err = ssb_drv->suspend(ssb_dev, state); - if (err) - goto out; - } - - bus = ssb_dev->bus; - bus->suspend_cnt++; - if (bus->suspend_cnt == bus->nr_devices) { - /* All devices suspended. Shutdown the bus. */ - ssb_bus_suspend(bus, state); - } - -out: - return err; -} - -#ifdef CONFIG_SSB_PCIHOST -int ssb_devices_freeze(struct ssb_bus *bus) -{ - struct ssb_device *dev; - struct ssb_driver *drv; - int err = 0; - int i; - pm_message_t state = PMSG_FREEZE; - - /* First check that we are capable to freeze all devices. */ - for (i = 0; i < bus->nr_devices; i++) { - dev = &(bus->devices[i]); - if (!dev->dev || - !dev->dev->driver || - !device_is_registered(dev->dev)) - continue; - drv = drv_to_ssb_drv(dev->dev->driver); - if (!drv) - continue; - if (!drv->suspend) { - /* Nope, can't suspend this one. */ - return -EOPNOTSUPP; - } - } - /* Now suspend all devices */ - for (i = 0; i < bus->nr_devices; i++) { - dev = &(bus->devices[i]); - if (!dev->dev || - !dev->dev->driver || - !device_is_registered(dev->dev)) - continue; - drv = drv_to_ssb_drv(dev->dev->driver); - if (!drv) - continue; - err = drv->suspend(dev, state); - if (err) { - ssb_printk(KERN_ERR PFX "Failed to freeze device %s\n", - dev->dev->bus_id); - goto err_unwind; - } - } - - return 0; -err_unwind: - for (i--; i >= 0; i--) { - dev = &(bus->devices[i]); - if (!dev->dev || - !dev->dev->driver || - !device_is_registered(dev->dev)) - continue; - drv = drv_to_ssb_drv(dev->dev->driver); - if (!drv) - continue; - if (drv->resume) - drv->resume(dev); - } - return err; -} - -int ssb_devices_thaw(struct ssb_bus *bus) -{ - struct ssb_device *dev; - struct ssb_driver *drv; - int err; - int i; - - for (i = 0; i < bus->nr_devices; i++) { - dev = &(bus->devices[i]); - if (!dev->dev || - !dev->dev->driver || - !device_is_registered(dev->dev)) - continue; - drv = drv_to_ssb_drv(dev->dev->driver); - if (!drv) - continue; - if (SSB_WARN_ON(!drv->resume)) - continue; - err = drv->resume(dev); - if (err) { - ssb_printk(KERN_ERR PFX "Failed to thaw device %s\n", - dev->dev->bus_id); - } - } - - return 0; -} -#endif /* CONFIG_SSB_PCIHOST */ - -static void ssb_device_shutdown(struct device *dev) -{ - struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); - struct ssb_driver *ssb_drv; - - if (!dev->driver) - return; - ssb_drv = drv_to_ssb_drv(dev->driver); - if (ssb_drv && ssb_drv->shutdown) - ssb_drv->shutdown(ssb_dev); -} - -static int ssb_device_remove(struct device *dev) -{ - struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); - struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver); - - if (ssb_drv && ssb_drv->remove) - ssb_drv->remove(ssb_dev); - ssb_device_put(ssb_dev); - - return 0; -} - -static int ssb_device_probe(struct device *dev) -{ - struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); - struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver); - int err = 0; - - ssb_device_get(ssb_dev); - if (ssb_drv && ssb_drv->probe) - err = ssb_drv->probe(ssb_dev, &ssb_dev->id); - if (err) - ssb_device_put(ssb_dev); - - return err; -} - -static int ssb_match_devid(const struct ssb_device_id *tabid, - const struct ssb_device_id *devid) -{ - if ((tabid->vendor != devid->vendor) && - tabid->vendor != SSB_ANY_VENDOR) - return 0; - if ((tabid->coreid != devid->coreid) && - tabid->coreid != SSB_ANY_ID) - return 0; - if ((tabid->revision != devid->revision) && - tabid->revision != SSB_ANY_REV) - return 0; - return 1; -} - -static int ssb_bus_match(struct device *dev, struct device_driver *drv) -{ - struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); - struct ssb_driver *ssb_drv = drv_to_ssb_drv(drv); - const struct ssb_device_id *id; - - for (id = ssb_drv->id_table; - id->vendor || id->coreid || id->revision; - id++) { - if (ssb_match_devid(id, &ssb_dev->id)) - return 1; /* found */ - } - - return 0; -} - -static int ssb_device_uevent(struct device *dev, struct kobj_uevent_env *env) -{ - struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); - - if (!dev) - return -ENODEV; - - return add_uevent_var(env, - "MODALIAS=ssb:v%04Xid%04Xrev%02X", - ssb_dev->id.vendor, ssb_dev->id.coreid, - ssb_dev->id.revision); -} - -static struct bus_type ssb_bustype = { - .name = "ssb", - .match = ssb_bus_match, - .probe = ssb_device_probe, - .remove = ssb_device_remove, - .shutdown = ssb_device_shutdown, - .suspend = ssb_device_suspend, - .resume = ssb_device_resume, - .uevent = ssb_device_uevent, -}; - -static void ssb_buses_lock(void) -{ - /* See the comment at the ssb_is_early_boot definition */ - if (!ssb_is_early_boot) - mutex_lock(&buses_mutex); -} - -static void ssb_buses_unlock(void) -{ - /* See the comment at the ssb_is_early_boot definition */ - if (!ssb_is_early_boot) - mutex_unlock(&buses_mutex); -} - -static void ssb_devices_unregister(struct ssb_bus *bus) -{ - struct ssb_device *sdev; - int i; - - for (i = bus->nr_devices - 1; i >= 0; i--) { - sdev = &(bus->devices[i]); - if (sdev->dev) - device_unregister(sdev->dev); - } -} - -void ssb_bus_unregister(struct ssb_bus *bus) -{ - ssb_buses_lock(); - ssb_devices_unregister(bus); - list_del(&bus->list); - ssb_buses_unlock(); - - /* ssb_pcmcia_exit(bus); */ - ssb_pci_exit(bus); - ssb_iounmap(bus); -} -EXPORT_SYMBOL(ssb_bus_unregister); - -static void ssb_release_dev(struct device *dev) -{ - struct __ssb_dev_wrapper *devwrap; - - devwrap = container_of(dev, struct __ssb_dev_wrapper, dev); - kfree(devwrap); -} - -static int ssb_devices_register(struct ssb_bus *bus) -{ - struct ssb_device *sdev; - struct device *dev; - struct __ssb_dev_wrapper *devwrap; - int i, err = 0; - int dev_idx = 0; - - for (i = 0; i < bus->nr_devices; i++) { - sdev = &(bus->devices[i]); - - /* We don't register SSB-system devices to the kernel, - * as the drivers for them are built into SSB. */ - switch (sdev->id.coreid) { - case SSB_DEV_CHIPCOMMON: - case SSB_DEV_PCI: - case SSB_DEV_PCIE: - case SSB_DEV_PCMCIA: - case SSB_DEV_MIPS: - case SSB_DEV_MIPS_3302: - case SSB_DEV_EXTIF: - continue; - } - - devwrap = kzalloc(sizeof(*devwrap), GFP_KERNEL); - if (!devwrap) { - ssb_printk(KERN_ERR PFX - "Could not allocate device\n"); - err = -ENOMEM; - goto error; - } - dev = &devwrap->dev; - devwrap->sdev = sdev; - - dev->release = ssb_release_dev; - dev->bus = &ssb_bustype; - snprintf(dev->bus_id, sizeof(dev->bus_id), - "ssb%u:%d", bus->busnumber, dev_idx); - - switch (bus->bustype) { - case SSB_BUSTYPE_PCI: -#ifdef CONFIG_SSB_PCIHOST - sdev->irq = bus->host_pci->irq; - dev->parent = &bus->host_pci->dev; -#endif - break; - case SSB_BUSTYPE_PCMCIA: -#ifdef CONFIG_SSB_PCMCIAHOST - sdev->irq = bus->host_pcmcia->irq.AssignedIRQ; - dev->parent = &bus->host_pcmcia->dev; -#endif - break; - case SSB_BUSTYPE_SSB: - break; - } - - sdev->dev = dev; - err = device_register(dev); - if (err) { - ssb_printk(KERN_ERR PFX - "Could not register %s\n", - dev->bus_id); - /* Set dev to NULL to not unregister - * dev on error unwinding. */ - sdev->dev = NULL; - kfree(devwrap); - goto error; - } - dev_idx++; - } - - return 0; -error: - /* Unwind the already registered devices. */ - ssb_devices_unregister(bus); - return err; -} - -/* Needs ssb_buses_lock() */ -static int ssb_attach_queued_buses(void) -{ - struct ssb_bus *bus, *n; - int err = 0; - int drop_them_all = 0; - - list_for_each_entry_safe(bus, n, &attach_queue, list) { - if (drop_them_all) { - list_del(&bus->list); - continue; - } - /* Can't init the PCIcore in ssb_bus_register(), as that - * is too early in boot for embedded systems - * (no udelay() available). So do it here in attach stage. - */ - err = ssb_bus_powerup(bus, 0); - if (err) - goto error; - ssb_pcicore_init(&bus->pcicore); - ssb_bus_may_powerdown(bus); - - err = ssb_devices_register(bus); -error: - if (err) { - drop_them_all = 1; - list_del(&bus->list); - continue; - } - list_move_tail(&bus->list, &buses); - } - - return err; -} - -static u16 ssb_ssb_read16(struct ssb_device *dev, u16 offset) -{ - struct ssb_bus *bus = dev->bus; - - offset += dev->core_index * SSB_CORE_SIZE; - return readw(bus->mmio + offset); -} - -static u32 ssb_ssb_read32(struct ssb_device *dev, u16 offset) -{ - struct ssb_bus *bus = dev->bus; - - offset += dev->core_index * SSB_CORE_SIZE; - return readl(bus->mmio + offset); -} - -static void ssb_ssb_write16(struct ssb_device *dev, u16 offset, u16 value) -{ - struct ssb_bus *bus = dev->bus; - - offset += dev->core_index * SSB_CORE_SIZE; - writew(value, bus->mmio + offset); -} - -static void ssb_ssb_write32(struct ssb_device *dev, u16 offset, u32 value) -{ - struct ssb_bus *bus = dev->bus; - - offset += dev->core_index * SSB_CORE_SIZE; - writel(value, bus->mmio + offset); -} - -/* Ops for the plain SSB bus without a host-device (no PCI or PCMCIA). */ -static const struct ssb_bus_ops ssb_ssb_ops = { - .read16 = ssb_ssb_read16, - .read32 = ssb_ssb_read32, - .write16 = ssb_ssb_write16, - .write32 = ssb_ssb_write32, -}; - -static int ssb_fetch_invariants(struct ssb_bus *bus, - ssb_invariants_func_t get_invariants) -{ - struct ssb_init_invariants iv; - int err; - - memset(&iv, 0, sizeof(iv)); - err = get_invariants(bus, &iv); - if (err) - goto out; - memcpy(&bus->boardinfo, &iv.boardinfo, sizeof(iv.boardinfo)); - memcpy(&bus->sprom, &iv.sprom, sizeof(iv.sprom)); -out: - return err; -} - -static int ssb_bus_register(struct ssb_bus *bus, - ssb_invariants_func_t get_invariants, - unsigned long baseaddr) -{ - int err; - - spin_lock_init(&bus->bar_lock); - INIT_LIST_HEAD(&bus->list); - - /* Powerup the bus */ - err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1); - if (err) - goto out; - ssb_buses_lock(); - bus->busnumber = next_busnumber; - /* Scan for devices (cores) */ - err = ssb_bus_scan(bus, baseaddr); - if (err) - goto err_disable_xtal; - - /* Init PCI-host device (if any) */ - err = ssb_pci_init(bus); - if (err) - goto err_unmap; - /* Init PCMCIA-host device (if any) */ - err = ssb_pcmcia_init(bus); - if (err) - goto err_pci_exit; - - /* Initialize basic system devices (if available) */ - err = ssb_bus_powerup(bus, 0); - if (err) - goto err_pcmcia_exit; - ssb_chipcommon_init(&bus->chipco); - ssb_mipscore_init(&bus->mipscore); - err = ssb_fetch_invariants(bus, get_invariants); - if (err) { - ssb_bus_may_powerdown(bus); - goto err_pcmcia_exit; - } - ssb_bus_may_powerdown(bus); - - /* Queue it for attach. - * See the comment at the ssb_is_early_boot definition. */ - list_add_tail(&bus->list, &attach_queue); - if (!ssb_is_early_boot) { - /* This is not early boot, so we must attach the bus now */ - err = ssb_attach_queued_buses(); - if (err) - goto err_dequeue; - } - next_busnumber++; - ssb_buses_unlock(); - -out: - return err; - -err_dequeue: - list_del(&bus->list); -err_pcmcia_exit: -/* ssb_pcmcia_exit(bus); */ -err_pci_exit: - ssb_pci_exit(bus); -err_unmap: - ssb_iounmap(bus); -err_disable_xtal: - ssb_buses_unlock(); - ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0); - return err; -} - -#ifdef CONFIG_SSB_PCIHOST -int ssb_bus_pcibus_register(struct ssb_bus *bus, - struct pci_dev *host_pci) -{ - int err; - - bus->bustype = SSB_BUSTYPE_PCI; - bus->host_pci = host_pci; - bus->ops = &ssb_pci_ops; - - err = ssb_bus_register(bus, ssb_pci_get_invariants, 0); - if (!err) { - ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on " - "PCI device %s\n", host_pci->dev.bus_id); - } - - return err; -} -EXPORT_SYMBOL(ssb_bus_pcibus_register); -#endif /* CONFIG_SSB_PCIHOST */ - -#ifdef CONFIG_SSB_PCMCIAHOST -int ssb_bus_pcmciabus_register(struct ssb_bus *bus, - struct pcmcia_device *pcmcia_dev, - unsigned long baseaddr) -{ - int err; - - bus->bustype = SSB_BUSTYPE_PCMCIA; - bus->host_pcmcia = pcmcia_dev; - bus->ops = &ssb_pcmcia_ops; - - err = ssb_bus_register(bus, ssb_pcmcia_get_invariants, baseaddr); - if (!err) { - ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on " - "PCMCIA device %s\n", pcmcia_dev->devname); - } - - return err; -} -EXPORT_SYMBOL(ssb_bus_pcmciabus_register); -#endif /* CONFIG_SSB_PCMCIAHOST */ - -int ssb_bus_ssbbus_register(struct ssb_bus *bus, - unsigned long baseaddr, - ssb_invariants_func_t get_invariants) -{ - int err; - - bus->bustype = SSB_BUSTYPE_SSB; - bus->ops = &ssb_ssb_ops; - - err = ssb_bus_register(bus, get_invariants, baseaddr); - if (!err) { - ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found at " - "address 0x%08lX\n", baseaddr); - } - - return err; -} - -int __ssb_driver_register(struct ssb_driver *drv, struct module *owner) -{ - drv->drv.name = drv->name; - drv->drv.bus = &ssb_bustype; - drv->drv.owner = owner; - - return driver_register(&drv->drv); -} -EXPORT_SYMBOL(__ssb_driver_register); - -void ssb_driver_unregister(struct ssb_driver *drv) -{ - driver_unregister(&drv->drv); -} -EXPORT_SYMBOL(ssb_driver_unregister); - -void ssb_set_devtypedata(struct ssb_device *dev, void *data) -{ - struct ssb_bus *bus = dev->bus; - struct ssb_device *ent; - int i; - - for (i = 0; i < bus->nr_devices; i++) { - ent = &(bus->devices[i]); - if (ent->id.vendor != dev->id.vendor) - continue; - if (ent->id.coreid != dev->id.coreid) - continue; - - ent->devtypedata = data; - } -} -EXPORT_SYMBOL(ssb_set_devtypedata); - -static u32 clkfactor_f6_resolve(u32 v) -{ - /* map the magic values */ - switch (v) { - case SSB_CHIPCO_CLK_F6_2: - return 2; - case SSB_CHIPCO_CLK_F6_3: - return 3; - case SSB_CHIPCO_CLK_F6_4: - return 4; - case SSB_CHIPCO_CLK_F6_5: - return 5; - case SSB_CHIPCO_CLK_F6_6: - return 6; - case SSB_CHIPCO_CLK_F6_7: - return 7; - } - return 0; -} - -/* Calculate the speed the backplane would run at a given set of clockcontrol values */ -u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m) -{ - u32 n1, n2, clock, m1, m2, m3, mc; - - n1 = (n & SSB_CHIPCO_CLK_N1); - n2 = ((n & SSB_CHIPCO_CLK_N2) >> SSB_CHIPCO_CLK_N2_SHIFT); - - switch (plltype) { - case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */ - if (m & SSB_CHIPCO_CLK_T6_MMASK) - return SSB_CHIPCO_CLK_T6_M0; - return SSB_CHIPCO_CLK_T6_M1; - case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */ - case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */ - case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */ - case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */ - n1 = clkfactor_f6_resolve(n1); - n2 += SSB_CHIPCO_CLK_F5_BIAS; - break; - case SSB_PLLTYPE_2: /* 48Mhz, 4 dividers */ - n1 += SSB_CHIPCO_CLK_T2_BIAS; - n2 += SSB_CHIPCO_CLK_T2_BIAS; - SSB_WARN_ON(!((n1 >= 2) && (n1 <= 7))); - SSB_WARN_ON(!((n2 >= 5) && (n2 <= 23))); - break; - case SSB_PLLTYPE_5: /* 25Mhz, 4 dividers */ - return 100000000; - default: - SSB_WARN_ON(1); - } - - switch (plltype) { - case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */ - case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */ - clock = SSB_CHIPCO_CLK_BASE2 * n1 * n2; - break; - default: - clock = SSB_CHIPCO_CLK_BASE1 * n1 * n2; - } - if (!clock) - return 0; - - m1 = (m & SSB_CHIPCO_CLK_M1); - m2 = ((m & SSB_CHIPCO_CLK_M2) >> SSB_CHIPCO_CLK_M2_SHIFT); - m3 = ((m & SSB_CHIPCO_CLK_M3) >> SSB_CHIPCO_CLK_M3_SHIFT); - mc = ((m & SSB_CHIPCO_CLK_MC) >> SSB_CHIPCO_CLK_MC_SHIFT); - - switch (plltype) { - case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */ - case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */ - case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */ - case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */ - m1 = clkfactor_f6_resolve(m1); - if ((plltype == SSB_PLLTYPE_1) || - (plltype == SSB_PLLTYPE_3)) - m2 += SSB_CHIPCO_CLK_F5_BIAS; - else - m2 = clkfactor_f6_resolve(m2); - m3 = clkfactor_f6_resolve(m3); - - switch (mc) { - case SSB_CHIPCO_CLK_MC_BYPASS: - return clock; - case SSB_CHIPCO_CLK_MC_M1: - return (clock / m1); - case SSB_CHIPCO_CLK_MC_M1M2: - return (clock / (m1 * m2)); - case SSB_CHIPCO_CLK_MC_M1M2M3: - return (clock / (m1 * m2 * m3)); - case SSB_CHIPCO_CLK_MC_M1M3: - return (clock / (m1 * m3)); - } - return 0; - case SSB_PLLTYPE_2: - m1 += SSB_CHIPCO_CLK_T2_BIAS; - m2 += SSB_CHIPCO_CLK_T2M2_BIAS; - m3 += SSB_CHIPCO_CLK_T2_BIAS; - SSB_WARN_ON(!((m1 >= 2) && (m1 <= 7))); - SSB_WARN_ON(!((m2 >= 3) && (m2 <= 10))); - SSB_WARN_ON(!((m3 >= 2) && (m3 <= 7))); - - if (!(mc & SSB_CHIPCO_CLK_T2MC_M1BYP)) - clock /= m1; - if (!(mc & SSB_CHIPCO_CLK_T2MC_M2BYP)) - clock /= m2; - if (!(mc & SSB_CHIPCO_CLK_T2MC_M3BYP)) - clock /= m3; - return clock; - default: - SSB_WARN_ON(1); - } - return 0; -} - -/* Get the current speed the backplane is running at */ -u32 ssb_clockspeed(struct ssb_bus *bus) -{ - u32 rate; - u32 plltype; - u32 clkctl_n, clkctl_m; - - if (ssb_extif_available(&bus->extif)) - ssb_extif_get_clockcontrol(&bus->extif, &plltype, - &clkctl_n, &clkctl_m); - else if (bus->chipco.dev) - ssb_chipco_get_clockcontrol(&bus->chipco, &plltype, - &clkctl_n, &clkctl_m); - else - return 0; - - if (bus->chip_id == 0x5365) { - rate = 100000000; - } else { - rate = ssb_calc_clock_rate(plltype, clkctl_n, clkctl_m); - if (plltype == SSB_PLLTYPE_3) /* 25Mhz, 2 dividers */ - rate /= 2; - } - - return rate; -} -EXPORT_SYMBOL(ssb_clockspeed); - -static u32 ssb_tmslow_reject_bitmask(struct ssb_device *dev) -{ - u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV; - - /* The REJECT bit changed position in TMSLOW between - * Backplane revisions. */ - switch (rev) { - case SSB_IDLOW_SSBREV_22: - return SSB_TMSLOW_REJECT_22; - case SSB_IDLOW_SSBREV_23: - return SSB_TMSLOW_REJECT_23; - case SSB_IDLOW_SSBREV_24: /* TODO - find the proper REJECT bits */ - case SSB_IDLOW_SSBREV_25: /* same here */ - case SSB_IDLOW_SSBREV_26: /* same here */ - case SSB_IDLOW_SSBREV_27: /* same here */ - return SSB_TMSLOW_REJECT_23; /* this is a guess */ - default: - printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev); - WARN_ON(1); - } - return (SSB_TMSLOW_REJECT_22 | SSB_TMSLOW_REJECT_23); -} - -int ssb_device_is_enabled(struct ssb_device *dev) -{ - u32 val; - u32 reject; - - reject = ssb_tmslow_reject_bitmask(dev); - val = ssb_read32(dev, SSB_TMSLOW); - val &= SSB_TMSLOW_CLOCK | SSB_TMSLOW_RESET | reject; - - return (val == SSB_TMSLOW_CLOCK); -} -EXPORT_SYMBOL(ssb_device_is_enabled); - -static void ssb_flush_tmslow(struct ssb_device *dev) -{ - /* Make _really_ sure the device has finished the TMSLOW - * register write transaction, as we risk running into - * a machine check exception otherwise. - * Do this by reading the register back to commit the - * PCI write and delay an additional usec for the device - * to react to the change. */ - ssb_read32(dev, SSB_TMSLOW); - udelay(1); -} - -void ssb_device_enable(struct ssb_device *dev, u32 core_specific_flags) -{ - u32 val; - - ssb_device_disable(dev, core_specific_flags); - ssb_write32(dev, SSB_TMSLOW, - SSB_TMSLOW_RESET | SSB_TMSLOW_CLOCK | - SSB_TMSLOW_FGC | core_specific_flags); - ssb_flush_tmslow(dev); - - /* Clear SERR if set. This is a hw bug workaround. */ - if (ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_SERR) - ssb_write32(dev, SSB_TMSHIGH, 0); - - val = ssb_read32(dev, SSB_IMSTATE); - if (val & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO)) { - val &= ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO); - ssb_write32(dev, SSB_IMSTATE, val); - } - - ssb_write32(dev, SSB_TMSLOW, - SSB_TMSLOW_CLOCK | SSB_TMSLOW_FGC | - core_specific_flags); - ssb_flush_tmslow(dev); - - ssb_write32(dev, SSB_TMSLOW, SSB_TMSLOW_CLOCK | - core_specific_flags); - ssb_flush_tmslow(dev); -} -EXPORT_SYMBOL(ssb_device_enable); - -/* Wait for a bit in a register to get set or unset. - * timeout is in units of ten-microseconds */ -static int ssb_wait_bit(struct ssb_device *dev, u16 reg, u32 bitmask, - int timeout, int set) -{ - int i; - u32 val; - - for (i = 0; i < timeout; i++) { - val = ssb_read32(dev, reg); - if (set) { - if (val & bitmask) - return 0; - } else { - if (!(val & bitmask)) - return 0; - } - udelay(10); - } - printk(KERN_ERR PFX "Timeout waiting for bitmask %08X on " - "register %04X to %s.\n", - bitmask, reg, (set ? "set" : "clear")); - - return -ETIMEDOUT; -} - -void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags) -{ - u32 reject; - - if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET) - return; - - reject = ssb_tmslow_reject_bitmask(dev); - ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK); - ssb_wait_bit(dev, SSB_TMSLOW, reject, 1000, 1); - ssb_wait_bit(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0); - ssb_write32(dev, SSB_TMSLOW, - SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK | - reject | SSB_TMSLOW_RESET | - core_specific_flags); - ssb_flush_tmslow(dev); - - ssb_write32(dev, SSB_TMSLOW, - reject | SSB_TMSLOW_RESET | - core_specific_flags); - ssb_flush_tmslow(dev); -} -EXPORT_SYMBOL(ssb_device_disable); - -u32 ssb_dma_translation(struct ssb_device *dev) -{ - switch (dev->bus->bustype) { - case SSB_BUSTYPE_SSB: - return 0; - case SSB_BUSTYPE_PCI: - case SSB_BUSTYPE_PCMCIA: - return SSB_PCI_DMA; - } - return 0; -} -EXPORT_SYMBOL(ssb_dma_translation); - -int ssb_dma_set_mask(struct ssb_device *ssb_dev, u64 mask) -{ - struct device *dev = ssb_dev->dev; - -#ifdef CONFIG_SSB_PCIHOST - if (ssb_dev->bus->bustype == SSB_BUSTYPE_PCI && - !dma_supported(dev, mask)) - return -EIO; -#endif - dev->coherent_dma_mask = mask; - dev->dma_mask = &dev->coherent_dma_mask; - - return 0; -} -EXPORT_SYMBOL(ssb_dma_set_mask); - -int ssb_bus_may_powerdown(struct ssb_bus *bus) -{ - struct ssb_chipcommon *cc; - int err = 0; - - /* On buses where more than one core may be working - * at a time, we must not powerdown stuff if there are - * still cores that may want to run. */ - if (bus->bustype == SSB_BUSTYPE_SSB) - goto out; - - cc = &bus->chipco; - ssb_chipco_set_clockmode(cc, SSB_CLKMODE_SLOW); - err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0); - if (err) - goto error; -out: -#ifdef CONFIG_SSB_DEBUG - bus->powered_up = 0; -#endif - return err; -error: - ssb_printk(KERN_ERR PFX "Bus powerdown failed\n"); - goto out; -} -EXPORT_SYMBOL(ssb_bus_may_powerdown); - -int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl) -{ - struct ssb_chipcommon *cc; - int err; - enum ssb_clkmode mode; - - err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1); - if (err) - goto error; - cc = &bus->chipco; - mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST; - ssb_chipco_set_clockmode(cc, mode); - -#ifdef CONFIG_SSB_DEBUG - bus->powered_up = 1; -#endif - return 0; -error: - ssb_printk(KERN_ERR PFX "Bus powerup failed\n"); - return err; -} -EXPORT_SYMBOL(ssb_bus_powerup); - -u32 ssb_admatch_base(u32 adm) -{ - u32 base = 0; - - switch (adm & SSB_ADM_TYPE) { - case SSB_ADM_TYPE0: - base = (adm & SSB_ADM_BASE0); - break; - case SSB_ADM_TYPE1: - SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */ - base = (adm & SSB_ADM_BASE1); - break; - case SSB_ADM_TYPE2: - SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */ - base = (adm & SSB_ADM_BASE2); - break; - default: - SSB_WARN_ON(1); - } - - return base; -} -EXPORT_SYMBOL(ssb_admatch_base); - -u32 ssb_admatch_size(u32 adm) -{ - u32 size = 0; - - switch (adm & SSB_ADM_TYPE) { - case SSB_ADM_TYPE0: - size = ((adm & SSB_ADM_SZ0) >> SSB_ADM_SZ0_SHIFT); - break; - case SSB_ADM_TYPE1: - SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */ - size = ((adm & SSB_ADM_SZ1) >> SSB_ADM_SZ1_SHIFT); - break; - case SSB_ADM_TYPE2: - SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */ - size = ((adm & SSB_ADM_SZ2) >> SSB_ADM_SZ2_SHIFT); - break; - default: - SSB_WARN_ON(1); - } - size = (1 << (size + 1)); - - return size; -} -EXPORT_SYMBOL(ssb_admatch_size); - -static int __init ssb_modinit(void) -{ - int err; - - /* See the comment at the ssb_is_early_boot definition */ - ssb_is_early_boot = 0; - err = bus_register(&ssb_bustype); - if (err) - return err; - - /* Maybe we already registered some buses at early boot. - * Check for this and attach them - */ - ssb_buses_lock(); - err = ssb_attach_queued_buses(); - ssb_buses_unlock(); - if (err) - bus_unregister(&ssb_bustype); - - err = b43_pci_ssb_bridge_init(); - if (err) { - ssb_printk(KERN_ERR "Broadcom 43xx PCI-SSB-bridge " - "initialization failed"); - /* don't fail SSB init because of this */ - err = 0; - } - - return err; -} -/* ssb must be initialized after PCI but before the ssb drivers. - * That means we must use some initcall between subsys_initcall - * and device_initcall. */ -fs_initcall(ssb_modinit); - -static void __exit ssb_modexit(void) -{ - b43_pci_ssb_bridge_exit(); - bus_unregister(&ssb_bustype); -} -module_exit(ssb_modexit) diff --git a/target/linux/generic-2.6/files/drivers/ssb/pci.c b/target/linux/generic-2.6/files/drivers/ssb/pci.c deleted file mode 100644 index b434df7504..0000000000 --- a/target/linux/generic-2.6/files/drivers/ssb/pci.c +++ /dev/null @@ -1,790 +0,0 @@ -/* - * Sonics Silicon Backplane PCI-Hostbus related functions. - * - * Copyright (C) 2005-2006 Michael Buesch <mb@bu3sch.de> - * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de> - * Copyright (C) 2005 Stefano Brivio <st3@riseup.net> - * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org> - * Copyright (C) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch> - * - * Derived from the Broadcom 4400 device driver. - * Copyright (C) 2002 David S. Miller (davem@redhat.com) - * Fixed by Pekka Pietikainen (pp@ee.oulu.fi) - * Copyright (C) 2006 Broadcom Corporation. - * - * Licensed under the GNU/GPL. See COPYING for details. - */ - -#include <linux/ssb/ssb.h> -#include <linux/ssb/ssb_regs.h> -#include <linux/pci.h> -#include <linux/delay.h> - -#include "ssb_private.h" - - -/* Define the following to 1 to enable a printk on each coreswitch. */ -#define SSB_VERBOSE_PCICORESWITCH_DEBUG 0 - - -/* Lowlevel coreswitching */ -int ssb_pci_switch_coreidx(struct ssb_bus *bus, u8 coreidx) -{ - int err; - int attempts = 0; - u32 cur_core; - - while (1) { - err = pci_write_config_dword(bus->host_pci, SSB_BAR0_WIN, - (coreidx * SSB_CORE_SIZE) - + SSB_ENUM_BASE); - if (err) - goto error; - err = pci_read_config_dword(bus->host_pci, SSB_BAR0_WIN, - &cur_core); - if (err) - goto error; - cur_core = (cur_core - SSB_ENUM_BASE) - / SSB_CORE_SIZE; - if (cur_core == coreidx) - break; - - if (attempts++ > SSB_BAR0_MAX_RETRIES) - goto error; - udelay(10); - } - return 0; -error: - ssb_printk(KERN_ERR PFX "Failed to switch to core %u\n", coreidx); - return -ENODEV; -} - -int ssb_pci_switch_core(struct ssb_bus *bus, - struct ssb_device *dev) -{ - int err; - unsigned long flags; - -#if SSB_VERBOSE_PCICORESWITCH_DEBUG - ssb_printk(KERN_INFO PFX - "Switching to %s core, index %d\n", - ssb_core_name(dev->id.coreid), - dev->core_index); -#endif - - spin_lock_irqsave(&bus->bar_lock, flags); - err = ssb_pci_switch_coreidx(bus, dev->core_index); - if (!err) - bus->mapped_device = dev; - spin_unlock_irqrestore(&bus->bar_lock, flags); - - return err; -} - -/* Enable/disable the on board crystal oscillator and/or PLL. */ -int ssb_pci_xtal(struct ssb_bus *bus, u32 what, int turn_on) -{ - int err; - u32 in, out, outenable; - u16 pci_status; - - if (bus->bustype != SSB_BUSTYPE_PCI) - return 0; - - err = pci_read_config_dword(bus->host_pci, SSB_GPIO_IN, &in); - if (err) - goto err_pci; - err = pci_read_config_dword(bus->host_pci, SSB_GPIO_OUT, &out); - if (err) - goto err_pci; - err = pci_read_config_dword(bus->host_pci, SSB_GPIO_OUT_ENABLE, &outenable); - if (err) - goto err_pci; - - outenable |= what; - - if (turn_on) { - /* Avoid glitching the clock if GPRS is already using it. - * We can't actually read the state of the PLLPD so we infer it - * by the value of XTAL_PU which *is* readable via gpioin. - */ - if (!(in & SSB_GPIO_XTAL)) { - if (what & SSB_GPIO_XTAL) { - /* Turn the crystal on */ - out |= SSB_GPIO_XTAL; - if (what & SSB_GPIO_PLL) - out |= SSB_GPIO_PLL; - err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT, out); - if (err) - goto err_pci; - err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT_ENABLE, - outenable); - if (err) - goto err_pci; - msleep(1); - } - if (what & SSB_GPIO_PLL) { - /* Turn the PLL on */ - out &= ~SSB_GPIO_PLL; - err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT, out); - if (err) - goto err_pci; - msleep(5); - } - } - - err = pci_read_config_word(bus->host_pci, PCI_STATUS, &pci_status); - if (err) - goto err_pci; - pci_status &= ~PCI_STATUS_SIG_TARGET_ABORT; - err = pci_write_config_word(bus->host_pci, PCI_STATUS, pci_status); - if (err) - goto err_pci; - } else { - if (what & SSB_GPIO_XTAL) { - /* Turn the crystal off */ - out &= ~SSB_GPIO_XTAL; - } - if (what & SSB_GPIO_PLL) { - /* Turn the PLL off */ - out |= SSB_GPIO_PLL; - } - err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT, out); - if (err) - goto err_pci; - err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT_ENABLE, outenable); - if (err) - goto err_pci; - } - -out: - return err; - -err_pci: - printk(KERN_ERR PFX "Error: ssb_pci_xtal() could not access PCI config space!\n"); - err = -EBUSY; - goto out; -} - -/* Get the word-offset for a SSB_SPROM_XXX define. */ -#define SPOFF(offset) (((offset) - SSB_SPROM_BASE) / sizeof(u16)) -/* Helper to extract some _offset, which is one of the SSB_SPROM_XXX defines. */ -#define SPEX(_outvar, _offset, _mask, _shift) \ - out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift)) - -static inline u8 ssb_crc8(u8 crc, u8 data) -{ - /* Polynomial: x^8 + x^7 + x^6 + x^4 + x^2 + 1 */ - static const u8 t[] = { - 0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B, - 0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21, - 0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF, - 0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5, - 0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14, - 0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E, - 0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80, - 0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA, - 0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95, - 0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF, - 0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01, - 0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B, - 0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA, - 0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0, - 0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E, - 0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34, - 0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0, - 0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A, - 0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54, - 0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E, - 0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF, - 0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5, - 0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B, - 0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61, - 0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E, - 0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74, - 0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA, - 0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0, - 0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41, - 0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B, - 0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5, - 0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F, - }; - return t[crc ^ data]; -} - -static u8 ssb_sprom_crc(const u16 *sprom, u16 size) -{ - int word; - u8 crc = 0xFF; - - for (word = 0; word < size - 1; word++) { - crc = ssb_crc8(crc, sprom[word] & 0x00FF); - crc = ssb_crc8(crc, (sprom[word] & 0xFF00) >> 8); - } - crc = ssb_crc8(crc, sprom[size - 1] & 0x00FF); - crc ^= 0xFF; - - return crc; -} - -static int sprom_check_crc(const u16 *sprom, u16 size) -{ - u8 crc; - u8 expected_crc; - u16 tmp; - - crc = ssb_sprom_crc(sprom, size); - tmp = sprom[size - 1] & SSB_SPROM_REVISION_CRC; - expected_crc = tmp >> SSB_SPROM_REVISION_CRC_SHIFT; - if (crc != expected_crc) - return -EPROTO; - - return 0; -} - -static void sprom_do_read(struct ssb_bus *bus, u16 *sprom) -{ - int i; - - for (i = 0; i < bus->sprom_size; i++) - sprom[i] = ioread16(bus->mmio + SSB_SPROM_BASE + (i * 2)); -} - -static int sprom_do_write(struct ssb_bus *bus, const u16 *sprom) -{ - struct pci_dev *pdev = bus->host_pci; - int i, err; - u32 spromctl; - u16 size = bus->sprom_size; - - ssb_printk(KERN_NOTICE PFX "Writing SPROM. Do NOT turn off the power! Please stand by...\n"); - err = pci_read_config_dword(pdev, SSB_SPROMCTL, &spromctl); - if (err) - goto err_ctlreg; - spromctl |= SSB_SPROMCTL_WE; - err = pci_write_config_dword(pdev, SSB_SPROMCTL, spromctl); - if (err) - goto err_ctlreg; - ssb_printk(KERN_NOTICE PFX "[ 0%%"); - msleep(500); - for (i = 0; i < size; i++) { - if (i == size / 4) - ssb_printk("25%%"); - else if (i == size / 2) - ssb_printk("50%%"); - else if (i == (size * 3) / 4) - ssb_printk("75%%"); - else if (i % 2) - ssb_printk("."); - writew(sprom[i], bus->mmio + SSB_SPROM_BASE + (i * 2)); - mmiowb(); - msleep(20); - } - err = pci_read_config_dword(pdev, SSB_SPROMCTL, &spromctl); - if (err) - goto err_ctlreg; - spromctl &= ~SSB_SPROMCTL_WE; - err = pci_write_config_dword(pdev, SSB_SPROMCTL, spromctl); - if (err) - goto err_ctlreg; - msleep(500); - ssb_printk("100%% ]\n"); - ssb_printk(KERN_NOTICE PFX "SPROM written.\n"); - - return 0; -err_ctlreg: - ssb_printk(KERN_ERR PFX "Could not access SPROM control register.\n"); - return err; -} - -static s8 r123_extract_antgain(u8 sprom_revision, const u16 *in, - u16 mask, u16 shift) -{ - u16 v; - u8 gain; - - v = in[SPOFF(SSB_SPROM1_AGAIN)]; - gain = (v & mask) >> shift; - if (gain == 0xFF) - gain = 2; /* If unset use 2dBm */ - if (sprom_revision == 1) { - /* Convert to Q5.2 */ - gain <<= 2; - } else { - /* Q5.2 Fractional part is stored in 0xC0 */ - gain = ((gain & 0xC0) >> 6) | ((gain & 0x3F) << 2); - } - - return (s8)gain; -} - -static void sprom_extract_r123(struct ssb_sprom *out, const u16 *in) -{ - int i; - u16 v; - s8 gain; - u16 loc[3]; - - if (out->revision == 3) { /* rev 3 moved MAC */ - loc[0] = SSB_SPROM3_IL0MAC; - loc[1] = SSB_SPROM3_ET0MAC; - loc[2] = SSB_SPROM3_ET1MAC; - } else { - loc[0] = SSB_SPROM1_IL0MAC; - loc[1] = SSB_SPROM1_ET0MAC; - loc[2] = SSB_SPROM1_ET1MAC; - } - for (i = 0; i < 3; i++) { - v = in[SPOFF(loc[0]) + i]; - *(((__be16 *)out->il0mac) + i) = cpu_to_be16(v); - } - for (i = 0; i < 3; i++) { - v = in[SPOFF(loc[1]) + i]; - *(((__be16 *)out->et0mac) + i) = cpu_to_be16(v); - } - for (i = 0; i < 3; i++) { - v = in[SPOFF(loc[2]) + i]; - *(((__be16 *)out->et1mac) + i) = cpu_to_be16(v); - } - SPEX(et0phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0A, 0); - SPEX(et1phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1A, - SSB_SPROM1_ETHPHY_ET1A_SHIFT); - SPEX(et0mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0M, 14); - SPEX(et1mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1M, 15); - SPEX(board_rev, SSB_SPROM1_BINF, SSB_SPROM1_BINF_BREV, 0); - SPEX(country_code, SSB_SPROM1_BINF, SSB_SPROM1_BINF_CCODE, - SSB_SPROM1_BINF_CCODE_SHIFT); - SPEX(ant_available_a, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTA, - SSB_SPROM1_BINF_ANTA_SHIFT); - SPEX(ant_available_bg, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTBG, - SSB_SPROM1_BINF_ANTBG_SHIFT); - SPEX(pa0b0, SSB_SPROM1_PA0B0, 0xFFFF, 0); - SPEX(pa0b1, SSB_SPROM1_PA0B1, 0xFFFF, 0); - SPEX(pa0b2, SSB_SPROM1_PA0B2, 0xFFFF, 0); - SPEX(pa1b0, SSB_SPROM1_PA1B0, 0xFFFF, 0); - SPEX(pa1b1, SSB_SPROM1_PA1B1, 0xFFFF, 0); - SPEX(pa1b2, SSB_SPROM1_PA1B2, 0xFFFF, 0); - SPEX(gpio0, SSB_SPROM1_GPIOA, SSB_SPROM1_GPIOA_P0, 0); - SPEX(gpio1, SSB_SPROM1_GPIOA, SSB_SPROM1_GPIOA_P1, - SSB_SPROM1_GPIOA_P1_SHIFT); - SPEX(gpio2, SSB_SPROM1_GPIOB, SSB_SPROM1_GPIOB_P2, 0); - SPEX(gpio3, SSB_SPROM1_GPIOB, SSB_SPROM1_GPIOB_P3, - SSB_SPROM1_GPIOB_P3_SHIFT); - SPEX(maxpwr_a, SSB_SPROM1_MAXPWR, SSB_SPROM1_MAXPWR_A, - SSB_SPROM1_MAXPWR_A_SHIFT); - SPEX(maxpwr_bg, SSB_SPROM1_MAXPWR, SSB_SPROM1_MAXPWR_BG, 0); - SPEX(itssi_a, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_A, - SSB_SPROM1_ITSSI_A_SHIFT); - SPEX(itssi_bg, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_BG, 0); - SPEX(boardflags_lo, SSB_SPROM1_BFLLO, 0xFFFF, 0); - if (out->revision >= 2) - SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0); - - /* Extract the antenna gain values. */ - gain = r123_extract_antgain(out->revision, in, - SSB_SPROM1_AGAIN_BG, - SSB_SPROM1_AGAIN_BG_SHIFT); - out->antenna_gain.ghz24.a0 = gain; - out->antenna_gain.ghz24.a1 = gain; - out->antenna_gain.ghz24.a2 = gain; - out->antenna_gain.ghz24.a3 = gain; - gain = r123_extract_antgain(out->revision, in, - SSB_SPROM1_AGAIN_A, - SSB_SPROM1_AGAIN_A_SHIFT); - out->antenna_gain.ghz5.a0 = gain; - out->antenna_gain.ghz5.a1 = gain; - out->antenna_gain.ghz5.a2 = gain; - out->antenna_gain.ghz5.a3 = gain; -} - -static void sprom_extract_r4(struct ssb_sprom *out, const u16 *in) -{ - int i; - u16 v; - - /* extract the equivalent of the r1 variables */ - for (i = 0; i < 3; i++) { - v = in[SPOFF(SSB_SPROM4_IL0MAC) + i]; - *(((__be16 *)out->il0mac) + i) = cpu_to_be16(v); - } - for (i = 0; i < 3; i++) { - v = in[SPOFF(SSB_SPROM4_ET0MAC) + i]; - *(((__be16 *)out->et0mac) + i) = cpu_to_be16(v); - } - for (i = 0; i < 3; i++) { - v = in[SPOFF(SSB_SPROM4_ET1MAC) + i]; - *(((__be16 *)out->et1mac) + i) = cpu_to_be16(v); - } - SPEX(et0phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET0A, 0); - SPEX(et1phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET1A, - SSB_SPROM4_ETHPHY_ET1A_SHIFT); - SPEX(country_code, SSB_SPROM4_CCODE, 0xFFFF, 0); - SPEX(boardflags_lo, SSB_SPROM4_BFLLO, 0xFFFF, 0); - SPEX(boardflags_hi, SSB_SPROM4_BFLHI, 0xFFFF, 0); - SPEX(ant_available_a, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_A, - SSB_SPROM4_ANTAVAIL_A_SHIFT); - SPEX(ant_available_bg, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_BG, - SSB_SPROM4_ANTAVAIL_BG_SHIFT); - SPEX(maxpwr_bg, SSB_SPROM4_MAXP_BG, SSB_SPROM4_MAXP_BG_MASK, 0); - SPEX(itssi_bg, SSB_SPROM4_MAXP_BG, SSB_SPROM4_ITSSI_BG, - SSB_SPROM4_ITSSI_BG_SHIFT); - SPEX(maxpwr_a, SSB_SPROM4_MAXP_A, SSB_SPROM4_MAXP_A_MASK, 0); - SPEX(itssi_a, SSB_SPROM4_MAXP_A, SSB_SPROM4_ITSSI_A, - SSB_SPROM4_ITSSI_A_SHIFT); - SPEX(gpio0, SSB_SPROM4_GPIOA, SSB_SPROM4_GPIOA_P0, 0); - SPEX(gpio1, SSB_SPROM4_GPIOA, SSB_SPROM4_GPIOA_P1, - SSB_SPROM4_GPIOA_P1_SHIFT); - SPEX(gpio2, SSB_SPROM4_GPIOB, SSB_SPROM4_GPIOB_P2, 0); - SPEX(gpio3, SSB_SPROM4_GPIOB, SSB_SPROM4_GPIOB_P3, - SSB_SPROM4_GPIOB_P3_SHIFT); - - /* Extract the antenna gain values. */ - SPEX(antenna_gain.ghz24.a0, SSB_SPROM4_AGAIN01, - SSB_SPROM4_AGAIN0, SSB_SPROM4_AGAIN0_SHIFT); - SPEX(antenna_gain.ghz24.a1, SSB_SPROM4_AGAIN01, - SSB_SPROM4_AGAIN1, SSB_SPROM4_AGAIN1_SHIFT); - SPEX(antenna_gain.ghz24.a2, SSB_SPROM4_AGAIN23, - SSB_SPROM4_AGAIN2, SSB_SPROM4_AGAIN2_SHIFT); - SPEX(antenna_gain.ghz24.a3, SSB_SPROM4_AGAIN23, - SSB_SPROM4_AGAIN3, SSB_SPROM4_AGAIN3_SHIFT); - memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24, - sizeof(out->antenna_gain.ghz5)); - - /* TODO - get remaining rev 4 stuff needed */ -} - -static int sprom_extract(struct ssb_bus *bus, struct ssb_sprom *out, - const u16 *in, u16 size) -{ - memset(out, 0, sizeof(*out)); - - out->revision = in[size - 1] & 0x00FF; - ssb_dprintk(KERN_DEBUG PFX "SPROM revision %d detected.\n", out->revision); - if ((bus->chip_id & 0xFF00) == 0x4400) { - /* Workaround: The BCM44XX chip has a stupid revision - * number stored in the SPROM. - * Always extract r1. */ - out->revision = 1; - sprom_extract_r123(out, in); - } else if (bus->chip_id == 0x4321) { - /* the BCM4328 has a chipid == 0x4321 and a rev 4 SPROM */ - out->revision = 4; - sprom_extract_r4(out, in); - } else { - if (out->revision == 0) - goto unsupported; - if (out->revision >= 1 && out->revision <= 3) { - sprom_extract_r123(out, in); - } - if (out->revision == 4) - sprom_extract_r4(out, in); - if (out->revision >= 5) - goto unsupported; - } - - return 0; -unsupported: - ssb_printk(KERN_WARNING PFX "Unsupported SPROM revision %d " - "detected. Will extract v1\n", out->revision); - sprom_extract_r123(out, in); - return 0; -} - -static int ssb_pci_sprom_get(struct ssb_bus *bus, - struct ssb_sprom *sprom) -{ - int err = -ENOMEM; - u16 *buf; - - buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL); - if (!buf) - goto out; - bus->sprom_size = SSB_SPROMSIZE_WORDS_R123; - sprom_do_read(bus, buf); - err = sprom_check_crc(buf, bus->sprom_size); - if (err) { - /* check for rev 4 sprom - has special signature */ - if (buf[32] == 0x5372) { - kfree(buf); - buf = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16), - GFP_KERNEL); - if (!buf) - goto out; - bus->sprom_size = SSB_SPROMSIZE_WORDS_R4; - sprom_do_read(bus, buf); - err = sprom_check_crc(buf, bus->sprom_size); - } - if (err) - ssb_printk(KERN_WARNING PFX "WARNING: Invalid" - " SPROM CRC (corrupt SPROM)\n"); - } - err = sprom_extract(bus, sprom, buf, bus->sprom_size); - - kfree(buf); -out: - return err; -} - -static void ssb_pci_get_boardinfo(struct ssb_bus *bus, - struct ssb_boardinfo *bi) -{ - pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_VENDOR_ID, - &bi->vendor); - pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_ID, - &bi->type); - pci_read_config_word(bus->host_pci, PCI_REVISION_ID, - &bi->rev); -} - -int ssb_pci_get_invariants(struct ssb_bus *bus, - struct ssb_init_invariants *iv) -{ - int err; - - err = ssb_pci_sprom_get(bus, &iv->sprom); - if (err) - goto out; - ssb_pci_get_boardinfo(bus, &iv->boardinfo); - -out: - return err; -} - -#ifdef CONFIG_SSB_DEBUG -static int ssb_pci_assert_buspower(struct ssb_bus *bus) -{ - if (likely(bus->powered_up)) - return 0; - - printk(KERN_ERR PFX "FATAL ERROR: Bus powered down " - "while accessing PCI MMIO space\n"); - if (bus->power_warn_count <= 10) { - bus->power_warn_count++; - dump_stack(); - } - - return -ENODEV; -} -#else /* DEBUG */ -static inline int ssb_pci_assert_buspower(struct ssb_bus *bus) -{ - return 0; -} -#endif /* DEBUG */ - -static u16 ssb_pci_read16(struct ssb_device *dev, u16 offset) -{ - struct ssb_bus *bus = dev->bus; - - if (unlikely(ssb_pci_assert_buspower(bus))) - return 0xFFFF; - if (unlikely(bus->mapped_device != dev)) { - if (unlikely(ssb_pci_switch_core(bus, dev))) - return 0xFFFF; - } - return ioread16(bus->mmio + offset); -} - -static u32 ssb_pci_read32(struct ssb_device *dev, u16 offset) -{ - struct ssb_bus *bus = dev->bus; - - if (unlikely(ssb_pci_assert_buspower(bus))) - return 0xFFFFFFFF; - if (unlikely(bus->mapped_device != dev)) { - if (unlikely(ssb_pci_switch_core(bus, dev))) - return 0xFFFFFFFF; - } - return ioread32(bus->mmio + offset); -} - -static void ssb_pci_write16(struct ssb_device *dev, u16 offset, u16 value) -{ - struct ssb_bus *bus = dev->bus; - - if (unlikely(ssb_pci_assert_buspower(bus))) - return; - if (unlikely(bus->mapped_device != dev)) { - if (unlikely(ssb_pci_switch_core(bus, dev))) - return; - } - iowrite16(value, bus->mmio + offset); -} - -static void ssb_pci_write32(struct ssb_device *dev, u16 offset, u32 value) -{ - struct ssb_bus *bus = dev->bus; - - if (unlikely(ssb_pci_assert_buspower(bus))) - return; - if (unlikely(bus->mapped_device != dev)) { - if (unlikely(ssb_pci_switch_core(bus, dev))) - return; - } - iowrite32(value, bus->mmio + offset); -} - -/* Not "static", as it's used in main.c */ -const struct ssb_bus_ops ssb_pci_ops = { - .read16 = ssb_pci_read16, - .read32 = ssb_pci_read32, - .write16 = ssb_pci_write16, - .write32 = ssb_pci_write32, -}; - -static int sprom2hex(const u16 *sprom, char *buf, size_t buf_len, u16 size) -{ - int i, pos = 0; - - for (i = 0; i < size; i++) - pos += snprintf(buf + pos, buf_len - pos - 1, - "%04X", swab16(sprom[i]) & 0xFFFF); - pos += snprintf(buf + pos, buf_len - pos - 1, "\n"); - - return pos + 1; -} - -static int hex2sprom(u16 *sprom, const char *dump, size_t len, u16 size) -{ - char tmp[5] = { 0 }; - int cnt = 0; - unsigned long parsed; - - if (len < size * 2) - return -EINVAL; - - while (cnt < size) { - memcpy(tmp, dump, 4); - dump += 4; - parsed = simple_strtoul(tmp, NULL, 16); - sprom[cnt++] = swab16((u16)parsed); - } - - return 0; -} - -static ssize_t ssb_pci_attr_sprom_show(struct device *pcidev, - struct device_attribute *attr, - char *buf) -{ - struct pci_dev *pdev = container_of(pcidev, struct pci_dev, dev); - struct ssb_bus *bus; - u16 *sprom; - int err = -ENODEV; - ssize_t count = 0; - - bus = ssb_pci_dev_to_bus(pdev); - if (!bus) - goto out; - err = -ENOMEM; - sprom = kcalloc(bus->sprom_size, sizeof(u16), GFP_KERNEL); - if (!sprom) - goto out; - - /* Use interruptible locking, as the SPROM write might - * be holding the lock for several seconds. So allow userspace - * to cancel operation. */ - err = -ERESTARTSYS; - if (mutex_lock_interruptible(&bus->pci_sprom_mutex)) - goto out_kfree; - sprom_do_read(bus, sprom); - mutex_unlock(&bus->pci_sprom_mutex); - - count = sprom2hex(sprom, buf, PAGE_SIZE, bus->sprom_size); - err = 0; - -out_kfree: - kfree(sprom); -out: - return err ? err : count; -} - -static ssize_t ssb_pci_attr_sprom_store(struct device *pcidev, - struct device_attribute *attr, - const char *buf, size_t count) -{ - struct pci_dev *pdev = container_of(pcidev, struct pci_dev, dev); - struct ssb_bus *bus; - u16 *sprom; - int res = 0, err = -ENODEV; - - bus = ssb_pci_dev_to_bus(pdev); - if (!bus) - goto out; - err = -ENOMEM; - sprom = kcalloc(bus->sprom_size, sizeof(u16), GFP_KERNEL); - if (!sprom) - goto out; - err = hex2sprom(sprom, buf, count, bus->sprom_size); - if (err) { - err = -EINVAL; - goto out_kfree; - } - err = sprom_check_crc(sprom, bus->sprom_size); - if (err) { - err = -EINVAL; - goto out_kfree; - } - - /* Use interruptible locking, as the SPROM write might - * be holding the lock for several seconds. So allow userspace - * to cancel operation. */ - err = -ERESTARTSYS; - if (mutex_lock_interruptible(&bus->pci_sprom_mutex)) - goto out_kfree; - err = ssb_devices_freeze(bus); - if (err == -EOPNOTSUPP) { - ssb_printk(KERN_ERR PFX "SPROM write: Could not freeze devices. " - "No suspend support. Is CONFIG_PM enabled?\n"); - goto out_unlock; - } - if (err) { - ssb_printk(KERN_ERR PFX "SPROM write: Could not freeze all devices\n"); - goto out_unlock; - } - res = sprom_do_write(bus, sprom); - err = ssb_devices_thaw(bus); - if (err) - ssb_printk(KERN_ERR PFX "SPROM write: Could not thaw all devices\n"); -out_unlock: - mutex_unlock(&bus->pci_sprom_mutex); -out_kfree: - kfree(sprom); -out: - if (res) - return res; - return err ? err : count; -} - -static DEVICE_ATTR(ssb_sprom, 0600, - ssb_pci_attr_sprom_show, - ssb_pci_attr_sprom_store); - -void ssb_pci_exit(struct ssb_bus *bus) -{ - struct pci_dev *pdev; - - if (bus->bustype != SSB_BUSTYPE_PCI) - return; - - pdev = bus->host_pci; - device_remove_file(&pdev->dev, &dev_attr_ssb_sprom); -} - -int ssb_pci_init(struct ssb_bus *bus) -{ - struct pci_dev *pdev; - int err; - - if (bus->bustype != SSB_BUSTYPE_PCI) - return 0; - - pdev = bus->host_pci; - mutex_init(&bus->pci_sprom_mutex); - err = device_create_file(&pdev->dev, &dev_attr_ssb_sprom); - if (err) - goto out; - -out: - return err; -} diff --git a/target/linux/generic-2.6/files/drivers/ssb/pcihost_wrapper.c b/target/linux/generic-2.6/files/drivers/ssb/pcihost_wrapper.c deleted file mode 100644 index 82a10abef6..0000000000 --- a/target/linux/generic-2.6/files/drivers/ssb/pcihost_wrapper.c +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Sonics Silicon Backplane - * PCI Hostdevice wrapper - * - * Copyright (c) 2005 Martin Langer <martin-langer@gmx.de> - * Copyright (c) 2005 Stefano Brivio <st3@riseup.net> - * Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org> - * Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch> - * Copyright (c) 2005-2007 Michael Buesch <mbuesch@freenet.de> - * - * Licensed under the GNU/GPL. See COPYING for details. - */ - -#include <linux/pci.h> -#include <linux/ssb/ssb.h> - - -#ifdef CONFIG_PM -static int ssb_pcihost_suspend(struct pci_dev *dev, pm_message_t state) -{ - pci_save_state(dev); - pci_disable_device(dev); - pci_set_power_state(dev, pci_choose_state(dev, state)); - - return 0; -} - -static int ssb_pcihost_resume(struct pci_dev *dev) -{ - int err; - - pci_set_power_state(dev, 0); - err = pci_enable_device(dev); - if (err) - return err; - pci_restore_state(dev); - - return 0; -} -#else /* CONFIG_PM */ -# define ssb_pcihost_suspend NULL -# define ssb_pcihost_resume NULL -#endif /* CONFIG_PM */ - -static int ssb_pcihost_probe(struct pci_dev *dev, - const struct pci_device_id *id) -{ - struct ssb_bus *ssb; - int err = -ENOMEM; - const char *name; - - ssb = kzalloc(sizeof(*ssb), GFP_KERNEL); - if (!ssb) - goto out; - err = pci_enable_device(dev); - if (err) - goto err_kfree_ssb; - name = dev->dev.bus_id; - if (dev->driver && dev->driver->name) - name = dev->driver->name; - err = pci_request_regions(dev, name); - if (err) - goto err_pci_disable; - pci_set_master(dev); - - err = ssb_bus_pcibus_register(ssb, dev); - if (err) - goto err_pci_release_regions; - - pci_set_drvdata(dev, ssb); - -out: - return err; - -err_pci_release_regions: - pci_release_regions(dev); -err_pci_disable: - pci_disable_device(dev); -err_kfree_ssb: - kfree(ssb); - return err; -} - -static void ssb_pcihost_remove(struct pci_dev *dev) -{ - struct ssb_bus *ssb = pci_get_drvdata(dev); - - ssb_bus_unregister(ssb); - pci_release_regions(dev); - pci_disable_device(dev); - kfree(ssb); - pci_set_drvdata(dev, NULL); -} - -int ssb_pcihost_register(struct pci_driver *driver) -{ - driver->probe = ssb_pcihost_probe; - driver->remove = ssb_pcihost_remove; - driver->suspend = ssb_pcihost_suspend; - driver->resume = ssb_pcihost_resume; - - return pci_register_driver(driver); -} -EXPORT_SYMBOL(ssb_pcihost_register); diff --git a/target/linux/generic-2.6/files/drivers/ssb/pcmcia.c b/target/linux/generic-2.6/files/drivers/ssb/pcmcia.c deleted file mode 100644 index 46816cda8b..0000000000 --- a/target/linux/generic-2.6/files/drivers/ssb/pcmcia.c +++ /dev/null @@ -1,287 +0,0 @@ -/* - * Sonics Silicon Backplane - * PCMCIA-Hostbus related functions - * - * Copyright 2006 Johannes Berg <johannes@sipsolutions.net> - * Copyright 2007 Michael Buesch <mb@bu3sch.de> - * - * Licensed under the GNU/GPL. See COPYING for details. - */ - -#include <linux/ssb/ssb.h> -#include <linux/delay.h> -#include <linux/io.h> - -#include <pcmcia/cs_types.h> -#include <pcmcia/cs.h> -#include <pcmcia/cistpl.h> -#include <pcmcia/ciscode.h> -#include <pcmcia/ds.h> -#include <pcmcia/cisreg.h> - -#include "ssb_private.h" - - -/* Define the following to 1 to enable a printk on each coreswitch. */ -#define SSB_VERBOSE_PCMCIACORESWITCH_DEBUG 0 - - -int ssb_pcmcia_switch_coreidx(struct ssb_bus *bus, - u8 coreidx) -{ - struct pcmcia_device *pdev = bus->host_pcmcia; - int err; - int attempts = 0; - u32 cur_core; - conf_reg_t reg; - u32 addr; - u32 read_addr; - - addr = (coreidx * SSB_CORE_SIZE) + SSB_ENUM_BASE; - while (1) { - reg.Action = CS_WRITE; - reg.Offset = 0x2E; - reg.Value = (addr & 0x0000F000) >> 12; - err = pcmcia_access_configuration_register(pdev, ®); - if (err != CS_SUCCESS) - goto error; - reg.Offset = 0x30; - reg.Value = (addr & 0x00FF0000) >> 16; - err = pcmcia_access_configuration_register(pdev, ®); - if (err != CS_SUCCESS) - goto error; - reg.Offset = 0x32; - reg.Value = (addr & 0xFF000000) >> 24; - err = pcmcia_access_configuration_register(pdev, ®); - if (err != CS_SUCCESS) - goto error; - - read_addr = 0; - - reg.Action = CS_READ; - reg.Offset = 0x2E; - err = pcmcia_access_configuration_register(pdev, ®); - if (err != CS_SUCCESS) - goto error; - read_addr |= ((u32)(reg.Value & 0x0F)) << 12; - reg.Offset = 0x30; - err = pcmcia_access_configuration_register(pdev, ®); - if (err != CS_SUCCESS) - goto error; - read_addr |= ((u32)reg.Value) << 16; - reg.Offset = 0x32; - err = pcmcia_access_configuration_register(pdev, ®); - if (err != CS_SUCCESS) - goto error; - read_addr |= ((u32)reg.Value) << 24; - - cur_core = (read_addr - SSB_ENUM_BASE) / SSB_CORE_SIZE; - if (cur_core == coreidx) - break; - - if (attempts++ > SSB_BAR0_MAX_RETRIES) - goto error; - udelay(10); - } - - return 0; -error: - ssb_printk(KERN_ERR PFX "Failed to switch to core %u\n", coreidx); - return -ENODEV; -} - -int ssb_pcmcia_switch_core(struct ssb_bus *bus, - struct ssb_device *dev) -{ - int err; - -#if SSB_VERBOSE_PCMCIACORESWITCH_DEBUG - ssb_printk(KERN_INFO PFX - "Switching to %s core, index %d\n", - ssb_core_name(dev->id.coreid), - dev->core_index); -#endif - - err = ssb_pcmcia_switch_coreidx(bus, dev->core_index); - if (!err) - bus->mapped_device = dev; - - return err; -} - -int ssb_pcmcia_switch_segment(struct ssb_bus *bus, u8 seg) -{ - int attempts = 0; - conf_reg_t reg; - int res; - - SSB_WARN_ON((seg != 0) && (seg != 1)); - reg.Offset = 0x34; - reg.Function = 0; - while (1) { - reg.Action = CS_WRITE; - reg.Value = seg; - res = pcmcia_access_configuration_register(bus->host_pcmcia, ®); - if (unlikely(res != CS_SUCCESS)) - goto error; - reg.Value = 0xFF; - reg.Action = CS_READ; - res = pcmcia_access_configuration_register(bus->host_pcmcia, ®); - if (unlikely(res != CS_SUCCESS)) - goto error; - - if (reg.Value == seg) - break; - - if (unlikely(attempts++ > SSB_BAR0_MAX_RETRIES)) - goto error; - udelay(10); - } - bus->mapped_pcmcia_seg = seg; - - return 0; -error: - ssb_printk(KERN_ERR PFX "Failed to switch pcmcia segment\n"); - return -ENODEV; -} - -static int select_core_and_segment(struct ssb_device *dev, - u16 *offset) -{ - struct ssb_bus *bus = dev->bus; - int err; - u8 need_segment; - - if (*offset >= 0x800) { - *offset -= 0x800; - need_segment = 1; - } else - need_segment = 0; - - if (unlikely(dev != bus->mapped_device)) { - err = ssb_pcmcia_switch_core(bus, dev); - if (unlikely(err)) - return err; - } - if (unlikely(need_segment != bus->mapped_pcmcia_seg)) { - err = ssb_pcmcia_switch_segment(bus, need_segment); - if (unlikely(err)) - return err; - } - - return 0; -} - -static u16 ssb_pcmcia_read16(struct ssb_device *dev, u16 offset) -{ - struct ssb_bus *bus = dev->bus; - unsigned long flags; - int err; - u16 value = 0xFFFF; - - spin_lock_irqsave(&bus->bar_lock, flags); - err = select_core_and_segment(dev, &offset); - if (likely(!err)) - value = readw(bus->mmio + offset); - spin_unlock_irqrestore(&bus->bar_lock, flags); - - return value; -} - -static u32 ssb_pcmcia_read32(struct ssb_device *dev, u16 offset) -{ - struct ssb_bus *bus = dev->bus; - unsigned long flags; - int err; - u32 lo = 0xFFFFFFFF, hi = 0xFFFFFFFF; - - spin_lock_irqsave(&bus->bar_lock, flags); - err = select_core_and_segment(dev, &offset); - if (likely(!err)) { - lo = readw(bus->mmio + offset); - hi = readw(bus->mmio + offset + 2); - } - spin_unlock_irqrestore(&bus->bar_lock, flags); - - return (lo | (hi << 16)); -} - -static void ssb_pcmcia_write16(struct ssb_device *dev, u16 offset, u16 value) -{ - struct ssb_bus *bus = dev->bus; - unsigned long flags; - int err; - - spin_lock_irqsave(&bus->bar_lock, flags); - err = select_core_and_segment(dev, &offset); - if (likely(!err)) - writew(value, bus->mmio + offset); - mmiowb(); - spin_unlock_irqrestore(&bus->bar_lock, flags); -} - -static void ssb_pcmcia_write32(struct ssb_device *dev, u16 offset, u32 value) -{ - struct ssb_bus *bus = dev->bus; - unsigned long flags; - int err; - - spin_lock_irqsave(&bus->bar_lock, flags); - err = select_core_and_segment(dev, &offset); - if (likely(!err)) { - writew((value & 0x0000FFFF), bus->mmio + offset); - writew(((value & 0xFFFF0000) >> 16), bus->mmio + offset + 2); - } - mmiowb(); - spin_unlock_irqrestore(&bus->bar_lock, flags); -} - -/* Not "static", as it's used in main.c */ -const struct ssb_bus_ops ssb_pcmcia_ops = { - .read16 = ssb_pcmcia_read16, - .read32 = ssb_pcmcia_read32, - .write16 = ssb_pcmcia_write16, - .write32 = ssb_pcmcia_write32, -}; - -#include <linux/etherdevice.h> -int ssb_pcmcia_get_invariants(struct ssb_bus *bus, - struct ssb_init_invariants *iv) -{ - //TODO - random_ether_addr(iv->sprom.il0mac); - return 0; -} - -int ssb_pcmcia_init(struct ssb_bus *bus) -{ - conf_reg_t reg; - int err; - - if (bus->bustype != SSB_BUSTYPE_PCMCIA) - return 0; - - /* Switch segment to a known state and sync - * bus->mapped_pcmcia_seg with hardware state. */ - ssb_pcmcia_switch_segment(bus, 0); - - /* Init IRQ routing */ - reg.Action = CS_READ; - reg.Function = 0; - if (bus->chip_id == 0x4306) - reg.Offset = 0x00; - else - reg.Offset = 0x80; - err = pcmcia_access_configuration_register(bus->host_pcmcia, ®); - if (err != CS_SUCCESS) - goto error; - reg.Action = CS_WRITE; - reg.Value |= 0x04 | 0x01; - err = pcmcia_access_configuration_register(bus->host_pcmcia, ®); - if (err != CS_SUCCESS) - goto error; - - return 0; -error: - return -ENODEV; -} diff --git a/target/linux/generic-2.6/files/drivers/ssb/scan.c b/target/linux/generic-2.6/files/drivers/ssb/scan.c deleted file mode 100644 index 63ee5cfbef..0000000000 --- a/target/linux/generic-2.6/files/drivers/ssb/scan.c +++ /dev/null @@ -1,424 +0,0 @@ -/* - * Sonics Silicon Backplane - * Bus scanning - * - * Copyright (C) 2005-2007 Michael Buesch <mb@bu3sch.de> - * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de> - * Copyright (C) 2005 Stefano Brivio <st3@riseup.net> - * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org> - * Copyright (C) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch> - * Copyright (C) 2006 Broadcom Corporation. - * - * Licensed under the GNU/GPL. See COPYING for details. - */ - -#include <linux/ssb/ssb.h> -#include <linux/ssb/ssb_regs.h> -#include <linux/pci.h> -#include <linux/io.h> - -#include <pcmcia/cs_types.h> -#include <pcmcia/cs.h> -#include <pcmcia/cistpl.h> -#include <pcmcia/ds.h> - -#include "ssb_private.h" - - -const char *ssb_core_name(u16 coreid) -{ - switch (coreid) { - case SSB_DEV_CHIPCOMMON: - return "ChipCommon"; - case SSB_DEV_ILINE20: - return "ILine 20"; - case SSB_DEV_SDRAM: - return "SDRAM"; - case SSB_DEV_PCI: - return "PCI"; - case SSB_DEV_MIPS: - return "MIPS"; - case SSB_DEV_ETHERNET: - return "Fast Ethernet"; - case SSB_DEV_V90: - return "V90"; - case SSB_DEV_USB11_HOSTDEV: - return "USB 1.1 Hostdev"; - case SSB_DEV_ADSL: - return "ADSL"; - case SSB_DEV_ILINE100: - return "ILine 100"; - case SSB_DEV_IPSEC: - return "IPSEC"; - case SSB_DEV_PCMCIA: - return "PCMCIA"; - case SSB_DEV_INTERNAL_MEM: - return "Internal Memory"; - case SSB_DEV_MEMC_SDRAM: - return "MEMC SDRAM"; - case SSB_DEV_EXTIF: - return "EXTIF"; - case SSB_DEV_80211: - return "IEEE 802.11"; - case SSB_DEV_MIPS_3302: - return "MIPS 3302"; - case SSB_DEV_USB11_HOST: - return "USB 1.1 Host"; - case SSB_DEV_USB11_DEV: - return "USB 1.1 Device"; - case SSB_DEV_USB20_HOST: - return "USB 2.0 Host"; - case SSB_DEV_USB20_DEV: - return "USB 2.0 Device"; - case SSB_DEV_SDIO_HOST: - return "SDIO Host"; - case SSB_DEV_ROBOSWITCH: - return "Roboswitch"; - case SSB_DEV_PARA_ATA: - return "PATA"; - case SSB_DEV_SATA_XORDMA: - return "SATA XOR-DMA"; - case SSB_DEV_ETHERNET_GBIT: - return "GBit Ethernet"; - case SSB_DEV_PCIE: - return "PCI-E"; - case SSB_DEV_MIMO_PHY: - return "MIMO PHY"; - case SSB_DEV_SRAM_CTRLR: - return "SRAM Controller"; - case SSB_DEV_MINI_MACPHY: - return "Mini MACPHY"; - case SSB_DEV_ARM_1176: - return "ARM 1176"; - case SSB_DEV_ARM_7TDMI: - return "ARM 7TDMI"; - } - return "UNKNOWN"; -} - -static u16 pcidev_to_chipid(struct pci_dev *pci_dev) -{ - u16 chipid_fallback = 0; - - switch (pci_dev->device) { - case 0x4301: - chipid_fallback = 0x4301; - break; - case 0x4305 ... 0x4307: - chipid_fallback = 0x4307; - break; - case 0x4403: - chipid_fallback = 0x4402; - break; - case 0x4610 ... 0x4615: - chipid_fallback = 0x4610; - break; - case 0x4710 ... 0x4715: - chipid_fallback = 0x4710; - break; - case 0x4320 ... 0x4325: - chipid_fallback = 0x4309; - break; - case PCI_DEVICE_ID_BCM4401: - case PCI_DEVICE_ID_BCM4401B0: - case PCI_DEVICE_ID_BCM4401B1: - chipid_fallback = 0x4401; - break; - default: - ssb_printk(KERN_ERR PFX - "PCI-ID not in fallback list\n"); - } - - return chipid_fallback; -} - -static u8 chipid_to_nrcores(u16 chipid) -{ - switch (chipid) { - case 0x5365: - return 7; - case 0x4306: - return 6; - case 0x4310: - return 8; - case 0x4307: - case 0x4301: - return 5; - case 0x4401: - case 0x4402: - return 3; - case 0x4710: - case 0x4610: - case 0x4704: - return 9; - default: - ssb_printk(KERN_ERR PFX - "CHIPID not in nrcores fallback list\n"); - } - - return 1; -} - -static u32 scan_read32(struct ssb_bus *bus, u8 current_coreidx, - u16 offset) -{ - switch (bus->bustype) { - case SSB_BUSTYPE_SSB: - offset += current_coreidx * SSB_CORE_SIZE; - break; - case SSB_BUSTYPE_PCI: - break; - case SSB_BUSTYPE_PCMCIA: - if (offset >= 0x800) { - ssb_pcmcia_switch_segment(bus, 1); - offset -= 0x800; - } else - ssb_pcmcia_switch_segment(bus, 0); - break; - } - return readl(bus->mmio + offset); -} - -static int scan_switchcore(struct ssb_bus *bus, u8 coreidx) -{ - switch (bus->bustype) { - case SSB_BUSTYPE_SSB: - break; - case SSB_BUSTYPE_PCI: - return ssb_pci_switch_coreidx(bus, coreidx); - case SSB_BUSTYPE_PCMCIA: - return ssb_pcmcia_switch_coreidx(bus, coreidx); - } - return 0; -} - -void ssb_iounmap(struct ssb_bus *bus) -{ - switch (bus->bustype) { - case SSB_BUSTYPE_SSB: - case SSB_BUSTYPE_PCMCIA: - iounmap(bus->mmio); - break; - case SSB_BUSTYPE_PCI: -#ifdef CONFIG_SSB_PCIHOST - pci_iounmap(bus->host_pci, bus->mmio); -#else - SSB_BUG_ON(1); /* Can't reach this code. */ -#endif - break; - } - bus->mmio = NULL; - bus->mapped_device = NULL; -} - -static void __iomem *ssb_ioremap(struct ssb_bus *bus, - unsigned long baseaddr) -{ - void __iomem *mmio = NULL; - - switch (bus->bustype) { - case SSB_BUSTYPE_SSB: - /* Only map the first core for now. */ - /* fallthrough... */ - case SSB_BUSTYPE_PCMCIA: - mmio = ioremap(baseaddr, SSB_CORE_SIZE); - break; - case SSB_BUSTYPE_PCI: -#ifdef CONFIG_SSB_PCIHOST - mmio = pci_iomap(bus->host_pci, 0, ~0UL); -#else - SSB_BUG_ON(1); /* Can't reach this code. */ -#endif - break; - } - - return mmio; -} - -static int we_support_multiple_80211_cores(struct ssb_bus *bus) -{ - /* More than one 802.11 core is only supported by special chips. - * There are chips with two 802.11 cores, but with dangling - * pins on the second core. Be careful and reject them here. - */ - -#ifdef CONFIG_SSB_PCIHOST - if (bus->bustype == SSB_BUSTYPE_PCI) { - if (bus->host_pci->vendor == PCI_VENDOR_ID_BROADCOM && - bus->host_pci->device == 0x4324) - return 1; - } -#endif /* CONFIG_SSB_PCIHOST */ - return 0; -} - -int ssb_bus_scan(struct ssb_bus *bus, - unsigned long baseaddr) -{ - int err = -ENOMEM; - void __iomem *mmio; - u32 idhi, cc, rev, tmp; - int dev_i, i; - struct ssb_device *dev; - int nr_80211_cores = 0; - - mmio = ssb_ioremap(bus, baseaddr); - if (!mmio) - goto out; - bus->mmio = mmio; - - err = scan_switchcore(bus, 0); /* Switch to first core */ - if (err) - goto err_unmap; - - idhi = scan_read32(bus, 0, SSB_IDHIGH); - cc = (idhi & SSB_IDHIGH_CC) >> SSB_IDHIGH_CC_SHIFT; - rev = (idhi & SSB_IDHIGH_RCLO); - rev |= (idhi & SSB_IDHIGH_RCHI) >> SSB_IDHIGH_RCHI_SHIFT; - - bus->nr_devices = 0; - if (cc == SSB_DEV_CHIPCOMMON) { - tmp = scan_read32(bus, 0, SSB_CHIPCO_CHIPID); - - bus->chip_id = (tmp & SSB_CHIPCO_IDMASK); - bus->chip_rev = (tmp & SSB_CHIPCO_REVMASK) >> - SSB_CHIPCO_REVSHIFT; - bus->chip_package = (tmp & SSB_CHIPCO_PACKMASK) >> - SSB_CHIPCO_PACKSHIFT; - if (rev >= 4) { - bus->nr_devices = (tmp & SSB_CHIPCO_NRCORESMASK) >> - SSB_CHIPCO_NRCORESSHIFT; - } - tmp = scan_read32(bus, 0, SSB_CHIPCO_CAP); - bus->chipco.capabilities = tmp; - } else { - if (bus->bustype == SSB_BUSTYPE_PCI) { - bus->chip_id = pcidev_to_chipid(bus->host_pci); - pci_read_config_word(bus->host_pci, PCI_REVISION_ID, - &bus->chip_rev); - bus->chip_package = 0; - } else { - bus->chip_id = 0x4710; - bus->chip_rev = 0; - bus->chip_package = 0; - } - } - if (!bus->nr_devices) - bus->nr_devices = chipid_to_nrcores(bus->chip_id); - if (bus->nr_devices > ARRAY_SIZE(bus->devices)) { - ssb_printk(KERN_ERR PFX - "More than %d ssb cores found (%d)\n", - SSB_MAX_NR_CORES, bus->nr_devices); - goto err_unmap; - } - if (bus->bustype == SSB_BUSTYPE_SSB) { - /* Now that we know the number of cores, - * remap the whole IO space for all cores. - */ - err = -ENOMEM; - iounmap(mmio); - mmio = ioremap(baseaddr, SSB_CORE_SIZE * bus->nr_devices); - if (!mmio) - goto out; - bus->mmio = mmio; - } - - /* Fetch basic information about each core/device */ - for (i = 0, dev_i = 0; i < bus->nr_devices; i++) { - err = scan_switchcore(bus, i); - if (err) - goto err_unmap; - dev = &(bus->devices[dev_i]); - - idhi = scan_read32(bus, i, SSB_IDHIGH); - dev->id.coreid = (idhi & SSB_IDHIGH_CC) >> SSB_IDHIGH_CC_SHIFT; - dev->id.revision = (idhi & SSB_IDHIGH_RCLO); - dev->id.revision |= (idhi & SSB_IDHIGH_RCHI) >> SSB_IDHIGH_RCHI_SHIFT; - dev->id.vendor = (idhi & SSB_IDHIGH_VC) >> SSB_IDHIGH_VC_SHIFT; - dev->core_index = i; - dev->bus = bus; - dev->ops = bus->ops; - - ssb_dprintk(KERN_INFO PFX - "Core %d found: %s " - "(cc 0x%03X, rev 0x%02X, vendor 0x%04X)\n", - i, ssb_core_name(dev->id.coreid), - dev->id.coreid, dev->id.revision, dev->id.vendor); - - switch (dev->id.coreid) { - case SSB_DEV_80211: - nr_80211_cores++; - if (nr_80211_cores > 1) { - if (!we_support_multiple_80211_cores(bus)) { - ssb_dprintk(KERN_INFO PFX "Ignoring additional " - "802.11 core\n"); - continue; - } - } - break; - case SSB_DEV_EXTIF: -#ifdef CONFIG_SSB_DRIVER_EXTIF - if (bus->extif.dev) { - ssb_printk(KERN_WARNING PFX - "WARNING: Multiple EXTIFs found\n"); - break; - } - bus->extif.dev = dev; -#endif /* CONFIG_SSB_DRIVER_EXTIF */ - break; - case SSB_DEV_CHIPCOMMON: - if (bus->chipco.dev) { - ssb_printk(KERN_WARNING PFX - "WARNING: Multiple ChipCommon found\n"); - break; - } - bus->chipco.dev = dev; - break; - case SSB_DEV_MIPS: - case SSB_DEV_MIPS_3302: -#ifdef CONFIG_SSB_DRIVER_MIPS - if (bus->mipscore.dev) { - ssb_printk(KERN_WARNING PFX - "WARNING: Multiple MIPS cores found\n"); - break; - } - bus->mipscore.dev = dev; -#endif /* CONFIG_SSB_DRIVER_MIPS */ - break; - case SSB_DEV_PCI: - case SSB_DEV_PCIE: -#ifdef CONFIG_SSB_DRIVER_PCICORE - if (bus->bustype == SSB_BUSTYPE_PCI) { - /* Ignore PCI cores on PCI-E cards. - * Ignore PCI-E cores on PCI cards. */ - if (dev->id.coreid == SSB_DEV_PCI) { - if (bus->host_pci->is_pcie) - continue; - } else { - if (!bus->host_pci->is_pcie) - continue; - } - } - if (bus->pcicore.dev) { - ssb_printk(KERN_WARNING PFX - "WARNING: Multiple PCI(E) cores found\n"); - break; - } - bus->pcicore.dev = dev; -#endif /* CONFIG_SSB_DRIVER_PCICORE */ - break; - default: - break; - } - - dev_i++; - } - bus->nr_devices = dev_i; - - err = 0; -out: - return err; -err_unmap: - ssb_iounmap(bus); - goto out; -} diff --git a/target/linux/generic-2.6/files/drivers/ssb/ssb_private.h b/target/linux/generic-2.6/files/drivers/ssb/ssb_private.h deleted file mode 100644 index a789364264..0000000000 --- a/target/linux/generic-2.6/files/drivers/ssb/ssb_private.h +++ /dev/null @@ -1,136 +0,0 @@ -#ifndef LINUX_SSB_PRIVATE_H_ -#define LINUX_SSB_PRIVATE_H_ - -#include <linux/ssb/ssb.h> -#include <linux/types.h> - - -#define PFX "ssb: " - -#ifdef CONFIG_SSB_SILENT -# define ssb_printk(fmt, x...) do { /* nothing */ } while (0) -#else -# define ssb_printk printk -#endif /* CONFIG_SSB_SILENT */ - -/* dprintk: Debugging printk; vanishes for non-debug compilation */ -#ifdef CONFIG_SSB_DEBUG -# define ssb_dprintk(fmt, x...) ssb_printk(fmt , ##x) -#else -# define ssb_dprintk(fmt, x...) do { /* nothing */ } while (0) -#endif - -#ifdef CONFIG_SSB_DEBUG -# define SSB_WARN_ON(x) WARN_ON(x) -# define SSB_BUG_ON(x) BUG_ON(x) -#else -static inline int __ssb_do_nothing(int x) { return x; } -# define SSB_WARN_ON(x) __ssb_do_nothing(unlikely(!!(x))) -# define SSB_BUG_ON(x) __ssb_do_nothing(unlikely(!!(x))) -#endif - - -/* pci.c */ -#ifdef CONFIG_SSB_PCIHOST -extern int ssb_pci_switch_core(struct ssb_bus *bus, - struct ssb_device *dev); -extern int ssb_pci_switch_coreidx(struct ssb_bus *bus, - u8 coreidx); -extern int ssb_pci_xtal(struct ssb_bus *bus, u32 what, - int turn_on); -extern int ssb_pci_get_invariants(struct ssb_bus *bus, - struct ssb_init_invariants *iv); -extern void ssb_pci_exit(struct ssb_bus *bus); -extern int ssb_pci_init(struct ssb_bus *bus); -extern const struct ssb_bus_ops ssb_pci_ops; - -#else /* CONFIG_SSB_PCIHOST */ - -static inline int ssb_pci_switch_core(struct ssb_bus *bus, - struct ssb_device *dev) -{ - return 0; -} -static inline int ssb_pci_switch_coreidx(struct ssb_bus *bus, - u8 coreidx) -{ - return 0; -} -static inline int ssb_pci_xtal(struct ssb_bus *bus, u32 what, - int turn_on) -{ - return 0; -} -static inline void ssb_pci_exit(struct ssb_bus *bus) -{ -} -static inline int ssb_pci_init(struct ssb_bus *bus) -{ - return 0; -} -#endif /* CONFIG_SSB_PCIHOST */ - - -/* pcmcia.c */ -#ifdef CONFIG_SSB_PCMCIAHOST -extern int ssb_pcmcia_switch_core(struct ssb_bus *bus, - struct ssb_device *dev); -extern int ssb_pcmcia_switch_coreidx(struct ssb_bus *bus, - u8 coreidx); -extern int ssb_pcmcia_switch_segment(struct ssb_bus *bus, - u8 seg); -extern int ssb_pcmcia_get_invariants(struct ssb_bus *bus, - struct ssb_init_invariants *iv); -extern int ssb_pcmcia_init(struct ssb_bus *bus); -extern const struct ssb_bus_ops ssb_pcmcia_ops; -#else /* CONFIG_SSB_PCMCIAHOST */ -static inline int ssb_pcmcia_switch_core(struct ssb_bus *bus, - struct ssb_device *dev) -{ - return 0; -} -static inline int ssb_pcmcia_switch_coreidx(struct ssb_bus *bus, - u8 coreidx) -{ - return 0; -} -static inline int ssb_pcmcia_switch_segment(struct ssb_bus *bus, - u8 seg) -{ - return 0; -} -static inline int ssb_pcmcia_init(struct ssb_bus *bus) -{ - return 0; -} -#endif /* CONFIG_SSB_PCMCIAHOST */ - - -/* scan.c */ -extern const char *ssb_core_name(u16 coreid); -extern int ssb_bus_scan(struct ssb_bus *bus, - unsigned long baseaddr); -extern void ssb_iounmap(struct ssb_bus *ssb); - - -/* core.c */ -extern u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m); -extern int ssb_devices_freeze(struct ssb_bus *bus); -extern int ssb_devices_thaw(struct ssb_bus *bus); -extern struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev); - -/* b43_pci_bridge.c */ -#ifdef CONFIG_SSB_PCIHOST -extern int __init b43_pci_ssb_bridge_init(void); -extern void __exit b43_pci_ssb_bridge_exit(void); -#else /* CONFIG_SSB_PCIHOST */ -static inline int b43_pci_ssb_bridge_init(void) -{ - return 0; -} -static inline void b43_pci_ssb_bridge_exit(void) -{ -} -#endif /* CONFIG_SSB_PCIHOST */ - -#endif /* LINUX_SSB_PRIVATE_H_ */ |