aboutsummaryrefslogtreecommitdiffstats
path: root/target/linux/brcm63xx/patches-2.6.37/001-6345_cpu.patch
diff options
context:
space:
mode:
Diffstat (limited to 'target/linux/brcm63xx/patches-2.6.37/001-6345_cpu.patch')
-rw-r--r--target/linux/brcm63xx/patches-2.6.37/001-6345_cpu.patch74
1 files changed, 74 insertions, 0 deletions
diff --git a/target/linux/brcm63xx/patches-2.6.37/001-6345_cpu.patch b/target/linux/brcm63xx/patches-2.6.37/001-6345_cpu.patch
new file mode 100644
index 0000000000..16751e508b
--- /dev/null
+++ b/target/linux/brcm63xx/patches-2.6.37/001-6345_cpu.patch
@@ -0,0 +1,74 @@
+--- a/arch/mips/bcm63xx/cpu.c
++++ b/arch/mips/bcm63xx/cpu.c
+@@ -260,8 +260,10 @@ static unsigned int detect_memory_size(v
+ unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
+ u32 val;
+
+- if (BCMCPU_IS_6345())
+- return (8 * 1024 * 1024);
++ if (BCMCPU_IS_6345()) {
++ val = bcm_sdram_readl(SDRAM_MBASE_REG);
++ return (val * 8 * 1024 * 1024);
++ }
+
+ if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) {
+ val = bcm_sdram_readl(SDRAM_CFG_REG);
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+@@ -735,6 +735,8 @@
+ #define SDRAM_CFG_BANK_SHIFT 13
+ #define SDRAM_CFG_BANK_MASK (1 << SDRAM_CFG_BANK_SHIFT)
+
++#define SDRAM_MBASE_REG 0xc
++
+ #define SDRAM_PRIO_REG 0x2C
+ #define SDRAM_PRIO_MIPS_SHIFT 29
+ #define SDRAM_PRIO_MIPS_MASK (1 << SDRAM_PRIO_MIPS_SHIFT)
+--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
+@@ -698,15 +698,9 @@ void __init board_prom_init(void)
+ char cfe_version[32];
+ u32 val;
+
+- /* read base address of boot chip select (0)
+- * 6345 does not have MPI but boots from standard
+- * MIPS Flash address */
+- if (BCMCPU_IS_6345())
+- val = 0x1fc00000;
+- else {
+- val = bcm_mpi_readl(MPI_CSBASE_REG(0));
+- val &= MPI_CSBASE_BASE_MASK;
+- }
++ /* read base address of boot chip select (0) */
++ val = bcm_mpi_readl(MPI_CSBASE_REG(0));
++ val &= MPI_CSBASE_BASE_MASK;
+ boot_addr = (u8 *)KSEG1ADDR(val);
+
+ /* dump cfe version */
+@@ -881,12 +875,9 @@ int __init board_register_devices(void)
+ bcm63xx_dsp_register(&board.dsp);
+
+ /* read base address of boot chip select (0) */
+- if (BCMCPU_IS_6345())
+- val = 0x1fc00000;
+- else {
+- val = bcm_mpi_readl(MPI_CSBASE_REG(0));
+- val &= MPI_CSBASE_BASE_MASK;
+- }
++ val = bcm_mpi_readl(MPI_CSBASE_REG(0));
++ val &= MPI_CSBASE_BASE_MASK;
++
+ mtd_resources[0].start = val;
+ mtd_resources[0].end = 0x1FFFFFFF;
+
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+@@ -163,7 +163,7 @@ enum bcm63xx_regs_set {
+ #define BCM_6345_ENET0_BASE (0xfffe1800)
+ #define BCM_6345_ENETDMA_BASE (0xfffe2800)
+ #define BCM_6345_PCMCIA_BASE (0xfffe2028)
+-#define BCM_6345_MPI_BASE (0xdeadbeef)
++#define BCM_6345_MPI_BASE (0xfffe2000)
+ #define BCM_6345_OHCI0_BASE (0xfffe2100)
+ #define BCM_6345_OHCI_PRIV_BASE (0xfffe2200)
+ #define BCM_6345_USBH_PRIV_BASE (0xdeadbeef)