diff options
Diffstat (limited to 'target/linux/brcm2708/patches-4.4/0584-clk-bcm2835-Don-t-rate-change-PLLs-on-behalf-of-DSI-.patch')
| -rw-r--r-- | target/linux/brcm2708/patches-4.4/0584-clk-bcm2835-Don-t-rate-change-PLLs-on-behalf-of-DSI-.patch | 177 |
1 files changed, 177 insertions, 0 deletions
diff --git a/target/linux/brcm2708/patches-4.4/0584-clk-bcm2835-Don-t-rate-change-PLLs-on-behalf-of-DSI-.patch b/target/linux/brcm2708/patches-4.4/0584-clk-bcm2835-Don-t-rate-change-PLLs-on-behalf-of-DSI-.patch new file mode 100644 index 0000000000..94f4be61a1 --- /dev/null +++ b/target/linux/brcm2708/patches-4.4/0584-clk-bcm2835-Don-t-rate-change-PLLs-on-behalf-of-DSI-.patch @@ -0,0 +1,177 @@ +From c08886564938df6796a7d98495cf5cc3f7a09337 Mon Sep 17 00:00:00 2001 +From: Eric Anholt <eric@anholt.net> +Date: Wed, 18 Jan 2017 07:31:55 +1100 +Subject: [PATCH] clk: bcm2835: Don't rate change PLLs on behalf of DSI PLL + dividers (v2). + +Our core PLLs are intended to be configured once and left alone. With +the SET_RATE_PARENT, asking to set the PLLD_DSI1 clock rate would +change PLLD just to get closer to the requested DSI clock, thus +changing PLLD_PER, the UART and ethernet PHY clock rates downstream of +it, and breaking ethernet. + +We *do* want PLLH to change so that PLLH_AUX can be exactly the value +we want, though. Thus, we need to have a per-divider policy of +whether to pass rate changes up. + +Signed-off-by: Eric Anholt <eric@anholt.net> +Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> +(cherry picked from commit 55486091bd1e1c5ed28c43c0d6b3392468a9adb5) +--- + drivers/clk/bcm/clk-bcm2835.c | 42 ++++++++++++++++++++++++++++-------------- + 1 file changed, 28 insertions(+), 14 deletions(-) + +diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c +index 89dad97..54cb4e1 100644 +--- a/drivers/clk/bcm/clk-bcm2835.c ++++ b/drivers/clk/bcm/clk-bcm2835.c +@@ -449,6 +449,7 @@ struct bcm2835_pll_divider_data { + u32 load_mask; + u32 hold_mask; + u32 fixed_divider; ++ u32 flags; + }; + + struct bcm2835_clock_data { +@@ -1286,7 +1287,7 @@ bcm2835_register_pll_divider(struct bcm2835_cprman *cprman, + init.num_parents = 1; + init.name = divider_name; + init.ops = &bcm2835_pll_divider_clk_ops; +- init.flags = CLK_IGNORE_UNUSED; ++ init.flags = data->flags | CLK_IGNORE_UNUSED; + + divider = devm_kzalloc(cprman->dev, sizeof(*divider), GFP_KERNEL); + if (!divider) +@@ -1525,7 +1526,8 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { + .a2w_reg = A2W_PLLA_CORE, + .load_mask = CM_PLLA_LOADCORE, + .hold_mask = CM_PLLA_HOLDCORE, +- .fixed_divider = 1), ++ .fixed_divider = 1, ++ .flags = CLK_SET_RATE_PARENT), + [BCM2835_PLLA_PER] = REGISTER_PLL_DIV( + .name = "plla_per", + .source_pll = "plla", +@@ -1533,7 +1535,8 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { + .a2w_reg = A2W_PLLA_PER, + .load_mask = CM_PLLA_LOADPER, + .hold_mask = CM_PLLA_HOLDPER, +- .fixed_divider = 1), ++ .fixed_divider = 1, ++ .flags = CLK_SET_RATE_PARENT), + [BCM2835_PLLA_DSI0] = REGISTER_PLL_DIV( + .name = "plla_dsi0", + .source_pll = "plla", +@@ -1549,7 +1552,8 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { + .a2w_reg = A2W_PLLA_CCP2, + .load_mask = CM_PLLA_LOADCCP2, + .hold_mask = CM_PLLA_HOLDCCP2, +- .fixed_divider = 1), ++ .fixed_divider = 1, ++ .flags = CLK_SET_RATE_PARENT), + + /* PLLB is used for the ARM's clock. */ + [BCM2835_PLLB] = REGISTER_PLL( +@@ -1573,7 +1577,8 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { + .a2w_reg = A2W_PLLB_ARM, + .load_mask = CM_PLLB_LOADARM, + .hold_mask = CM_PLLB_HOLDARM, +- .fixed_divider = 1), ++ .fixed_divider = 1, ++ .flags = CLK_SET_RATE_PARENT), + + /* + * PLLC is the core PLL, used to drive the core VPU clock. +@@ -1602,7 +1607,8 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { + .a2w_reg = A2W_PLLC_CORE0, + .load_mask = CM_PLLC_LOADCORE0, + .hold_mask = CM_PLLC_HOLDCORE0, +- .fixed_divider = 1), ++ .fixed_divider = 1, ++ .flags = CLK_SET_RATE_PARENT), + [BCM2835_PLLC_CORE1] = REGISTER_PLL_DIV( + .name = "pllc_core1", + .source_pll = "pllc", +@@ -1610,7 +1616,8 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { + .a2w_reg = A2W_PLLC_CORE1, + .load_mask = CM_PLLC_LOADCORE1, + .hold_mask = CM_PLLC_HOLDCORE1, +- .fixed_divider = 1), ++ .fixed_divider = 1, ++ .flags = CLK_SET_RATE_PARENT), + [BCM2835_PLLC_CORE2] = REGISTER_PLL_DIV( + .name = "pllc_core2", + .source_pll = "pllc", +@@ -1618,7 +1625,8 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { + .a2w_reg = A2W_PLLC_CORE2, + .load_mask = CM_PLLC_LOADCORE2, + .hold_mask = CM_PLLC_HOLDCORE2, +- .fixed_divider = 1), ++ .fixed_divider = 1, ++ .flags = CLK_SET_RATE_PARENT), + [BCM2835_PLLC_PER] = REGISTER_PLL_DIV( + .name = "pllc_per", + .source_pll = "pllc", +@@ -1626,7 +1634,8 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { + .a2w_reg = A2W_PLLC_PER, + .load_mask = CM_PLLC_LOADPER, + .hold_mask = CM_PLLC_HOLDPER, +- .fixed_divider = 1), ++ .fixed_divider = 1, ++ .flags = CLK_SET_RATE_PARENT), + + /* + * PLLD is the display PLL, used to drive DSI display panels. +@@ -1655,7 +1664,8 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { + .a2w_reg = A2W_PLLD_CORE, + .load_mask = CM_PLLD_LOADCORE, + .hold_mask = CM_PLLD_HOLDCORE, +- .fixed_divider = 1), ++ .fixed_divider = 1, ++ .flags = CLK_SET_RATE_PARENT), + [BCM2835_PLLD_PER] = REGISTER_PLL_DIV( + .name = "plld_per", + .source_pll = "plld", +@@ -1663,7 +1673,8 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { + .a2w_reg = A2W_PLLD_PER, + .load_mask = CM_PLLD_LOADPER, + .hold_mask = CM_PLLD_HOLDPER, +- .fixed_divider = 1), ++ .fixed_divider = 1, ++ .flags = CLK_SET_RATE_PARENT), + [BCM2835_PLLD_DSI0] = REGISTER_PLL_DIV( + .name = "plld_dsi0", + .source_pll = "plld", +@@ -1708,7 +1719,8 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { + .a2w_reg = A2W_PLLH_RCAL, + .load_mask = CM_PLLH_LOADRCAL, + .hold_mask = 0, +- .fixed_divider = 10), ++ .fixed_divider = 10, ++ .flags = CLK_SET_RATE_PARENT), + [BCM2835_PLLH_AUX] = REGISTER_PLL_DIV( + .name = "pllh_aux", + .source_pll = "pllh", +@@ -1716,7 +1728,8 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { + .a2w_reg = A2W_PLLH_AUX, + .load_mask = CM_PLLH_LOADAUX, + .hold_mask = 0, +- .fixed_divider = 1), ++ .fixed_divider = 1, ++ .flags = CLK_SET_RATE_PARENT), + [BCM2835_PLLH_PIX] = REGISTER_PLL_DIV( + .name = "pllh_pix", + .source_pll = "pllh", +@@ -1724,7 +1737,8 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { + .a2w_reg = A2W_PLLH_PIX, + .load_mask = CM_PLLH_LOADPIX, + .hold_mask = 0, +- .fixed_divider = 10), ++ .fixed_divider = 10, ++ .flags = CLK_SET_RATE_PARENT), + + /* the clocks */ + +-- +2.1.4 + |