diff options
Diffstat (limited to 'target/linux/bcm27xx/patches-5.4/950-0556-drm-vc4-crtc-Add-FIFO-depth-to-vc4_crtc_data.patch')
| -rw-r--r-- | target/linux/bcm27xx/patches-5.4/950-0556-drm-vc4-crtc-Add-FIFO-depth-to-vc4_crtc_data.patch | 86 |
1 files changed, 86 insertions, 0 deletions
diff --git a/target/linux/bcm27xx/patches-5.4/950-0556-drm-vc4-crtc-Add-FIFO-depth-to-vc4_crtc_data.patch b/target/linux/bcm27xx/patches-5.4/950-0556-drm-vc4-crtc-Add-FIFO-depth-to-vc4_crtc_data.patch new file mode 100644 index 0000000000..e920a0be64 --- /dev/null +++ b/target/linux/bcm27xx/patches-5.4/950-0556-drm-vc4-crtc-Add-FIFO-depth-to-vc4_crtc_data.patch @@ -0,0 +1,86 @@ +From a294de7c4782f91fe724e4e5b05fd99798d50760 Mon Sep 17 00:00:00 2001 +From: Maxime Ripard <maxime@cerno.tech> +Date: Mon, 13 Jan 2020 13:39:20 +0100 +Subject: [PATCH] drm/vc4: crtc: Add FIFO depth to vc4_crtc_data + +Not all pixelvalve FIFOs in vc5 have the same depth, so we need to add that +to our vc4_crtc_data structure to be able to compute the fill level +properly later on. + +Signed-off-by: Maxime Ripard <maxime@cerno.tech> +--- + drivers/gpu/drm/vc4/vc4_crtc.c | 20 ++++++++++++++++---- + drivers/gpu/drm/vc4/vc4_drv.h | 3 +++ + 2 files changed, 19 insertions(+), 4 deletions(-) + +--- a/drivers/gpu/drm/vc4/vc4_crtc.c ++++ b/drivers/gpu/drm/vc4/vc4_crtc.c +@@ -250,11 +250,20 @@ vc4_crtc_update_gamma_lut(struct drm_crt + vc4_crtc_lut_load(crtc); + } + +- +-static u32 vc4_get_fifo_full_level(u32 format) ++static u32 vc4_get_fifo_full_level(struct vc4_crtc *vc4_crtc, u32 format) + { +- static const u32 fifo_len_bytes = 64; ++ u32 fifo_len_bytes = vc4_crtc->data->fifo_depth; + ++ /* ++ * Pixels are pulled from the HVS if the number of bytes is ++ * lower than the FIFO full level. ++ * ++ * The latency of the pixel fetch mechanism is 6 pixels, so we ++ * need to convert those 6 pixels in bytes, depending on the ++ * format, and then substract that from the length of the FIFO ++ * to make sure we never end up in a situation where the FIFO ++ * is full. ++ */ + switch (format) { + case PV_CONTROL_FORMAT_DSIV_16: + case PV_CONTROL_FORMAT_DSIC_16: +@@ -369,7 +378,7 @@ static void vc4_crtc_config_pv(struct dr + + CRTC_WRITE(PV_CONTROL, + VC4_SET_FIELD(format, PV_CONTROL_FORMAT) | +- VC4_SET_FIELD(vc4_get_fifo_full_level(format), ++ VC4_SET_FIELD(vc4_get_fifo_full_level(vc4_crtc, format), + PV_CONTROL_FIFO_LEVEL) | + VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) | + PV_CONTROL_CLR_AT_START | +@@ -1067,6 +1076,7 @@ static const struct vc4_crtc_data bcm283 + .hvs_available_channels = BIT(0), + .hvs_output = 0, + .debugfs_name = "crtc0_regs", ++ .fifo_depth = 64, + .pixels_per_clock = 1, + .encoder_types = { + [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0, +@@ -1078,6 +1088,7 @@ static const struct vc4_crtc_data bcm283 + .hvs_available_channels = BIT(2), + .hvs_output = 2, + .debugfs_name = "crtc1_regs", ++ .fifo_depth = 64, + .pixels_per_clock = 1, + .encoder_types = { + [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1, +@@ -1089,6 +1100,7 @@ static const struct vc4_crtc_data bcm283 + .hvs_available_channels = BIT(1), + .hvs_output = 1, + .debugfs_name = "crtc2_regs", ++ .fifo_depth = 64, + .pixels_per_clock = 1, + .encoder_types = { + [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI, +--- a/drivers/gpu/drm/vc4/vc4_drv.h ++++ b/drivers/gpu/drm/vc4/vc4_drv.h +@@ -452,6 +452,9 @@ to_vc4_encoder(struct drm_encoder *encod + } + + struct vc4_crtc_data { ++ /* Depth of the PixelValve FIFO in bytes */ ++ unsigned int fifo_depth; ++ + /* Which channels of the HVS can the output source from */ + unsigned int hvs_available_channels; + |