diff options
Diffstat (limited to 'target/linux/ar7-2.6/files/include/asm-mips/ar7/ar7.h')
| -rw-r--r-- | target/linux/ar7-2.6/files/include/asm-mips/ar7/ar7.h | 84 |
1 files changed, 49 insertions, 35 deletions
diff --git a/target/linux/ar7-2.6/files/include/asm-mips/ar7/ar7.h b/target/linux/ar7-2.6/files/include/asm-mips/ar7/ar7.h index fe51a8d67b..a5fa474aff 100644 --- a/target/linux/ar7-2.6/files/include/asm-mips/ar7/ar7.h +++ b/target/linux/ar7-2.6/files/include/asm-mips/ar7/ar7.h @@ -31,12 +31,20 @@ #define AR7_REGS_GPIO (AR7_REGS_BASE + 0x0900) #define AR7_REGS_POWER (AR7_REGS_BASE + 0x0a00) #define AR7_REGS_WDT (AR7_REGS_BASE + 0x0b00) +#define AR7_REGS_TIMER0 (AR7_REGS_BASE + 0x0c00) +#define AR7_REGS_TIMER1 (AR7_REGS_BASE + 0x0d00) #define AR7_REGS_UART0 (AR7_REGS_BASE + 0x0e00) #define AR7_REGS_UART1 (AR7_REGS_BASE + 0x0f00) +#define AR7_REGS_I2C (AR7_REGS_BASE + 0x1000) +#define AR7_REGS_USB (AR7_REGS_BASE + 0x1200) +#define AR7_REGS_DMA (AR7_REGS_BASE + 0x1400) #define AR7_REGS_RESET (AR7_REGS_BASE + 0x1600) +#define AR7_REGS_BIST (AR7_REGS_BASE + 0x1700) #define AR7_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1800) +#define AR7_REGS_DCL (AR7_REGS_BASE + 0x1A00) #define AR7_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1C00) #define AR7_REGS_MDIO (AR7_REGS_BASE + 0x1E00) +#define AR7_REGS_FSER (AR7_REGS_BASE + 0x2000) #define AR7_REGS_IRQ (AR7_REGS_BASE + 0x2400) #define AR7_REGS_MAC1 (AR7_REGS_BASE + 0x2800) @@ -54,6 +62,9 @@ #define AR7_GPIO_BIT_STATUS_LED 8 +#define AR7_CHIP_7100 0x18 +#define AR7_CHIP_7200 0x2b +#define AR7_CHIP_7300 0x05 /* Interrupts */ #define AR7_IRQ_UART0 15 @@ -66,49 +77,52 @@ struct plat_cpmac_data { char dev_addr[6]; }; +struct plat_dsl_data { + int reset_bit_dsl; + int reset_bit_sar; +}; + extern char *prom_getenv(char *envname); -/* A bunch of small bit-toggling functions */ -static inline u32 get_chip_id(void) +extern int ar7_cpu_clock, ar7_bus_clock, ar7_dsp_clock; + +static inline u16 ar7_chip_id(void) { - return *((u16 *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)); + return readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) & 0xffff; +} + +static inline u8 ar7_chip_rev(void) +{ + return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) >> 16) & 0xff; } static inline int ar7_cpu_freq(void) { - u16 chip_id = get_chip_id(); - switch (chip_id) { - case 0x5: - return 150000000; - case 0x18: - case 0x2b: - return 211968000; - default: - return 150000000; - } + return ar7_cpu_clock; } static inline int ar7_bus_freq(void) { - u16 chip_id = get_chip_id(); - switch (chip_id) { - case 0x5: - return 125000000; - case 0x18: - case 0x2b: - return 105984000; - default: - return 125000000; - } + return ar7_bus_clock; +} + +static inline int ar7_vbus_freq(void) +{ + return ar7_bus_clock / 2; +} +#define ar7_cpmac_freq ar7_vbus_freq + +static inline int ar7_dsp_freq(void) +{ + return ar7_dsp_clock; } -#define ar7_cpmac_freq ar7_bus_freq static inline int ar7_has_high_cpmac(void) { - u16 chip_id = get_chip_id(); + u16 chip_id = ar7_chip_id(); switch (chip_id) { - case 0x18: - case 0x2b: + case AR7_CHIP_7100: + case AR7_CHIP_7200: return 0; default: return 1; @@ -118,15 +132,15 @@ static inline int ar7_has_high_cpmac(void) static inline void ar7_device_enable(u32 bit) { - volatile u32 *reset_reg = (u32 *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PEREPHERIAL); - *reset_reg |= (1 << bit); + void *reset_reg = (void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PEREPHERIAL); + writel(readl(reset_reg) | (1 << bit), reset_reg); mdelay(20); } static inline void ar7_device_disable(u32 bit) { - volatile u32 *reset_reg = (u32 *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PEREPHERIAL); - *reset_reg &= ~(1 << bit); + void *reset_reg = (void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PEREPHERIAL); + writel(readl(reset_reg) & ~(1 << bit), reset_reg); mdelay(20); } @@ -138,15 +152,15 @@ static inline void ar7_device_reset(u32 bit) static inline void ar7_device_on(u32 bit) { - volatile u32 *power_reg = (u32 *)KSEG1ADDR(AR7_REGS_POWER); - *power_reg |= (1 << bit); + void *power_reg = (void *)KSEG1ADDR(AR7_REGS_POWER); + writel(readl(power_reg) | (1 << bit), power_reg); mdelay(20); } static inline void ar7_device_off(u32 bit) { - volatile u32 *power_reg = (u32 *)KSEG1ADDR(AR7_REGS_POWER); - *power_reg &= ~(1 << bit); + void *power_reg = (void *)KSEG1ADDR(AR7_REGS_POWER); + writel(readl(power_reg) & ~(1 << bit), power_reg); mdelay(20); } |