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-rw-r--r--target/linux/apm821xx/patches-4.4/300-fix-atheros-nics-on-apm82181.patch51
1 files changed, 51 insertions, 0 deletions
diff --git a/target/linux/apm821xx/patches-4.4/300-fix-atheros-nics-on-apm82181.patch b/target/linux/apm821xx/patches-4.4/300-fix-atheros-nics-on-apm82181.patch
new file mode 100644
index 0000000000..b9e5fb07c6
--- /dev/null
+++ b/target/linux/apm821xx/patches-4.4/300-fix-atheros-nics-on-apm82181.patch
@@ -0,0 +1,51 @@
+--- a/arch/powerpc/sysdev/ppc4xx_pci.c 2016-05-30 17:23:34.543707092 +0200
++++ b/arch/powerpc/sysdev/ppc4xx_pci.c 2016-05-30 17:31:02.497707885 +0200
+@@ -1066,15 +1066,24 @@ static int __init apm821xx_pciex_init_po
+ u32 val;
+
+ /*
+- * Do a software reset on PCIe ports.
+- * This code is to fix the issue that pci drivers doesn't re-assign
+- * bus number for PCIE devices after Uboot
+- * scanned and configured all the buses (eg. PCIE NIC IntelPro/1000
+- * PT quad port, SAS LSI 1064E)
++ * Only reset the PHY when no link is currently established.
++ * This is for the Atheros PCIe board which has problems to establish
++ * the link (again) after this PHY reset. All other currently tested
++ * PCIe boards don't show this problem.
+ */
+-
+- mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x0);
+- mdelay(10);
++ val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP);
++ if (!(val & 0x00001000)) {
++ /*
++ * Do a software reset on PCIe ports.
++ * This code is to fix the issue that pci drivers doesn't re-assign
++ * bus number for PCIE devices after Uboot
++ * scanned and configured all the buses (eg. PCIE NIC IntelPro/1000
++ * PT quad port, SAS LSI 1064E)
++ */
++
++ mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x0);
++ mdelay(10);
++ }
+
+ if (port->endpoint)
+ val = PTYPE_LEGACY_ENDPOINT << 20;
+@@ -1091,9 +1100,12 @@ static int __init apm821xx_pciex_init_po
+ mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000130);
+ mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006);
+
+- mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x10000000);
+- mdelay(50);
+- mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x30000000);
++ val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP);
++ if (!(val & 0x00001000)) {
++ mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x10000000);
++ mdelay(50);
++ mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x30000000);
++ }
+
+ mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
+ mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) |