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-rw-r--r--package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/clock.h84
-rw-r--r--package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/cpu.h26
-rw-r--r--package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/hardware.h30
-rw-r--r--package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/pinmux.h46
-rw-r--r--package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/spl.h6
-rw-r--r--package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/sysctl.h125
-rw-r--r--package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/timer.h23
7 files changed, 340 insertions, 0 deletions
diff --git a/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/clock.h b/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/clock.h
new file mode 100644
index 0000000000..da7dd1c063
--- /dev/null
+++ b/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/clock.h
@@ -0,0 +1,84 @@
+#ifndef _NAS782X_CLOCK_H
+#define _NAS782X_CLOCK_H
+
+#include <asm/arch/sysctl.h>
+#include <asm/arch/cpu.h>
+
+/* bit numbers of clock control register */
+#define SYS_CTRL_CLK_COPRO 0
+#define SYS_CTRL_CLK_DMA 1
+#define SYS_CTRL_CLK_CIPHER 2
+#define SYS_CTRL_CLK_SD 3
+#define SYS_CTRL_CLK_SATA 4
+#define SYS_CTRL_CLK_I2S 5
+#define SYS_CTRL_CLK_USBHS 6
+#define SYS_CTRL_CLK_MACA 7
+#define SYS_CTRL_CLK_MAC SYS_CTRL_CLK_MACA
+#define SYS_CTRL_CLK_PCIEA 8
+#define SYS_CTRL_CLK_STATIC 9
+#define SYS_CTRL_CLK_MACB 10
+#define SYS_CTRL_CLK_PCIEB 11
+#define SYS_CTRL_CLK_REF600 12
+#define SYS_CTRL_CLK_USBDEV 13
+#define SYS_CTRL_CLK_DDR 14
+#define SYS_CTRL_CLK_DDRPHY 15
+#define SYS_CTRL_CLK_DDRCK 16
+
+/* bit numbers of reset control register */
+#define SYS_CTRL_RST_SCU 0
+#define SYS_CTRL_RST_COPRO 1
+#define SYS_CTRL_RST_ARM0 2
+#define SYS_CTRL_RST_ARM1 3
+#define SYS_CTRL_RST_USBHS 4
+#define SYS_CTRL_RST_USBHSPHYA 5
+#define SYS_CTRL_RST_MACA 6
+#define SYS_CTRL_RST_MAC SYS_CTRL_RST_MACA
+#define SYS_CTRL_RST_PCIEA 7
+#define SYS_CTRL_RST_SGDMA 8
+#define SYS_CTRL_RST_CIPHER 9
+#define SYS_CTRL_RST_DDR 10
+#define SYS_CTRL_RST_SATA 11
+#define SYS_CTRL_RST_SATA_LINK 12
+#define SYS_CTRL_RST_SATA_PHY 13
+#define SYS_CTRL_RST_PCIEPHY 14
+#define SYS_CTRL_RST_STATIC 15
+#define SYS_CTRL_RST_GPIO 16
+#define SYS_CTRL_RST_UART1 17
+#define SYS_CTRL_RST_UART2 18
+#define SYS_CTRL_RST_MISC 19
+#define SYS_CTRL_RST_I2S 20
+#define SYS_CTRL_RST_SD 21
+#define SYS_CTRL_RST_MACB 22
+#define SYS_CTRL_RST_PCIEB 23
+#define SYS_CTRL_RST_VIDEO 24
+#define SYS_CTRL_RST_DDR_PHY 25
+#define SYS_CTRL_RST_USBHSPHYB 26
+#define SYS_CTRL_RST_USBDEV 27
+#define SYS_CTRL_RST_ARMDBG 29
+#define SYS_CTRL_RST_PLLA 30
+#define SYS_CTRL_RST_PLLB 31
+
+static inline void reset_block(int block, int reset)
+{
+ u32 reg;
+ if (reset)
+ reg = SYS_CTRL_RST_SET_CTRL;
+ else
+ reg = SYS_CTRL_RST_CLR_CTRL;
+
+ writel(BIT(block), reg);
+}
+
+static inline void enable_clock(int block)
+{
+ writel(BIT(block), SYS_CTRL_CLK_SET_CTRL);
+}
+
+static inline void disable_clock(int block)
+{
+ writel(BIT(block), SYS_CTRL_CLK_CLR_CTRL);
+}
+
+int plla_set_config(int idx);
+
+#endif /* _NAS782X_CLOCK_H */
diff --git a/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/cpu.h b/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/cpu.h
new file mode 100644
index 0000000000..11e803c5c0
--- /dev/null
+++ b/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/cpu.h
@@ -0,0 +1,26 @@
+#ifndef _NAS782X_CPU_H
+#define _NAS782X_CPU_H
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+#include <asm/io.h>
+#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/timer.h>
+
+#ifndef __KERNEL_STRICT_NAMES
+#ifndef __ASSEMBLY__
+
+#define BIT(x) (1 << (x))
+
+/* fix "implicit declaration of function" warnning */
+void *memalign(size_t alignment, size_t bytes);
+void free(void* mem);
+void *malloc(size_t bytes);
+void *calloc(size_t n, size_t elem_size);
+
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
+
+#endif /* _NAS782X_CPU_H */
diff --git a/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/hardware.h b/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/hardware.h
new file mode 100644
index 0000000000..f26b17f062
--- /dev/null
+++ b/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/hardware.h
@@ -0,0 +1,30 @@
+#ifndef _NAS782X_HARDWARE_H
+#define _NAS782X_HARDWARE_H
+
+/* Core addresses */
+#define USB_HOST_BASE 0x40200000
+#define MACA_BASE 0x40400000
+#define MACB_BASE 0x40800000
+#define MAC_BASE MACA_BASE
+#define STATIC_CS0_BASE 0x41000000
+#define STATIC_CS1_BASE 0x41400000
+#define STATIC_CONTROL_BASE 0x41C00000
+#define SATA_DATA_BASE 0x42000000 /* non-functional, DMA just needs an address */
+#define GPIO_1_BASE 0x44000000
+#define GPIO_2_BASE 0x44100000
+#define UART_1_BASE 0x44200000
+#define UART_2_BASE 0x44300000
+#define SYS_CONTROL_BASE 0x44e00000
+#define SEC_CONTROL_BASE 0x44f00000
+#define RPSA_BASE 0x44400000
+#define RPSC_BASE 0x44500000
+#define DDR_BASE 0x44700000
+
+#define SATA_BASE 0x45900000
+#define SATA_0_REGS_BASE 0x45900000
+#define SATA_1_REGS_BASE 0x45910000
+#define SATA_DMA_REGS_BASE 0x459a0000
+#define SATA_SGDMA_REGS_BASE 0x459b0000
+#define SATA_HOST_REGS_BASE 0x459e0000
+
+#endif /* _NAS782X_HARDWARE_H */
diff --git a/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/pinmux.h b/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/pinmux.h
new file mode 100644
index 0000000000..810ba5cbab
--- /dev/null
+++ b/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/pinmux.h
@@ -0,0 +1,46 @@
+#ifndef _NAS782X_PINMUX_H
+#define _NAS782X_PINMUX_H
+
+#include <asm/arch/cpu.h>
+
+#define PINMUX_GPIO 0
+#define PINMUX_2 1
+#define PINMUX_3 2
+#define PINMUX_4 3
+#define PINMUX_DEBUG 4
+#define PINMUX_ALT 5
+
+#define PINMUX_BANK_MFA 0
+#define PINMUX_BANK_MFB 1
+
+/* System control multi-function pin function selection */
+#define PINMUX_SECONDARY_SEL 0x14
+#define PINMUX_TERTIARY_SEL 0x8c
+#define PINMUX_QUATERNARY_SEL 0x94
+#define PINMUX_DEBUG_SEL 0x9c
+#define PINMUX_ALTERNATIVE_SEL 0xa4
+#define PINMUX_PULLUP_SEL 0xac
+
+#define PINMUX_UARTA_SIN PINMUX_ALT
+#define PINMUX_UARTA_SOUT PINMUX_ALT
+
+#define PINMUX_STATIC_DATA0 PINMUX_2
+#define PINMUX_STATIC_DATA1 PINMUX_2
+#define PINMUX_STATIC_DATA2 PINMUX_2
+#define PINMUX_STATIC_DATA3 PINMUX_2
+#define PINMUX_STATIC_DATA4 PINMUX_2
+#define PINMUX_STATIC_DATA5 PINMUX_2
+#define PINMUX_STATIC_DATA6 PINMUX_2
+#define PINMUX_STATIC_DATA7 PINMUX_2
+#define PINMUX_STATIC_NWE PINMUX_2
+#define PINMUX_STATIC_NOE PINMUX_2
+#define PINMUX_STATIC_NCS PINMUX_2
+#define PINMUX_STATIC_ADDR18 PINMUX_2
+#define PINMUX_STATIC_ADDR19 PINMUX_2
+
+#define PINMUX_MACA_MDC PINMUX_2
+#define PINMUX_MACA_MDIO PINMUX_2
+
+extern void pinmux_set(int bank, int pin, int func);
+
+#endif /* _NAS782X_PINMUX_H */
diff --git a/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/spl.h b/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/spl.h
new file mode 100644
index 0000000000..f73afdab4f
--- /dev/null
+++ b/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/spl.h
@@ -0,0 +1,6 @@
+#ifndef _NAS782X_SPL_H
+#define _NAS782X_SPL_H
+
+#include <asm/arch/cpu.h>
+
+#endif /* _NAS782X_SPL_H */
diff --git a/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/sysctl.h b/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/sysctl.h
new file mode 100644
index 0000000000..3867e45f92
--- /dev/null
+++ b/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/sysctl.h
@@ -0,0 +1,125 @@
+#ifndef _NAS782X_SYSCTL_H
+#define _NAS782X_SYSCTL_H
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
+
+#include <asm/arch/hardware.h>
+
+/**
+ * System block reset and clock control
+ */
+#define SYS_CTRL_PCI_STAT (SYS_CONTROL_BASE + 0x20)
+#define SYS_CTRL_CLK_SET_CTRL (SYS_CONTROL_BASE + 0x2C)
+#define SYS_CTRL_CLK_CLR_CTRL (SYS_CONTROL_BASE + 0x30)
+#define SYS_CTRL_RST_SET_CTRL (SYS_CONTROL_BASE + 0x34)
+#define SYS_CTRL_RST_CLR_CTRL (SYS_CONTROL_BASE + 0x38)
+#define SYS_CTRL_PLLSYS_CTRL (SYS_CONTROL_BASE + 0x48)
+#define SYS_CTRL_PLLSYS_KEY_CTRL (SYS_CONTROL_BASE + 0x6C)
+#define SYS_CTRL_GMAC_CTRL (SYS_CONTROL_BASE + 0x78)
+
+/* Scratch registers */
+#define SYS_CTRL_SCRATCHWORD0 (SYS_CONTROL_BASE + 0xc4)
+#define SYS_CTRL_SCRATCHWORD1 (SYS_CONTROL_BASE + 0xc8)
+#define SYS_CTRL_SCRATCHWORD2 (SYS_CONTROL_BASE + 0xcc)
+#define SYS_CTRL_SCRATCHWORD3 (SYS_CONTROL_BASE + 0xd0)
+
+#define SYS_CTRL_PLLA_CTRL0 (SYS_CONTROL_BASE + 0x1F0)
+#define SYS_CTRL_PLLA_CTRL1 (SYS_CONTROL_BASE + 0x1F4)
+#define SYS_CTRL_PLLA_CTRL2 (SYS_CONTROL_BASE + 0x1F8)
+#define SYS_CTRL_PLLA_CTRL3 (SYS_CONTROL_BASE + 0x1FC)
+
+#define SYS_CTRL_GMAC_AUTOSPEED 3
+#define SYS_CTRL_GMAC_RGMII 2
+#define SYS_CTRL_GMAC_SIMPLE_MUX 1
+#define SYS_CTRL_GMAC_CKEN_GTX 0
+
+#define SYS_CTRL_CKCTRL_CTRL_ADDR (SYS_CONTROL_BASE + 0x64)
+
+#define SYS_CTRL_CKCTRL_PCI_DIV_BIT 0
+#define SYS_CTRL_CKCTRL_SLOW_BIT 8
+
+
+#define SYS_CTRL_USBHSMPH_CTRL (SYS_CONTROL_BASE + 0x40)
+#define SYS_CTRL_USBHSMPH_STAT (SYS_CONTROL_BASE + 0x44)
+#define SYS_CTRL_REF300_DIV (SYS_CONTROL_BASE + 0xF8)
+#define SYS_CTRL_USBHSPHY_CTRL (SYS_CONTROL_BASE + 0x84)
+#define SYS_CTRL_USB_CTRL (SYS_CONTROL_BASE + 0x90)
+
+/* System control multi-function pin function selection */
+#define SYS_CTRL_SECONDARY_SEL (SYS_CONTROL_BASE + 0x14)
+#define SYS_CTRL_TERTIARY_SEL (SYS_CONTROL_BASE + 0x8c)
+#define SYS_CTRL_QUATERNARY_SEL (SYS_CONTROL_BASE + 0x94)
+#define SYS_CTRL_DEBUG_SEL (SYS_CONTROL_BASE + 0x9c)
+#define SYS_CTRL_ALTERNATIVE_SEL (SYS_CONTROL_BASE + 0xa4)
+#define SYS_CTRL_PULLUP_SEL (SYS_CONTROL_BASE + 0xac)
+
+/* Secure control multi-function pin function selection */
+#define SEC_CTRL_SECONDARY_SEL (SEC_CONTROL_BASE + 0x14)
+#define SEC_CTRL_TERTIARY_SEL (SEC_CONTROL_BASE + 0x8c)
+#define SEC_CTRL_QUATERNARY_SEL (SEC_CONTROL_BASE + 0x94)
+#define SEC_CTRL_DEBUG_SEL (SEC_CONTROL_BASE + 0x9c)
+#define SEC_CTRL_ALTERNATIVE_SEL (SEC_CONTROL_BASE + 0xa4)
+#define SEC_CTRL_PULLUP_SEL (SEC_CONTROL_BASE + 0xac)
+
+#define SEC_CTRL_COPRO_CTRL (SEC_CONTROL_BASE + 0x68)
+#define SEC_CTRL_SECURE_CTRL (SEC_CONTROL_BASE + 0x98)
+#define SEC_CTRL_LEON_DEBUG (SEC_CONTROL_BASE + 0xF0)
+#define SEC_CTRL_PLLB_DIV_CTRL (SEC_CONTROL_BASE + 0xF8)
+#define SEC_CTRL_PLLB_CTRL0 (SEC_CONTROL_BASE + 0x1F0)
+#define SEC_CTRL_PLLB_CTRL1 (SEC_CONTROL_BASE + 0x1F4)
+#define SEC_CTRL_PLLB_CTRL8 (SEC_CONTROL_BASE + 0x1F4)
+
+#define REF300_DIV_INT_SHIFT 8
+#define REF300_DIV_FRAC_SHIFT 0
+#define REF300_DIV_INT(val) ((val) << REF300_DIV_INT_SHIFT)
+#define REF300_DIV_FRAC(val) ((val) << REF300_DIV_FRAC_SHIFT)
+
+#define USBHSPHY_SUSPENDM_MANUAL_ENABLE 16
+#define USBHSPHY_SUSPENDM_MANUAL_STATE 15
+#define USBHSPHY_ATE_ESET 14
+#define USBHSPHY_TEST_DIN 6
+#define USBHSPHY_TEST_ADD 2
+#define USBHSPHY_TEST_DOUT_SEL 1
+#define USBHSPHY_TEST_CLK 0
+
+#define USB_CTRL_USBAPHY_CKSEL_SHIFT 5
+#define USB_CLK_XTAL0_XTAL1 (0 << USB_CTRL_USBAPHY_CKSEL_SHIFT)
+#define USB_CLK_XTAL0 (1 << USB_CTRL_USBAPHY_CKSEL_SHIFT)
+#define USB_CLK_INTERNAL (2 << USB_CTRL_USBAPHY_CKSEL_SHIFT)
+
+#define USBAMUX_DEVICE BIT(4)
+
+#define USBPHY_REFCLKDIV_SHIFT 2
+#define USB_PHY_REF_12MHZ (0 << USBPHY_REFCLKDIV_SHIFT)
+#define USB_PHY_REF_24MHZ (1 << USBPHY_REFCLKDIV_SHIFT)
+#define USB_PHY_REF_48MHZ (2 << USBPHY_REFCLKDIV_SHIFT)
+
+#define USB_CTRL_USB_CKO_SEL_BIT 0
+
+#define USB_INT_CLK_XTAL 0
+#define USB_INT_CLK_REF300 2
+#define USB_INT_CLK_PLLB 3
+
+#define SYS_CTRL_GMAC_AUTOSPEED 3
+#define SYS_CTRL_GMAC_RGMII 2
+#define SYS_CTRL_GMAC_SIMPLE_MUX 1
+#define SYS_CTRL_GMAC_CKEN_GTX 0
+
+
+#define PLLB_ENSAT 3
+#define PLLB_OUTDIV 4
+#define PLLB_REFDIV 8
+#define PLLB_DIV_INT_SHIFT 8
+#define PLLB_DIV_FRAC_SHIFT 0
+#define PLLB_DIV_INT(val) ((val) << PLLB_DIV_INT_SHIFT)
+#define PLLB_DIV_FRAC(val) ((val) << PLLB_DIV_FRAC_SHIFT)
+
+#ifndef __KERNEL_STRICT_NAMES
+#ifndef __ASSEMBLY__
+
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
+
+#endif /* _NAS782X_SYSCTL_H */
diff --git a/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/timer.h b/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/timer.h
new file mode 100644
index 0000000000..ea4d71e164
--- /dev/null
+++ b/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/timer.h
@@ -0,0 +1,23 @@
+#ifndef _NAS782X_TIMER_H
+#define _NAS782X_TIMER_H
+
+#define TIMER1_BASE (RPSA_BASE + 0x200)
+#define TIMER2_BASE (RPSA_BASE + 0x220)
+
+#define TIMER_LOAD 0
+#define TIMER_CURR 4
+#define TIMER_CTRL 8
+#define TIMER_INTR 0x0C
+
+#define TIMER_PRESCALE_SHIFT 2
+#define TIMER_PRESCALE_1 0
+#define TIMER_PRESCALE_16 1
+#define TIMER_PRESCALE_256 2
+#define TIMER_MODE_SHIFT 6
+#define TIMER_MODE_FREE_RUNNING 0
+#define TIMER_MODE_PERIODIC 1
+#define TIMER_ENABLE_SHIFT 7
+#define TIMER_DISABLE 0
+#define TIMER_ENABLE 1
+
+#endif /* _NAS782X_TIMER_H */