1 files changed, 99 insertions, 0 deletions
diff --git a/package/boot/uboot-mediatek/patches/002-0013-pwm-mtk-add-support-for-MediaTek-MT7981-SoC.patch b/package/boot/uboot-mediatek/patches/002-0013-pwm-mtk-add-support-for-MediaTek-MT7981-SoC.patch
new file mode 100644
index 0000000000..2da5b960a3
--- /dev/null
+++ b/package/boot/uboot-mediatek/patches/002-0013-pwm-mtk-add-support-for-MediaTek-MT7981-SoC.patch
@@ -0,0 +1,99 @@
+From 4569ef02981f20b236a8cdc3a57b4d27fbdbc22e Mon Sep 17 00:00:00 2001
+From: Weijie Gao <weijie.gao@mediatek.com>
+Date: Wed, 27 Jul 2022 11:01:34 +0800
+Subject: [PATCH 13/31] pwm: mtk: add support for MediaTek MT7981 SoC
+
+This patch adds PWM support for MediaTek MT7981 SoC.
+MT7981 uses a different register offset so we have to add a version field
+to indicate the IP core version.
+
+Reviewed-by: Simon Glass <sjg@chromium.org>
+Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+---
+ drivers/pwm/pwm-mtk.c | 34 ++++++++++++++++++++++++++++++++--
+ 1 file changed, 32 insertions(+), 2 deletions(-)
+
+--- a/drivers/pwm/pwm-mtk.c
++++ b/drivers/pwm/pwm-mtk.c
+@@ -29,13 +29,23 @@
+ 
+ #define NSEC_PER_SEC 1000000000L
+ 
+-static const unsigned int mtk_pwm_reg_offset[] = {
++enum mtk_pwm_reg_ver {
++	PWM_REG_V1,
++	PWM_REG_V2,
++};
++
++static const unsigned int mtk_pwm_reg_offset_v1[] = {
+ 	0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220
+ };
+ 
++static const unsigned int mtk_pwm_reg_offset_v2[] = {
++	0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x01c0, 0x0200, 0x0240
++};
++
+ struct mtk_pwm_soc {
+ 	unsigned int num_pwms;
+ 	bool pwm45_fixup;
++	enum mtk_pwm_reg_ver reg_ver;
+ };
+ 
+ struct mtk_pwm_priv {
+@@ -49,7 +59,16 @@ struct mtk_pwm_priv {
+ static void mtk_pwm_w32(struct udevice *dev, uint channel, uint reg, uint val)
+ {
+ 	struct mtk_pwm_priv *priv = dev_get_priv(dev);
+-	u32 offset = mtk_pwm_reg_offset[channel];
++	u32 offset;
++
++	switch (priv->soc->reg_ver) {
++	case PWM_REG_V2:
++		offset = mtk_pwm_reg_offset_v2[channel];
++		break;
++
++	default:
++		offset = mtk_pwm_reg_offset_v1[channel];
++	}
+ 
+ 	writel(val, priv->base + offset + reg);
+ }
+@@ -159,27 +178,38 @@ static const struct pwm_ops mtk_pwm_ops
+ static const struct mtk_pwm_soc mt7622_data = {
+ 	.num_pwms = 6,
+ 	.pwm45_fixup = false,
++	.reg_ver = PWM_REG_V1,
+ };
+ 
+ static const struct mtk_pwm_soc mt7623_data = {
+ 	.num_pwms = 5,
+ 	.pwm45_fixup = true,
++	.reg_ver = PWM_REG_V1,
+ };
+ 
+ static const struct mtk_pwm_soc mt7629_data = {
+ 	.num_pwms = 1,
+ 	.pwm45_fixup = false,
++	.reg_ver = PWM_REG_V1,
++};
++
++static const struct mtk_pwm_soc mt7981_data = {
++	.num_pwms = 2,
++	.pwm45_fixup = false,
++	.reg_ver = PWM_REG_V2,
+ };
+ 
+ static const struct mtk_pwm_soc mt7986_data = {
+ 	.num_pwms = 2,
+ 	.pwm45_fixup = false,
++	.reg_ver = PWM_REG_V1,
+ };
+ 
+ static const struct udevice_id mtk_pwm_ids[] = {
+ 	{ .compatible = "mediatek,mt7622-pwm", .data = (ulong)&mt7622_data },
+ 	{ .compatible = "mediatek,mt7623-pwm", .data = (ulong)&mt7623_data },
+ 	{ .compatible = "mediatek,mt7629-pwm", .data = (ulong)&mt7629_data },
++	{ .compatible = "mediatek,mt7981-pwm", .data = (ulong)&mt7981_data },
+ 	{ .compatible = "mediatek,mt7986-pwm", .data = (ulong)&mt7986_data },
+ 	{ }
+ };