diff options
Diffstat (limited to 'package/boot/uboot-layerscape/patches/0063-board-freescale-ls1012a-Enable-secure-DDR-on-LS1012A.patch')
| -rw-r--r-- | package/boot/uboot-layerscape/patches/0063-board-freescale-ls1012a-Enable-secure-DDR-on-LS1012A.patch | 157 |
1 files changed, 0 insertions, 157 deletions
diff --git a/package/boot/uboot-layerscape/patches/0063-board-freescale-ls1012a-Enable-secure-DDR-on-LS1012A.patch b/package/boot/uboot-layerscape/patches/0063-board-freescale-ls1012a-Enable-secure-DDR-on-LS1012A.patch deleted file mode 100644 index 52bc555d51..0000000000 --- a/package/boot/uboot-layerscape/patches/0063-board-freescale-ls1012a-Enable-secure-DDR-on-LS1012A.patch +++ /dev/null @@ -1,157 +0,0 @@ -From 1882af9f2c7533c6cd2dea5811b4e69f9a151f29 Mon Sep 17 00:00:00 2001 -From: Abhimanyu Saini <abhimanyu.saini@nxp.com> -Date: Fri, 24 Jun 2016 10:45:39 +0530 -Subject: [PATCH 63/93] board: freescale: ls1012a: Enable secure DDR on - LS1012A platforms - -PPA binary needs to be relocated on secure DDR, hence marking out -a portion of DDR as secure if CONFIG_SYS_MEM_RESERVE_SECURE flag -is set - -Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> -Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> ---- - arch/arm/include/asm/arch-fsl-layerscape/config.h | 3 +++ - board/freescale/ls1012afrdm/ls1012afrdm.c | 28 +++++++++++++++++++++ - board/freescale/ls1012aqds/ls1012aqds.c | 28 +++++++++++++++++++++ - board/freescale/ls1012ardb/ls1012ardb.c | 28 +++++++++++++++++++++ - include/configs/ls1012a_common.h | 1 + - 5 files changed, 88 insertions(+) - -diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h -index 679be6c..efaa79a 100644 ---- a/arch/arm/include/asm/arch-fsl-layerscape/config.h -+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h -@@ -222,6 +222,9 @@ - #define GICD_BASE 0x01401000 - #define GICC_BASE 0x01402000 - -+#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -+#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE -+ - #define CONFIG_SYS_FSL_CCSR_GUR_BE - #define CONFIG_SYS_FSL_CCSR_SCFG_BE - #define CONFIG_SYS_FSL_ESDHC_BE -diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c -index 6856250..c691a76 100644 ---- a/board/freescale/ls1012afrdm/ls1012afrdm.c -+++ b/board/freescale/ls1012afrdm/ls1012afrdm.c -@@ -176,3 +176,31 @@ int ft_board_setup(void *blob, bd_t *bd) - - return 0; - } -+ -+void dram_init_banksize(void) -+{ -+ /* -+ * gd->secure_ram tracks the location of secure memory. -+ * It was set as if the memory starts from 0. -+ * The address needs to add the offset of its bank. -+ */ -+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; -+ if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { -+ gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; -+ gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; -+ gd->bd->bi_dram[1].size = gd->ram_size - -+ CONFIG_SYS_DDR_BLOCK1_SIZE; -+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE -+ gd->secure_ram = gd->bd->bi_dram[1].start + -+ gd->secure_ram - -+ CONFIG_SYS_DDR_BLOCK1_SIZE; -+ gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -+#endif -+ } else { -+ gd->bd->bi_dram[0].size = gd->ram_size; -+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE -+ gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram; -+ gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -+#endif -+ } -+} -diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c -index 56004ea..516f0c3 100644 ---- a/board/freescale/ls1012aqds/ls1012aqds.c -+++ b/board/freescale/ls1012aqds/ls1012aqds.c -@@ -240,3 +240,31 @@ int ft_board_setup(void *blob, bd_t *bd) - return 0; - } - #endif -+ -+void dram_init_banksize(void) -+{ -+ /* -+ * gd->secure_ram tracks the location of secure memory. -+ * It was set as if the memory starts from 0. -+ * The address needs to add the offset of its bank. -+ */ -+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; -+ if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { -+ gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; -+ gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; -+ gd->bd->bi_dram[1].size = gd->ram_size - -+ CONFIG_SYS_DDR_BLOCK1_SIZE; -+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE -+ gd->secure_ram = gd->bd->bi_dram[1].start + -+ gd->secure_ram - -+ CONFIG_SYS_DDR_BLOCK1_SIZE; -+ gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -+#endif -+ } else { -+ gd->bd->bi_dram[0].size = gd->ram_size; -+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE -+ gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram; -+ gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -+#endif -+ } -+} -diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c -index ad4d8ee..8340f14 100644 ---- a/board/freescale/ls1012ardb/ls1012ardb.c -+++ b/board/freescale/ls1012ardb/ls1012ardb.c -@@ -235,3 +235,31 @@ int ft_board_setup(void *blob, bd_t *bd) - - return 0; - } -+ -+void dram_init_banksize(void) -+{ -+ /* -+ * gd->secure_ram tracks the location of secure memory. -+ * It was set as if the memory starts from 0. -+ * The address needs to add the offset of its bank. -+ */ -+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; -+ if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { -+ gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; -+ gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; -+ gd->bd->bi_dram[1].size = gd->ram_size - -+ CONFIG_SYS_DDR_BLOCK1_SIZE; -+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE -+ gd->secure_ram = gd->bd->bi_dram[1].start + -+ gd->secure_ram - -+ CONFIG_SYS_DDR_BLOCK1_SIZE; -+ gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -+#endif -+ } else { -+ gd->bd->bi_dram[0].size = gd->ram_size; -+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE -+ gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram; -+ gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -+#endif -+ } -+} -diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h -index 7c0e64f..4c7c697 100644 ---- a/include/configs/ls1012a_common.h -+++ b/include/configs/ls1012a_common.h -@@ -36,6 +36,7 @@ - #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 - #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 - #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -+#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL - - /* Generic Timer Definitions */ - #define COUNTER_FREQUENCY 25000000 /* 12MHz */ --- -1.7.9.5 - |