diff options
Diffstat (limited to 'package/boot/uboot-lantiq/patches')
5 files changed, 381 insertions, 0 deletions
diff --git a/package/boot/uboot-lantiq/patches/0030-lzma-force-8bit-reads.patch b/package/boot/uboot-lantiq/patches/0030-lzma-force-8bit-reads.patch new file mode 100644 index 00000000000..a934dab5cd6 --- /dev/null +++ b/package/boot/uboot-lantiq/patches/0030-lzma-force-8bit-reads.patch @@ -0,0 +1,57 @@ +From a40a6e16ed76e5e26a0f60226b64c311d4a62c9f Mon Sep 17 00:00:00 2001 +From: Mathias Kresin <dev@kresin.me> +Date: Sun, 31 Oct 2021 23:04:54 +0100 +Subject: [PATCH] lzma: force 8bit reads + +At least since gcc 7.3.0 (OpenWrt 18.06) lwr/lwl are used in the +assembly of LzmaProps_Decode. While the decission made by the compiler +looks perfect fine, it triggers some obscure hang on lantiq danube-s +v1.5 with MX29LV640EB NOR flash chips. + +Only if the offset 1 is used, the hang can be observed. Using any other +offset works fine: + + lwl s0,0(a1) - s0 == 0x6d000080 + lwl s0,1(a1) - hangs + lwl s0,2(a1) - s0 == 0x0080xxxx + lwl s0,3(a1) - s0 == 0x80xxxxxx + +It isn't clear whether it is a limitation of the flash chip, the EBU or +something else. + +Force 8bit reads to prevent gcc optimizing the read with lwr/lwl +instructions. + +Signed-off-by: Mathias Kresin <dev@kresin.me> +--- + lib/lzma/LzmaDec.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/lib/lzma/LzmaDec.c ++++ b/lib/lzma/LzmaDec.c +@@ -7,6 +7,7 @@ + #include "LzmaDec.h" + + #include <linux/string.h> ++#include <asm/io.h> + + #define kNumTopBits 24 + #define kTopValue ((UInt32)1 << kNumTopBits) +@@ -703,7 +704,7 @@ static ELzmaDummy LzmaDec_TryDummy(const + + static void LzmaDec_InitRc(CLzmaDec *p, const Byte *data) + { +- p->code = ((UInt32)data[1] << 24) | ((UInt32)data[2] << 16) | ((UInt32)data[3] << 8) | ((UInt32)data[4]); ++ p->code = ((UInt32)readb(&data[1]) << 24) | ((UInt32)readb(&data[2]) << 16) | ((UInt32)readb(&data[3]) << 8) | ((UInt32)readb(&data[4])); + p->range = 0xFFFFFFFF; + p->needFlush = 0; + } +@@ -929,7 +930,7 @@ SRes LzmaProps_Decode(CLzmaProps *p, con + if (size < LZMA_PROPS_SIZE) + return SZ_ERROR_UNSUPPORTED; + else +- dicSize = data[1] | ((UInt32)data[2] << 8) | ((UInt32)data[3] << 16) | ((UInt32)data[4] << 24); ++ dicSize = readb(&data[1]) | ((UInt32)readb(&data[2]) << 8) | ((UInt32)readb(&data[3]) << 16) | ((UInt32)readb(&data[4]) << 24); + + if (dicSize < LZMA_DIC_MIN) + dicSize = LZMA_DIC_MIN; diff --git a/package/boot/uboot-lantiq/patches/0031-dma-lantiq-fix-out-of-bounds-cache-invalidate.patch b/package/boot/uboot-lantiq/patches/0031-dma-lantiq-fix-out-of-bounds-cache-invalidate.patch new file mode 100644 index 00000000000..b99b07292ce --- /dev/null +++ b/package/boot/uboot-lantiq/patches/0031-dma-lantiq-fix-out-of-bounds-cache-invalidate.patch @@ -0,0 +1,62 @@ +From d9527989b2d63749d6c6678fa3a1b658eb26c225 Mon Sep 17 00:00:00 2001 +From: Mathias Kresin <dev@kresin.me> +Date: Tue, 2 Nov 2021 21:24:29 +0100 +Subject: [PATCH] dma: lantiq: fix out of bounds cache invalidate + +With gcc10 the variables are placed more tightly to each other, which +uncovers a long existing bug in the lantiq DMA code. It can be observed +when using tftpboot with the filename parameter, which gets reset during +the tftpboot execution. + +NetRxPackets[] points to cache line size aligned addresses. In +ltq_eth_rx_packet_align() the address NetRxPackets[] points to is +increased by LTQ_ETH_IP_ALIGN and the resulting not cache aligned +address is used further on. While doing so, the length/size is never +updated. + +The "not cache aligned address" + len/size for a cache aligned address +is passed to invalidate_dcache_range(). Hence, invalidate_dcache_range() +invalidates the next 32 bit as well, which flashes the BootFile variable +as well. + + variable BootFile is at address: 0x83ffe12c + NetRxPackets[] points to 0x83ffdb20 (len is 0x600) + data points to: 0x83ffdb22 (len is 0x600) + + ltq_dma_dcache_inv: 0x83ffdb22 (for len 0x600) + invalidate_dcache_range: 0x83ffdb20 to 0x83ffe120 (size: 32) + invalidate_dcache_range: 0x83ffdb20 to 0x83ffdb40 (Bootfile: a.bin) + ... + invalidate_dcache_range: 0x83ffe100 to 0x83ffe120 (Bootfile: a.bin) + invalidate_dcache_range: 0x83ffe120 to 0x83ffe140 (Bootfile: ) + +In ltq_dma_tx_map() and ltq_dma_rx_map() the start address passed to +ltq_dma_dcache_wb_inv() is incorrect. By considering the offset, the +start address passed to flush_dcache_range() is always aligned to 32, 64 +or 128 bytes dependent on configured DMA burst size. + +Signed-off-by: Mathias Kresin <dev@kresin.me> +--- + drivers/dma/lantiq_dma.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/dma/lantiq_dma.c ++++ b/drivers/dma/lantiq_dma.c +@@ -280,7 +280,7 @@ int ltq_dma_rx_map(struct ltq_dma_device + + offset = dma_addr % ltq_dma_burst_align(dev->rx_burst_len); + +- ltq_dma_dcache_inv(data, len); ++ ltq_dma_dcache_inv(data - offset, len); + + #if 0 + printf("%s: index %d, data %p, dma_addr %08x, offset %u, len %d\n", +@@ -355,7 +355,7 @@ int ltq_dma_tx_map(struct ltq_dma_device + __func__, index, desc, data, dma_addr, offset, len); + #endif + +- ltq_dma_dcache_wb_inv(data, len); ++ ltq_dma_dcache_wb_inv(data - offset, len); + + desc->addr = dma_addr - offset; + desc->ctl = DMA_DESC_OWN | DMA_DESC_SOP | DMA_DESC_EOP | diff --git a/package/boot/uboot-lantiq/patches/0032-MIPS-lantiq-danube-fix-SPL-boot.patch b/package/boot/uboot-lantiq/patches/0032-MIPS-lantiq-danube-fix-SPL-boot.patch new file mode 100644 index 00000000000..6cb309b8f2d --- /dev/null +++ b/package/boot/uboot-lantiq/patches/0032-MIPS-lantiq-danube-fix-SPL-boot.patch @@ -0,0 +1,34 @@ +From 65f1f160139c2bac83650c9c7c4aee4e5fd74c7c Mon Sep 17 00:00:00 2001 +From: Mathias Kresin <dev@kresin.me> +Date: Sun, 2 May 2021 02:03:05 +0200 +Subject: [PATCH] MIPS: lantiq: danube: fix SPL boot + +On danube we only have 0x6800 bytes of usable SRAM. Everything behind +can't be written to and a SPL u-boot locks up during boot. + +Signed-off-by: Mathias Kresin <dev@kresin.me> +Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +--- + arch/mips/include/asm/arch-danube/config.h | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/arch/mips/include/asm/arch-danube/config.h ++++ b/arch/mips/include/asm/arch-danube/config.h +@@ -61,7 +61,7 @@ + + /* SRAM */ + #define CONFIG_SYS_SRAM_BASE 0xBE1A0000 +-#define CONFIG_SYS_SRAM_SIZE 0x10000 ++#define CONFIG_SYS_SRAM_SIZE 0x6800 + + /* ASC/UART driver and console */ + #define CONFIG_LANTIQ_SERIAL +@@ -117,7 +117,7 @@ + #define CONFIG_CMD_NET + #endif + +-#define CONFIG_SPL_MAX_SIZE (32 * 1024) ++#define CONFIG_SPL_MAX_SIZE (18 * 1024) + #define CONFIG_SPL_BSS_MAX_SIZE (8 * 1024) + #define CONFIG_SPL_STACK_MAX_SIZE (8 * 1024) + #define CONFIG_SPL_MALLOC_MAX_SIZE (32 * 1024) diff --git a/package/boot/uboot-lantiq/patches/0033-MIPS-lantiq-reduce-stack-size.patch b/package/boot/uboot-lantiq/patches/0033-MIPS-lantiq-reduce-stack-size.patch new file mode 100644 index 00000000000..4f63ffc423a --- /dev/null +++ b/package/boot/uboot-lantiq/patches/0033-MIPS-lantiq-reduce-stack-size.patch @@ -0,0 +1,56 @@ +From ad739ffebf689abdbcddbe4e1b0bf847d7931a92 Mon Sep 17 00:00:00 2001 +From: Mathias Kresin <dev@kresin.me> +Date: Fri, 20 Jan 2017 13:59:53 +0100 +Subject: [PATCH] MIPS: lantiq: reduce stack size + +On lantiq a lot of stuff expects to be loaded to and executed at +0x80002000, including our own second stage bootloader. + +For all build u-boots, the initial stack pointer is at 0x80008000. After +loading data to 0x80002000, every further stack operation corrupts the +loaded code. + +Set the initial stack pointer to 0x80002000, to not overwrite code +loaded in memory. A stack of 0x2000 bytes has been proven as enough in +all done tests. + +Signed-off-by: Mathias Kresin <dev@kresin.me> +--- + arch/mips/include/asm/arch-arx100/config.h | 2 +- + arch/mips/include/asm/arch-danube/config.h | 2 +- + arch/mips/include/asm/arch-vrx200/config.h | 2 +- + 3 files changed, 3 insertions(+), 3 deletions(-) + +--- a/arch/mips/include/asm/arch-arx100/config.h ++++ b/arch/mips/include/asm/arch-arx100/config.h +@@ -66,7 +66,7 @@ + #define CONFIG_SYS_MEMTEST_END 0x82000000 + #define CONFIG_SYS_LOAD_ADDR 0x81000000 + #define CONFIG_SYS_LOAD_SIZE (2 * 1024 * 1024) +-#define CONFIG_SYS_INIT_SP_OFFSET (32 * 1024) ++#define CONFIG_SYS_INIT_SP_OFFSET 0x2000 + + /* SRAM */ + #define CONFIG_SYS_SRAM_BASE 0xBE1A0000 +--- a/arch/mips/include/asm/arch-danube/config.h ++++ b/arch/mips/include/asm/arch-danube/config.h +@@ -57,7 +57,7 @@ + #define CONFIG_SYS_MEMTEST_END 0x82000000 + #define CONFIG_SYS_LOAD_ADDR 0x81000000 + #define CONFIG_SYS_LOAD_SIZE (2 * 1024 * 1024) +-#define CONFIG_SYS_INIT_SP_OFFSET 0x4000 ++#define CONFIG_SYS_INIT_SP_OFFSET 0x2000 + + /* SRAM */ + #define CONFIG_SYS_SRAM_BASE 0xBE1A0000 +--- a/arch/mips/include/asm/arch-vrx200/config.h ++++ b/arch/mips/include/asm/arch-vrx200/config.h +@@ -69,7 +69,7 @@ + #define CONFIG_SYS_MEMTEST_END 0x82000000 + #define CONFIG_SYS_LOAD_ADDR 0x81000000 + #define CONFIG_SYS_LOAD_SIZE (2 * 1024 * 1024) +-#define CONFIG_SYS_INIT_SP_OFFSET (32 * 1024) ++#define CONFIG_SYS_INIT_SP_OFFSET 0x2000 + + /* SRAM */ + #define CONFIG_SYS_SRAM_BASE 0xBE220000 diff --git a/package/boot/uboot-lantiq/patches/101-fix-crypt-header-clash.patch b/package/boot/uboot-lantiq/patches/101-fix-crypt-header-clash.patch new file mode 100644 index 00000000000..fcb1a3d95b0 --- /dev/null +++ b/package/boot/uboot-lantiq/patches/101-fix-crypt-header-clash.patch @@ -0,0 +1,172 @@ +Fix header clash with system /usr/include/sha1.h and sha256.h when libmd +is installed. + +Backport of u-boot commit "includes: move openssl headers to include/u-boot" +https://github.com/u-boot/u-boot/commit/2b9912e6a7df7b1f60beb7942bd0e6fa5f9d0167 + +--- a/board/gdsys/p1022/controlcenterd-id.c ++++ b/board/gdsys/p1022/controlcenterd-id.c +@@ -30,7 +30,7 @@ + #include <i2c.h> + #include <mmc.h> + #include <tpm.h> +-#include <sha1.h> ++#include <u-boot/sha1.h> + #include <asm/byteorder.h> + #include <asm/unaligned.h> + #include <pca9698.h> +--- a/board/pcs440ep/pcs440ep.c ++++ b/board/pcs440ep/pcs440ep.c +@@ -13,7 +13,7 @@ + #include <asm/processor.h> + #include <spd_sdram.h> + #include <status_led.h> +-#include <sha1.h> ++#include <u-boot/sha1.h> + #include <asm/io.h> + #include <net.h> + #include <ata.h> +--- a/common/cmd_sha1sum.c ++++ b/common/cmd_sha1sum.c +@@ -11,7 +11,7 @@ + #include <common.h> + #include <command.h> + #include <hash.h> +-#include <sha1.h> ++#include <u-boot/sha1.h> + + int do_sha1sum(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) + { +--- a/common/hash.c ++++ b/common/hash.c +@@ -14,8 +14,8 @@ + #include <command.h> + #include <hw_sha.h> + #include <hash.h> +-#include <sha1.h> +-#include <sha256.h> ++#include <u-boot/sha1.h> ++#include <u-boot/sha256.h> + #include <asm/io.h> + #include <asm/errno.h> + +--- a/common/image-fit.c ++++ b/common/image-fit.c +@@ -21,7 +21,7 @@ DECLARE_GLOBAL_DATA_PTR; + #endif /* !USE_HOSTCC*/ + + #include <bootstage.h> +-#include <sha1.h> ++#include <u-boot/sha1.h> + #include <u-boot/crc.h> + #include <u-boot/md5.h> + +--- a/common/image.c ++++ b/common/image.c +@@ -34,7 +34,7 @@ + #endif + + #include <u-boot/md5.h> +-#include <sha1.h> ++#include <u-boot/sha1.h> + #include <asm/errno.h> + #include <asm/io.h> + +--- a/drivers/crypto/ace_sha.c ++++ b/drivers/crypto/ace_sha.c +@@ -5,8 +5,8 @@ + * SPDX-License-Identifier: GPL-2.0+ + */ + #include <common.h> +-#include <sha256.h> +-#include <sha1.h> ++#include <u-boot/sha256.h> ++#include <u-boot/sha1.h> + #include <asm/errno.h> + #include "ace_sha.h" + +--- /dev/null ++++ b/include/u-boot/sha1.h +@@ -0,0 +1 @@ ++#include "../sha1.h" +--- /dev/null ++++ b/include/u-boot/sha256.h +@@ -0,0 +1 @@ ++#include "../sha256.h" +--- a/lib/rsa/rsa-verify.c ++++ b/lib/rsa/rsa-verify.c +@@ -7,7 +7,7 @@ + #include <common.h> + #include <fdtdec.h> + #include <rsa.h> +-#include <sha1.h> ++#include <u-boot/sha1.h> + #include <asm/byteorder.h> + #include <asm/errno.h> + #include <asm/unaligned.h> +--- a/lib/sha1.c ++++ b/lib/sha1.c +@@ -36,7 +36,7 @@ + #include <string.h> + #endif /* USE_HOSTCC */ + #include <watchdog.h> +-#include "sha1.h" ++#include <u-boot/sha1.h> + + /* + * 32-bit integer manipulation macros (big endian) +--- a/lib/sha256.c ++++ b/lib/sha256.c +@@ -11,7 +11,7 @@ + #endif /* USE_HOSTCC */ + #include <watchdog.h> + #include <linux/string.h> +-#include <sha256.h> ++#include <u-boot/sha256.h> + + /* + * 32-bit integer manipulation macros (big endian) +--- a/lib/tpm.c ++++ b/lib/tpm.c +@@ -7,7 +7,7 @@ + + #include <common.h> + #include <stdarg.h> +-#include <sha1.h> ++#include <u-boot/sha1.h> + #include <tpm.h> + #include <asm/unaligned.h> + +--- a/tools/imls/imls.c ++++ b/tools/imls/imls.c +@@ -24,7 +24,7 @@ + #include <mtd/mtd-user.h> + #endif + +-#include <sha1.h> ++#include <u-boot/sha1.h> + #include <libfdt.h> + #include <fdt_support.h> + #include <image.h> +--- a/tools/mkimage.h ++++ b/tools/mkimage.h +@@ -18,7 +18,7 @@ + #include <sys/stat.h> + #include <time.h> + #include <unistd.h> +-#include <sha1.h> ++#include <u-boot/sha1.h> + #include "fdt_host.h" + + #undef MKIMAGE_DEBUG +--- a/tools/ubsha1.c ++++ b/tools/ubsha1.c +@@ -13,7 +13,7 @@ + #include <errno.h> + #include <string.h> + #include <sys/stat.h> +-#include "sha1.h" ++#include <u-boot/sha1.h> + + int main (int argc, char **argv) + { |