diff options
8 files changed, 524 insertions, 1 deletions
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a.dtsi index e135fee35a..ade4cebbd5 100644 --- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +++ b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a.dtsi @@ -9,6 +9,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/phy/phy.h> #include <dt-bindings/reset/mt7986-resets.h> +#include <dt-bindings/thermal/thermal.h> / { interrupt-parent = <&gic>; @@ -199,6 +200,20 @@ status = "okay"; }; + pwm: pwm@10048000 { + compatible = "mediatek,mt7986-pwm"; + reg = <0 0x10048000 0 0x1000>; + #clock-cells = <1>; + #pwm-cells = <2>; + interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&topckgen CLK_TOP_PWM_SEL>, + <&infracfg CLK_INFRA_PWM_BSEL>, + <&infracfg CLK_INFRA_PWM1_CK>, + <&infracfg CLK_INFRA_PWM2_CK>; + clock-names = "top", "main", "pwm1", "pwm2"; + status = "disabled"; + }; + uart0: serial@11002000 { compatible = "mediatek,mt7986-uart", "mediatek,mt6577-uart"; @@ -240,6 +255,20 @@ status = "disabled"; }; + i2c0: i2c@11008000 { + compatible = "mediatek,mt7986-i2c"; + reg = <0 0x11008000 0 0x90>, + <0 0x10217080 0 0x80>; + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; + clock-div = <5>; + clocks = <&infracfg CLK_INFRA_I2C0_CK>, + <&infracfg CLK_INFRA_AP_DMA_CK>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + spi0: spi@1100a000 { compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; reg = <0 0x1100a000 0 0x100>; @@ -264,6 +293,16 @@ status = "disabled"; }; + auxadc: adc@1100d000 { + compatible = "mediatek,mt7986-auxadc", + "mediatek,mt7622-auxadc"; + reg = <0 0x1100d000 0 0x1000>; + clocks = <&infracfg CLK_INFRA_ADC_26M_CK>, + <&infracfg CLK_INFRA_ADC_FRC_CK>; + clock-names = "main", "32k"; + #io-channel-cells = <1>; + }; + ssusb: usb@11200000 { compatible = "mediatek,mt7986-xhci", "mediatek,mtk-xhci"; @@ -304,6 +343,21 @@ status = "disabled"; }; + thermal: thermal@1100c800 { + #thermal-sensor-cells = <1>; + compatible = "mediatek,mt7986-thermal"; + reg = <0 0x1100c800 0 0x800>; + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&infracfg CLK_INFRA_THERM_CK>, + <&infracfg CLK_INFRA_ADC_26M_CK>, + <&infracfg CLK_INFRA_ADC_FRC_CK>; + clock-names = "therm", "auxadc", "adc_32k"; + mediatek,auxadc = <&auxadc>; + mediatek,apmixedsys = <&apmixedsys>; + nvmem-cells = <&thermal_calibration>; + nvmem-cell-names = "calibration-data"; + }; + pcie: pcie@11280000 { compatible = "mediatek,mt7986-pcie", "mediatek,mt8192-pcie"; @@ -373,7 +427,6 @@ }; }; - efuse: efuse@11d00000 { compatible = "mediatek,mt7986-efuse", "mediatek,efuse"; @@ -609,4 +662,71 @@ }; }; + fan: pwm-fan { + compatible = "pwm-fan"; + /* cooling level (0, 1, 2) : (0% duty, 50% duty, 100% duty) */ + cooling-levels = <0 128 255>; + #cooling-cells = <2>; + status = "disabled"; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <1000>; + polling-delay = <1000>; + thermal-sensors = <&thermal 0>; + trips { + cpu_trip_crit: crit { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + + cpu_trip_hot: hot { + temperature = <120000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpu_trip_active_high: active-high { + temperature = <115000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_trip_active_low: active-low { + temperature = <85000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_trip_passive: passive { + temperature = <40000>; + hysteresis = <2000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu-active-high { + /* active: set fan to cooling level 2 */ + cooling-device = <&fan 2 2>; + trip = <&cpu_trip_active_high>; + }; + + cpu-active-low { + /* active: set fan to cooling level 1 */ + cooling-device = <&fan 1 1>; + trip = <&cpu_trip_active_low>; + }; + + cpu-passive { + /* passive: set fan to cooling level 0 */ + cooling-device = <&fan 0 0>; + trip = <&cpu_trip_passive>; + }; + }; + + }; + }; }; diff --git a/target/linux/mediatek/patches-5.15/501-auxadc-add-auxadc-32k-clk.patch b/target/linux/mediatek/patches-5.15/501-auxadc-add-auxadc-32k-clk.patch new file mode 100644 index 0000000000..a49fbca4ee --- /dev/null +++ b/target/linux/mediatek/patches-5.15/501-auxadc-add-auxadc-32k-clk.patch @@ -0,0 +1,66 @@ +--- a/drivers/iio/adc/mt6577_auxadc.c ++++ b/drivers/iio/adc/mt6577_auxadc.c +@@ -42,6 +42,7 @@ struct mtk_auxadc_compatible { + struct mt6577_auxadc_device { + void __iomem *reg_base; + struct clk *adc_clk; ++ struct clk *adc_32k_clk; + struct mutex lock; + const struct mtk_auxadc_compatible *dev_comp; + }; +@@ -222,6 +223,12 @@ static int __maybe_unused mt6577_auxadc_ + return ret; + } + ++ ret = clk_prepare_enable(adc_dev->adc_32k_clk); ++ if (ret) { ++ pr_err("failed to enable auxadc clock\n"); ++ return ret; ++ } ++ + mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC, + MT6577_AUXADC_PDN_EN, 0); + mdelay(MT6577_AUXADC_POWER_READY_MS); +@@ -236,6 +243,8 @@ static int __maybe_unused mt6577_auxadc_ + + mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC, + 0, MT6577_AUXADC_PDN_EN); ++ ++ clk_disable_unprepare(adc_dev->adc_32k_clk); + clk_disable_unprepare(adc_dev->adc_clk); + + return 0; +@@ -277,6 +286,17 @@ static int mt6577_auxadc_probe(struct pl + return ret; + } + ++ adc_dev->adc_32k_clk = devm_clk_get(&pdev->dev, "32k"); ++ if (IS_ERR(adc_dev->adc_32k_clk)) { ++ dev_err(&pdev->dev, "failed to get auxadc 32k clock\n"); ++ } else { ++ ret = clk_prepare_enable(adc_dev->adc_32k_clk); ++ if (ret) { ++ dev_err(&pdev->dev, "failed to enable auxadc 32k clock\n"); ++ return ret; ++ } ++ } ++ + adc_clk_rate = clk_get_rate(adc_dev->adc_clk); + if (!adc_clk_rate) { + ret = -EINVAL; +@@ -306,6 +326,7 @@ err_power_off: + mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC, + 0, MT6577_AUXADC_PDN_EN); + err_disable_clk: ++ clk_disable_unprepare(adc_dev->adc_32k_clk); + clk_disable_unprepare(adc_dev->adc_clk); + return ret; + } +@@ -320,6 +341,7 @@ static int mt6577_auxadc_remove(struct p + mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC, + 0, MT6577_AUXADC_PDN_EN); + ++ clk_disable_unprepare(adc_dev->adc_32k_clk); + clk_disable_unprepare(adc_dev->adc_clk); + + return 0; diff --git a/target/linux/mediatek/patches-5.15/815-nvmem-mtk-efuse-support-minimum-one-byte-access-stri.patch b/target/linux/mediatek/patches-5.15/800-nvmem-mtk-efuse-support-minimum-one-byte-access-stri.patch index e57f742fc8..e57f742fc8 100644 --- a/target/linux/mediatek/patches-5.15/815-nvmem-mtk-efuse-support-minimum-one-byte-access-stri.patch +++ b/target/linux/mediatek/patches-5.15/800-nvmem-mtk-efuse-support-minimum-one-byte-access-stri.patch diff --git a/target/linux/mediatek/patches-5.15/817-phy-phy-mtk-tphy-Add-PCIe-2-lane-efuse-support.patch b/target/linux/mediatek/patches-5.15/801-phy-phy-mtk-tphy-Add-PCIe-2-lane-efuse-support.patch index 4c2fd18b3b..4c2fd18b3b 100644 --- a/target/linux/mediatek/patches-5.15/817-phy-phy-mtk-tphy-Add-PCIe-2-lane-efuse-support.patch +++ b/target/linux/mediatek/patches-5.15/801-phy-phy-mtk-tphy-Add-PCIe-2-lane-efuse-support.patch diff --git a/target/linux/mediatek/patches-5.15/818-phy-phy-mtk-tphy-add-auto-load-valid-check-mechanism.patch b/target/linux/mediatek/patches-5.15/802-phy-phy-mtk-tphy-add-auto-load-valid-check-mechanism.patch index 67580f1e11..67580f1e11 100644 --- a/target/linux/mediatek/patches-5.15/818-phy-phy-mtk-tphy-add-auto-load-valid-check-mechanism.patch +++ b/target/linux/mediatek/patches-5.15/802-phy-phy-mtk-tphy-add-auto-load-valid-check-mechanism.patch diff --git a/target/linux/mediatek/patches-5.15/803-i2c-busses-add-mt7986-support.patch b/target/linux/mediatek/patches-5.15/803-i2c-busses-add-mt7986-support.patch new file mode 100644 index 0000000000..1860a6da01 --- /dev/null +++ b/target/linux/mediatek/patches-5.15/803-i2c-busses-add-mt7986-support.patch @@ -0,0 +1,30 @@ +--- a/drivers/i2c/busses/i2c-mt65xx.c ++++ b/drivers/i2c/busses/i2c-mt65xx.c +@@ -365,6 +365,19 @@ static const struct mtk_i2c_compatible m + .max_dma_support = 32, + }; + ++static const struct mtk_i2c_compatible mt7986_compat = { ++ .quirks = &mt7622_i2c_quirks, ++ .regs = mt_i2c_regs_v1, ++ .pmic_i2c = 0, ++ .dcm = 1, ++ .auto_restart = 1, ++ .aux_len_reg = 1, ++ .max_dma_support = 32, ++ .timing_adjust = 0, ++ .dma_sync = 1, ++ .ltiming_adjust = 0, ++}; ++ + static const struct mtk_i2c_compatible mt8173_compat = { + .regs = mt_i2c_regs_v1, + .pmic_i2c = 0, +@@ -411,6 +424,7 @@ static const struct of_device_id mtk_i2c + { .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat }, + { .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat }, + { .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat }, ++ { .compatible = "mediatek,mt7986-i2c", .data = &mt7986_compat }, + { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat }, + { .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat }, + { .compatible = "mediatek,mt8192-i2c", .data = &mt8192_compat }, diff --git a/target/linux/mediatek/patches-5.15/804-pwm-add-mt7986-support.patch b/target/linux/mediatek/patches-5.15/804-pwm-add-mt7986-support.patch new file mode 100644 index 0000000000..fe095c5633 --- /dev/null +++ b/target/linux/mediatek/patches-5.15/804-pwm-add-mt7986-support.patch @@ -0,0 +1,23 @@ +--- a/drivers/pwm/pwm-mediatek.c ++++ b/drivers/pwm/pwm-mediatek.c +@@ -302,6 +302,12 @@ static const struct pwm_mediatek_of_data + .has_ck_26m_sel = true, + }; + ++static const struct pwm_mediatek_of_data mt7986_pwm_data = { ++ .num_pwms = 2, ++ .pwm45_fixup = false, ++ .has_ck_26m_sel = false, ++}; ++ + static const struct pwm_mediatek_of_data mt8516_pwm_data = { + .num_pwms = 5, + .pwm45_fixup = false, +@@ -314,6 +320,7 @@ static const struct of_device_id pwm_med + { .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data }, + { .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data }, + { .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data }, ++ { .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data }, + { .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data }, + { .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data }, + { }, diff --git a/target/linux/mediatek/patches-5.15/805-thermal-drivers-mediatek-add-support-for-MT7986-and-.patch b/target/linux/mediatek/patches-5.15/805-thermal-drivers-mediatek-add-support-for-MT7986-and-.patch new file mode 100644 index 0000000000..ff2b71872c --- /dev/null +++ b/target/linux/mediatek/patches-5.15/805-thermal-drivers-mediatek-add-support-for-MT7986-and-.patch @@ -0,0 +1,284 @@ +From cd47d86ab09f1f3ec5c86441d4fe95e0cf597c06 Mon Sep 17 00:00:00 2001 +From: Daniel Golle <daniel@makrotopia.org> +Date: Tue, 13 Sep 2022 00:56:24 +0100 +Subject: [PATCH] thermal/drivers/mediatek: add support for MT7986 and MT7981 + +Add support for V3 generation thermal found in MT7986 and MT7981 SoCs. + +Signed-off-by: Daniel Golle <daniel@makrotopia.org> +--- + drivers/thermal/mtk_thermal.c | 202 +++++++++++++++++++++++++++++++++- + 1 file changed, 198 insertions(+), 4 deletions(-) + +--- a/drivers/thermal/mtk_thermal.c ++++ b/drivers/thermal/mtk_thermal.c +@@ -150,6 +150,21 @@ + #define CALIB_BUF1_VALID_V2(x) (((x) >> 4) & 0x1) + #define CALIB_BUF1_O_SLOPE_SIGN_V2(x) (((x) >> 3) & 0x1) + ++/* ++ * Layout of the fuses providing the calibration data ++ * These macros could be used for MT7981 and MT7986. ++ */ ++#define CALIB_BUF0_ADC_GE_V3(x) (((x) >> 0) & 0x3ff) ++#define CALIB_BUF0_ADC_OE_V3(x) (((x) >> 10) & 0x3ff) ++#define CALIB_BUF0_DEGC_CALI_V3(x) (((x) >> 20) & 0x3f) ++#define CALIB_BUF0_O_SLOPE_V3(x) (((x) >> 26) & 0x3f) ++#define CALIB_BUF1_VTS_TS1_V3(x) (((x) >> 0) & 0x1ff) ++#define CALIB_BUF1_VTS_TS2_V3(x) (((x) >> 21) & 0x1ff) ++#define CALIB_BUF1_VTS_TSABB_V3(x) (((x) >> 9) & 0x1ff) ++#define CALIB_BUF1_VALID_V3(x) (((x) >> 18) & 0x1) ++#define CALIB_BUF1_O_SLOPE_SIGN_V3(x) (((x) >> 19) & 0x1) ++#define CALIB_BUF1_ID_V3(x) (((x) >> 20) & 0x1) ++ + enum { + VTS1, + VTS2, +@@ -163,6 +178,7 @@ enum { + enum mtk_thermal_version { + MTK_THERMAL_V1 = 1, + MTK_THERMAL_V2, ++ MTK_THERMAL_V3, + }; + + /* MT2701 thermal sensors */ +@@ -245,6 +261,27 @@ enum mtk_thermal_version { + /* The calibration coefficient of sensor */ + #define MT8183_CALIBRATION 153 + ++/* AUXADC channel 11 is used for the temperature sensors */ ++#define MT7986_TEMP_AUXADC_CHANNEL 11 ++ ++/* The total number of temperature sensors in the MT7986 */ ++#define MT7986_NUM_SENSORS 1 ++ ++/* The number of banks in the MT7986 */ ++#define MT7986_NUM_ZONES 1 ++ ++/* The number of sensing points per bank */ ++#define MT7986_NUM_SENSORS_PER_ZONE 1 ++ ++/* MT7986 thermal sensors */ ++#define MT7986_TS1 0 ++ ++/* The number of controller in the MT7986 */ ++#define MT7986_NUM_CONTROLLER 1 ++ ++/* The calibration coefficient of sensor */ ++#define MT7986_CALIBRATION 165 ++ + struct mtk_thermal; + + struct thermal_bank_cfg { +@@ -279,6 +316,7 @@ struct mtk_thermal { + + struct clk *clk_peri_therm; + struct clk *clk_auxadc; ++ struct clk *clk_adc_32k; + /* lock: for getting and putting banks */ + struct mutex lock; + +@@ -386,6 +424,14 @@ static const int mt7622_mux_values[MT762 + static const int mt7622_vts_index[MT7622_NUM_SENSORS] = { VTS1 }; + static const int mt7622_tc_offset[MT7622_NUM_CONTROLLER] = { 0x0, }; + ++/* MT7986 thermal sensor data */ ++static const int mt7986_bank_data[MT7986_NUM_SENSORS] = { MT7986_TS1, }; ++static const int mt7986_msr[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, }; ++static const int mt7986_adcpnp[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, }; ++static const int mt7986_mux_values[MT7986_NUM_SENSORS] = { 0, }; ++static const int mt7986_vts_index[MT7986_NUM_SENSORS] = { VTS1 }; ++static const int mt7986_tc_offset[MT7986_NUM_CONTROLLER] = { 0x0, }; ++ + /* + * The MT8173 thermal controller has four banks. Each bank can read up to + * four temperature sensors simultaneously. The MT8173 has a total of 5 +@@ -549,6 +595,30 @@ static const struct mtk_thermal_data mt8 + .version = MTK_THERMAL_V1, + }; + ++/* ++ * MT7986 uses AUXADC Channel 11 for raw data access. ++ */ ++static const struct mtk_thermal_data mt7986_thermal_data = { ++ .auxadc_channel = MT7986_TEMP_AUXADC_CHANNEL, ++ .num_banks = MT7986_NUM_ZONES, ++ .num_sensors = MT7986_NUM_SENSORS, ++ .vts_index = mt7986_vts_index, ++ .cali_val = MT7986_CALIBRATION, ++ .num_controller = MT7986_NUM_CONTROLLER, ++ .controller_offset = mt7986_tc_offset, ++ .need_switch_bank = true, ++ .bank_data = { ++ { ++ .num_sensors = 1, ++ .sensors = mt7986_bank_data, ++ }, ++ }, ++ .msr = mt7986_msr, ++ .adcpnp = mt7986_adcpnp, ++ .sensor_mux_values = mt7986_mux_values, ++ .version = MTK_THERMAL_V3, ++}; ++ + /** + * raw_to_mcelsius - convert a raw ADC value to mcelsius + * @mt: The thermal controller +@@ -603,6 +673,22 @@ static int raw_to_mcelsius_v2(struct mtk + return (format_2 - tmp) * 100; + } + ++static int raw_to_mcelsius_v3(struct mtk_thermal *mt, int sensno, s32 raw) ++{ ++ s32 tmp; ++ ++ if (raw == 0) ++ return 0; ++ ++ raw &= 0xfff; ++ tmp = 100000 * 15 / 16 * 10000; ++ tmp /= 4096 - 512 + mt->adc_ge; ++ tmp /= 1490; ++ tmp *= raw - mt->vts[sensno] - 2900; ++ ++ return mt->degc_cali * 500 - tmp; ++} ++ + /** + * mtk_thermal_get_bank - get bank + * @bank: The bank +@@ -659,9 +745,12 @@ static int mtk_thermal_bank_temperature( + if (mt->conf->version == MTK_THERMAL_V1) { + temp = raw_to_mcelsius_v1( + mt, conf->bank_data[bank->id].sensors[i], raw); +- } else { ++ } else if (mt->conf->version == MTK_THERMAL_V2) { + temp = raw_to_mcelsius_v2( + mt, conf->bank_data[bank->id].sensors[i], raw); ++ } else { ++ temp = raw_to_mcelsius_v3( ++ mt, conf->bank_data[bank->id].sensors[i], raw); + } + + /* +@@ -887,6 +976,26 @@ static int mtk_thermal_extract_efuse_v2( + return 0; + } + ++static int mtk_thermal_extract_efuse_v3(struct mtk_thermal *mt, u32 *buf) ++{ ++ if (!CALIB_BUF1_VALID_V3(buf[1])) ++ return -EINVAL; ++ ++ mt->adc_oe = CALIB_BUF0_ADC_OE_V3(buf[0]); ++ mt->adc_ge = CALIB_BUF0_ADC_GE_V3(buf[0]); ++ mt->degc_cali = CALIB_BUF0_DEGC_CALI_V3(buf[0]); ++ mt->o_slope = CALIB_BUF0_O_SLOPE_V3(buf[0]); ++ mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V3(buf[1]); ++ mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V3(buf[1]); ++ mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V3(buf[1]); ++ mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V3(buf[1]); ++ ++ if (CALIB_BUF1_ID_V3(buf[1]) == 0) ++ mt->o_slope = 0; ++ ++ return 0; ++} ++ + static int mtk_thermal_get_calibration_data(struct device *dev, + struct mtk_thermal *mt) + { +@@ -897,6 +1006,7 @@ static int mtk_thermal_get_calibration_d + + /* Start with default values */ + mt->adc_ge = 512; ++ mt->adc_oe = 512; + for (i = 0; i < mt->conf->num_sensors; i++) + mt->vts[i] = 260; + mt->degc_cali = 40; +@@ -924,8 +1034,10 @@ static int mtk_thermal_get_calibration_d + + if (mt->conf->version == MTK_THERMAL_V1) + ret = mtk_thermal_extract_efuse_v1(mt, buf); +- else ++ else if (mt->conf->version == MTK_THERMAL_V2) + ret = mtk_thermal_extract_efuse_v2(mt, buf); ++ else ++ ret = mtk_thermal_extract_efuse_v3(mt, buf); + + if (ret) { + dev_info(dev, "Device not calibrated, using default calibration values\n"); +@@ -956,6 +1068,10 @@ static const struct of_device_id mtk_the + .data = (void *)&mt7622_thermal_data, + }, + { ++ .compatible = "mediatek,mt7986-thermal", ++ .data = (void *)&mt7986_thermal_data, ++ }, ++ { + .compatible = "mediatek,mt8183-thermal", + .data = (void *)&mt8183_thermal_data, + }, { +@@ -1009,6 +1125,12 @@ static int mtk_thermal_probe(struct plat + if (IS_ERR(mt->clk_auxadc)) + return PTR_ERR(mt->clk_auxadc); + ++ if (mt->conf->version == MTK_THERMAL_V3) { ++ mt->clk_adc_32k = devm_clk_get(&pdev->dev, "adc_32k"); ++ if (IS_ERR(mt->clk_adc_32k)) ++ return PTR_ERR(mt->clk_adc_32k); ++ } ++ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + mt->thermal_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(mt->thermal_base)) +@@ -1058,10 +1180,18 @@ static int mtk_thermal_probe(struct plat + if (ret) + return ret; + ++ if (mt->conf->version == MTK_THERMAL_V3) { ++ ret = clk_prepare_enable(mt->clk_adc_32k); ++ if (ret) { ++ dev_err(&pdev->dev, "Can't enable auxadc 32k clk: %d\n", ret); ++ return ret; ++ } ++ } ++ + ret = clk_prepare_enable(mt->clk_auxadc); + if (ret) { + dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret); +- return ret; ++ goto err_disable_clk_adc_32k; + } + + ret = clk_prepare_enable(mt->clk_peri_therm); +@@ -1070,7 +1200,8 @@ static int mtk_thermal_probe(struct plat + goto err_disable_clk_auxadc; + } + +- if (mt->conf->version == MTK_THERMAL_V2) { ++ if (mt->conf->version == MTK_THERMAL_V2 || ++ mt->conf->version == MTK_THERMAL_V3) { + mtk_thermal_turn_on_buffer(apmixed_base); + mtk_thermal_release_periodic_ts(mt, auxadc_base); + } +@@ -1099,6 +1230,9 @@ err_disable_clk_peri_therm: + clk_disable_unprepare(mt->clk_peri_therm); + err_disable_clk_auxadc: + clk_disable_unprepare(mt->clk_auxadc); ++err_disable_clk_adc_32k: ++ if (mt->conf->version == MTK_THERMAL_V3) ++ clk_disable_unprepare(mt->clk_adc_32k); + + return ret; + } +@@ -1110,6 +1244,9 @@ static int mtk_thermal_remove(struct pla + clk_disable_unprepare(mt->clk_peri_therm); + clk_disable_unprepare(mt->clk_auxadc); + ++ if (mt->conf->version == MTK_THERMAL_V3) ++ clk_disable_unprepare(mt->clk_adc_32k); ++ + return 0; + } + |