diff options
11 files changed, 805 insertions, 8 deletions
diff --git a/target/linux/mediatek/base-files/etc/board.d/02_network b/target/linux/mediatek/base-files/etc/board.d/02_network index 8015cf3cc2..faa2434241 100755 --- a/target/linux/mediatek/base-files/etc/board.d/02_network +++ b/target/linux/mediatek/base-files/etc/board.d/02_network @@ -13,9 +13,21 @@ mediatek_setup_interfaces() ucidef_set_interface_lan "lan0 lan1 lan2 lan3" ucidef_set_interface_wan eth1 ;; - 'bananapi,bpi-r2') - ucidef_set_interface_lan "lan0 lan1 lan2 lan3" - ucidef_set_interface_wan wan + 'bananapi,bpi-r2'|\ + "unielec,u7623"*) + ucidef_set_interfaces_lan_wan "lan0 lan1 lan2 lan3" "wan" + ;; + esac +} + +mediatek_setup_macs() +{ + local board="$1" + + case $board in + "unielec,u7623"*) + mac=$(cat /sys/class/net/wan/address) + ucidef_set_interface_macaddr "wan" $mac ;; esac } @@ -23,6 +35,7 @@ mediatek_setup_interfaces() board_config_update board=$(board_name) mediatek_setup_interfaces $board +mediatek_setup_macs $board board_config_flush exit 0 diff --git a/target/linux/mediatek/base-files/lib/preinit/07_set_iface_mac b/target/linux/mediatek/base-files/lib/preinit/07_set_iface_mac new file mode 100644 index 0000000000..3d04000738 --- /dev/null +++ b/target/linux/mediatek/base-files/lib/preinit/07_set_iface_mac @@ -0,0 +1,47 @@ +#!/bin/sh +# Copyright (C) 2018 OpenWrt.org + +RECOVERY_PART=/dev/mmcblk0p1 + +preinit_set_mac_address() { + local mac + + . /lib/functions.sh + . /lib/functions/system.sh + + case $(board_name) in + "unielec,u7623"*) + if [ -b $RECOVERY_PART ]; then + insmod nls_cp437 + insmod nls_iso8859-1 + insmod fat + insmod vfat + mkdir -p /tmp/recovery + mount -o rw,noatime $RECOVERY_PART /tmp/recovery + + if [ -f "/tmp/recovery/mac_addr" ]; + then + mac=$(cat /tmp/recovery/mac_addr) + else + mac=$(cat /sys/class/net/eth0/address) + echo "$mac" > /tmp/recovery/mac_addr + fi + + sync + umount /tmp/recovery + rm -rf /tmp/recovery + fi + + ip link set dev wan address $mac 2> /dev/null + + mac=$(macaddr_add $mac 1) + + ip link set dev lan0 address $mac 2>/dev/null + ip link set dev lan1 address $mac 2>/dev/null + ip link set dev lan2 address $mac 2>/dev/null + ip link set dev lan3 address $mac 2>/dev/null + ;; + esac +} + +boot_hook_add preinit_main preinit_set_mac_address diff --git a/target/linux/mediatek/base-files/lib/preinit/79_move_config b/target/linux/mediatek/base-files/lib/preinit/79_move_config new file mode 100644 index 0000000000..e8e62883dc --- /dev/null +++ b/target/linux/mediatek/base-files/lib/preinit/79_move_config @@ -0,0 +1,19 @@ +#!/bin/sh +# Copyright (C) 2015 OpenWrt.org + +RECOVERY_PART=/dev/mmcblk0p1 + +move_config() { + if [ -b $RECOVERY_PART ]; then + insmod nls_cp437 + insmod nls_iso8859-1 + insmod fat + insmod vfat + mkdir -p /recovery + mount -o rw,noatime $RECOVERY_PART /recovery + [ -f /recovery/sysupgrade.tgz ] && mv -f /recovery/sysupgrade.tgz / + umount /recovery + fi +} + +boot_hook_add preinit_mount_root move_config diff --git a/target/linux/mediatek/base-files/lib/upgrade/platform.sh b/target/linux/mediatek/base-files/lib/upgrade/platform.sh index 646ce0dc53..487a262dc2 100755 --- a/target/linux/mediatek/base-files/lib/upgrade/platform.sh +++ b/target/linux/mediatek/base-files/lib/upgrade/platform.sh @@ -1,6 +1,28 @@ platform_do_upgrade() { - default_do_upgrade "$ARGV" -} + local board=$(board_name) + case "$board" in + "unielec,u7623"*) + #Keep the persisten random mac address (if it exists) + mkdir -p /tmp/recovery + mount -o rw,noatime /dev/mmcblk0p1 /tmp/recovery + [ -f "/tmp/recovery/mac_addr" ] && \ + mv -f /tmp/recovery/mac_addr /tmp/ + umount /tmp/recovery + + #1310720 is the offset in bytes from the start of eMMC and to + #the location of the kernel (2560 512 byte sectors) + get_image "$1" | dd of=/dev/mmcblk0 bs=1310720 seek=1 conv=fsync + + mount -o rw,noatime /dev/mmcblk0p1 /tmp/recovery + [ -f "/tmp/mac_addr" ] && mv -f /tmp/mac_addr /tmp/recovery + sync + umount /tmp/recovery + ;; + *) + default_do_upgrade "$ARGV" + ;; + esac +} PART_NAME=firmware @@ -11,7 +33,8 @@ platform_check_image() { [ "$#" -gt 1 ] && return 1 case "$board" in - bananapi,bpi-r2) + bananapi,bpi-r2|\ + "unielec,u7623"*) [ "$magic" != "27051956" ] && { echo "Invalid image type." return 1 @@ -26,4 +49,20 @@ platform_check_image() { esac return 0 -} +} + +platform_copy_config_emmc() { + mkdir -p /recovery + mount -o rw,noatime /dev/mmcblk0p1 /recovery + cp -af "$CONF_TAR" /recovery/ + sync + umount /recovery +} + +platform_copy_config() { + case "$(board_name)" in + "unielec,u7623"*) + platform_copy_config_emmc + ;; + esac +} diff --git a/target/linux/mediatek/image/Makefile b/target/linux/mediatek/image/Makefile index 6659d446d0..5e2b2c6d0a 100644 --- a/target/linux/mediatek/image/Makefile +++ b/target/linux/mediatek/image/Makefile @@ -22,6 +22,16 @@ define Build/dtb $(CP) $(DEVICE_DTS_DIR)/$(DEVICE_DTS).dtb $(BIN_DIR)/ endef +define Build/sysupgrade-emmc + rm -f $@.recovery + mkfs.fat -C $@.recovery 3070 + + ./gen_mt7623_emmc_img.sh $@ \ + $(IMAGE_KERNEL) \ + $@.recovery \ + $(IMAGE_ROOTFS) +endef + # default all platform image(fit) build define Device/Default PROFILES = Default $$(DEVICE_NAME) diff --git a/target/linux/mediatek/image/gen_mt7623_emmc_img.sh b/target/linux/mediatek/image/gen_mt7623_emmc_img.sh new file mode 100755 index 0000000000..1cb0883fb0 --- /dev/null +++ b/target/linux/mediatek/image/gen_mt7623_emmc_img.sh @@ -0,0 +1,18 @@ +#!/usr/bin/env bash + +OUTPUT_FILE=$1 +KERNEL_FILE=$2 +RECOVERY_FILE=$3 +ROOTFS_FILE=$4 + +BS=512 + +#These to offsets are relative to the absolute location of the kernel on the mmc +#(0xA00), so their position in the image is -2560 blocks +RECOVERY_OFFSET=67072 +ROOTFS_OFFSET=87552 + +dd bs="$BS" of="$OUTPUT_FILE" if="$KERNEL_FILE" +dd bs="$BS" of="$OUTPUT_FILE" if="$RECOVERY_FILE" seek="$RECOVERY_OFFSET" +dd bs="$BS" of="$OUTPUT_FILE" if="$ROOTFS_FILE" seek="$ROOTFS_OFFSET" +dd if=/dev/zero of="$OUTPUT_FILE" bs=128k count=1 oflag=append conv=notrunc diff --git a/target/linux/mediatek/image/mt7623.mk b/target/linux/mediatek/image/mt7623.mk index ddb4faa480..fa6774e783 100644 --- a/target/linux/mediatek/image/mt7623.mk +++ b/target/linux/mediatek/image/mt7623.mk @@ -1,3 +1,14 @@ +define Device/7623a-unielec-u7623-02-emmc-512m + DEVICE_TITLE := MTK7623a UniElec U7623-02 (eMMC/512MB RAM) + DEVICE_DTS := mt7623a-unielec-u7623-02-emmc-512M + DEVICE_PACKAGES := mkf2fs e2fsprogs kmod-fs-vfat kmod-nls-cp437 kmod-nls-iso8859-1 kmod-mmc + SUPPORTED_DEVICES := unielec,u7623-02-emmc-512m + IMAGES := sysupgrade-emmc.bin.gz + IMAGE/sysupgrade-emmc.bin.gz := sysupgrade-emmc | gzip | append-metadata +endef + +TARGET_DEVICES += 7623a-unielec-u7623-02-emmc-512m + define Device/7623n-bananapi-bpi-r2 DEVICE_TITLE := MTK7623n BananaPi R2 DEVICE_DTS := mt7623n-bananapi-bpi-r2 diff --git a/target/linux/mediatek/mt7623/config-4.14 b/target/linux/mediatek/mt7623/config-4.14 index 9f70989410..0437740467 100644 --- a/target/linux/mediatek/mt7623/config-4.14 +++ b/target/linux/mediatek/mt7623/config-4.14 @@ -51,6 +51,7 @@ CONFIG_ARM_UNWIND=y CONFIG_ARM_VIRT_EXT=y CONFIG_ATAGS=y CONFIG_AUTO_ZRELADDR=y +CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_MQ_PCI=y CONFIG_BOUNCE=y # CONFIG_CACHE_L2X0 is not set @@ -114,6 +115,8 @@ CONFIG_CROSS_MEMORY_ATTACH=y CONFIG_CRYPTO_ACOMP2=y CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_CRC32=y +CONFIG_CRYPTO_CRC32C=y CONFIG_CRYPTO_CTR=y CONFIG_CRYPTO_DEFLATE=y CONFIG_CRYPTO_DEV_MEDIATEK=y @@ -165,9 +168,16 @@ CONFIG_EARLY_PRINTK=y CONFIG_EDAC_ATOMIC_SCRUB=y CONFIG_EDAC_SUPPORT=y CONFIG_ELF_CORE=y +CONFIG_EXT4_FS=y +# CONFIG_F2FS_CHECK_FS is not set +CONFIG_F2FS_FS=y +# CONFIG_F2FS_FS_SECURITY is not set +CONFIG_F2FS_FS_XATTR=y +CONFIG_F2FS_STAT_FS=y CONFIG_FIXED_PHY=y CONFIG_FIX_EARLYCON_MEM=y CONFIG_FREEZER=y +CONFIG_FS_MBCACHE=y CONFIG_GENERIC_ALLOCATOR=y CONFIG_GENERIC_BUG=y CONFIG_GENERIC_CLOCKEVENTS=y @@ -269,6 +279,7 @@ CONFIG_IRQ_DOMAIN=y CONFIG_IRQ_DOMAIN_HIERARCHY=y CONFIG_IRQ_FORCED_THREADING=y CONFIG_IRQ_WORK=y +CONFIG_JBD2=y CONFIG_KALLSYMS=y CONFIG_LEDS_MT6323=y CONFIG_LIBFDT=y @@ -472,7 +483,6 @@ CONFIG_UNINLINE_SPIN_UNLOCK=y CONFIG_USB=y CONFIG_USB_COMMON=y # CONFIG_USB_EHCI_HCD is not set -# CONFIG_USB_MTU3 is not set CONFIG_USB_SUPPORT=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_MTK=y diff --git a/target/linux/mediatek/patches-4.14/0225-arm-dts-Add-missing-mt7623-pcie-nodes.patch b/target/linux/mediatek/patches-4.14/0225-arm-dts-Add-missing-mt7623-pcie-nodes.patch new file mode 100644 index 0000000000..b87f95c1f9 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0225-arm-dts-Add-missing-mt7623-pcie-nodes.patch @@ -0,0 +1,128 @@ +From d31800ff6ed81f44488b590fe372e7b6572d2896 Mon Sep 17 00:00:00 2001 +From: Kristian Evensen <kristian.evensen@gmail.com> +Date: Sun, 17 Jun 2018 14:18:45 +0200 +Subject: [PATCH] arm: dts: Add missing mt7623 pcie nodes + +--- + arch/arm/boot/dts/mt7623.dtsi | 105 ++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 105 insertions(+) + +diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi +index 36983a7d7..714245365 100644 +--- a/arch/arm/boot/dts/mt7623.dtsi ++++ b/arch/arm/boot/dts/mt7623.dtsi +@@ -669,6 +669,111 @@ + #reset-cells = <1>; + }; + ++ pcie: pcie@1a140000 { ++ compatible = "mediatek,mt7623-pcie"; ++ device_type = "pci"; ++ reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */ ++ <0 0x1a142000 0 0x1000>, /* Port0 registers */ ++ <0 0x1a143000 0 0x1000>, /* Port1 registers */ ++ <0 0x1a144000 0 0x1000>; /* Port2 registers */ ++ reg-names = "subsys", "port0", "port1", "port2"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0xf800 0 0 0>; ++ interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>, ++ <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>, ++ <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; ++ clocks = <&topckgen CLK_TOP_ETHIF_SEL>, ++ <&hifsys CLK_HIFSYS_PCIE0>, ++ <&hifsys CLK_HIFSYS_PCIE1>, ++ <&hifsys CLK_HIFSYS_PCIE2>; ++ clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2"; ++ resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>, ++ <&hifsys MT2701_HIFSYS_PCIE1_RST>, ++ <&hifsys MT2701_HIFSYS_PCIE2_RST>; ++ reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2"; ++ phys = <&pcie0_port PHY_TYPE_PCIE>, ++ <&pcie1_port PHY_TYPE_PCIE>, ++ <&u3port1 PHY_TYPE_PCIE>; ++ phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2"; ++ power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; ++ bus-range = <0x00 0xff>; ++ status = "disabled"; ++ ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 ++ 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; ++ ++ pcie@0,0 { ++ reg = <0x0000 0 0 0 0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 0>; ++ interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; ++ ranges; ++ num-lanes = <1>; ++ status = "disabled"; ++ }; ++ pcie@1,0 { ++ reg = <0x0800 0 0 0 0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 0>; ++ interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; ++ ranges; ++ num-lanes = <1>; ++ status = "disabled"; ++ }; ++ ++ pcie@2,0 { ++ reg = <0x1000 0 0 0 0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 0>; ++ interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; ++ ranges; ++ num-lanes = <1>; ++ status = "disabled"; ++ }; ++ }; ++ ++ pcie0_phy: pcie-phy@1a149000 { ++ compatible = "mediatek,generic-tphy-v1"; ++ reg = <0 0x1a149000 0 0x0700>; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ status = "disabled"; ++ ++ pcie0_port: pcie-phy@1a149900 { ++ reg = <0 0x1a149900 0 0x0700>; ++ clocks = <&clk26m>; ++ clock-names = "ref"; ++ #phy-cells = <1>; ++ status = "okay"; ++ }; ++ }; ++ ++ pcie1_phy: pcie-phy@1a14a000 { ++ compatible = "mediatek,generic-tphy-v1"; ++ reg = <0 0x1a14a000 0 0x0700>; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ status = "disabled"; ++ ++ pcie1_port: pcie-phy@1a14a900 { ++ reg = <0 0x1a14a900 0 0x0700>; ++ clocks = <&clk26m>; ++ clock-names = "ref"; ++ #phy-cells = <1>; ++ status = "okay"; ++ }; ++ }; ++ ++ + usb1: usb@1a1c0000 { + compatible = "mediatek,mt7623-xhci", + "mediatek,mt8173-xhci"; +-- +2.14.1 + diff --git a/target/linux/mediatek/patches-4.14/0226-phy-phy-mtk-tphy-Add-hifsys-support.patch b/target/linux/mediatek/patches-4.14/0226-phy-phy-mtk-tphy-Add-hifsys-support.patch new file mode 100644 index 0000000000..1ac15bdb72 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0226-phy-phy-mtk-tphy-Add-hifsys-support.patch @@ -0,0 +1,71 @@ +From 28f9a5e2a3f5441ab5594669ed82da11e32277a9 Mon Sep 17 00:00:00 2001 +From: Kristian Evensen <kristian.evensen@gmail.com> +Date: Mon, 30 Apr 2018 14:38:01 +0200 +Subject: [PATCH] phy: phy-mtk-tphy: Add hifsys-support + +--- + drivers/phy/mediatek/phy-mtk-tphy.c | 20 ++++++++++++++++++++ + 1 file changed, 20 insertions(+) + +diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c +index 721a2a1c9..0cb1cea53 100644 +--- a/drivers/phy/mediatek/phy-mtk-tphy.c ++++ b/drivers/phy/mediatek/phy-mtk-tphy.c +@@ -22,6 +22,8 @@ + #include <linux/of_address.h> + #include <linux/phy/phy.h> + #include <linux/platform_device.h> ++#include <linux/mfd/syscon.h> ++#include <linux/regmap.h> + + /* version V1 sub-banks offset base address */ + /* banks shared by multiple phys */ +@@ -259,6 +261,9 @@ + #define RG_CDR_BIRLTD0_GEN3_MSK GENMASK(4, 0) + #define RG_CDR_BIRLTD0_GEN3_VAL(x) (0x1f & (x)) + ++#define HIF_SYSCFG1 0x14 ++#define HIF_SYSCFG1_PHY2_MASK (0x3 << 20) ++ + enum mtk_phy_version { + MTK_PHY_V1 = 1, + MTK_PHY_V2, +@@ -302,6 +307,7 @@ struct mtk_tphy { + struct clk *u3phya_ref; /* reference clock of usb3 anolog phy */ + const struct mtk_phy_pdata *pdata; + struct mtk_phy_instance **phys; ++ struct regmap *hif; + int nphys; + }; + +@@ -594,6 +600,10 @@ static void pcie_phy_instance_init(struct mtk_tphy *tphy, + if (tphy->pdata->version != MTK_PHY_V1) + return; + ++ if (tphy->hif) ++ regmap_update_bits(tphy->hif, HIF_SYSCFG1, ++ HIF_SYSCFG1_PHY2_MASK, 0); ++ + tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG0); + tmp &= ~(P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H); + tmp |= P3A_RG_XTAL_EXT_PE1H_VAL(0x2) | P3A_RG_XTAL_EXT_PE2H_VAL(0x2); +@@ -1008,6 +1018,16 @@ static int mtk_tphy_probe(struct platform_device *pdev) + tphy->u3phya_ref = NULL; + } + ++ if (of_find_property(np, "mediatek,phy-switch", NULL)) { ++ tphy->hif = syscon_regmap_lookup_by_phandle(np, ++ "mediatek,phy-switch"); ++ if (IS_ERR(tphy->hif)) { ++ dev_err(&pdev->dev, ++ "missing \"mediatek,phy-switch\" phandle\n"); ++ return PTR_ERR(tphy->hif); ++ } ++ } ++ + port = 0; + for_each_child_of_node(np, child_np) { + struct mtk_phy_instance *instance; +-- +2.14.1 + diff --git a/target/linux/mediatek/patches-4.14/0227-arm-dts-Add-Unielec-U7623-DTS.patch b/target/linux/mediatek/patches-4.14/0227-arm-dts-Add-Unielec-U7623-DTS.patch new file mode 100644 index 0000000000..9d554da0be --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0227-arm-dts-Add-Unielec-U7623-DTS.patch @@ -0,0 +1,431 @@ +From 0c88c72bf130c9276958dc6f595ea473ea357a75 Mon Sep 17 00:00:00 2001 +From: Kristian Evensen <kristian.evensen@gmail.com> +Date: Sun, 17 Jun 2018 14:41:47 +0200 +Subject: [PATCH] arm: dts: Add Unielec U7623 DTS + +--- + arch/arm/boot/dts/Makefile | 1 + + .../dts/mt7623a-unielec-u7623-02-emmc-512M.dts | 17 + + .../boot/dts/mt7623a-unielec-u7623-02-emmc.dtsi | 374 +++++++++++++++++++++ + 3 files changed, 392 insertions(+) + create mode 100644 arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc-512M.dts + create mode 100644 arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc.dtsi + +diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile +index 3fec84fa0..e685ce9a4 100644 +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -1062,6 +1062,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ + mt6589-aquaris5.dtb \ + mt6592-evb.dtb \ + mt7623a-rfb-emmc.dtb \ ++ mt7623a-unielec-u7623-02-emmc-512M.dtb \ + mt7623n-rfb-nand.dtb \ + mt7623n-bananapi-bpi-r2.dtb \ + mt8127-moose.dtb \ +diff --git a/arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc-512M.dts b/arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc-512M.dts +new file mode 100644 +index 000000000..3b14eccd3 +--- /dev/null ++++ b/arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc-512M.dts +@@ -0,0 +1,17 @@ ++/* ++ * Copyright 2018 Kristian Evensen <kristian.evensen@gmail.com> ++ * ++ * SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ */ ++ ++/dts-v1/; ++#include "mt7623a-unielec-u7623-02-emmc.dtsi" ++ ++/ { ++ model = "UniElec U7623-02 eMMC (512M RAM)"; ++ compatible = "unielec,u7623-02-emmc-512m", "unielec,u7623-02-emmc", "mediatek,mt7623"; ++ ++ memory { ++ reg = <0 0x80000000 0 0x20000000>; ++ }; ++}; +diff --git a/arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc.dtsi b/arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc.dtsi +new file mode 100644 +index 000000000..4fc8ce8a9 +--- /dev/null ++++ b/arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc.dtsi +@@ -0,0 +1,374 @@ ++/* ++ * Copyright 2018 Kristian Evensen <kristian.evensen@gmail.com> ++ * ++ * SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ */ ++ ++#include <dt-bindings/input/input.h> ++#include "mt7623.dtsi" ++#include "mt6323.dtsi" ++ ++/ { ++ compatible = "unielec,u7623-02-emmc", "mediatek,mt7623"; ++ ++ aliases { ++ serial2 = &uart2; ++ }; ++ ++ chosen { ++ bootargs = "root=/dev/mmcblk0p2 rootfstype=squashfs,f2fs"; ++ stdout-path = "serial2:115200n8"; ++ }; ++ ++ memory { ++ reg = <0 0x80000000 0 0x20000000>; ++ }; ++ ++ cpus { ++ cpu@0 { ++ proc-supply = <&mt6323_vproc_reg>; ++ }; ++ ++ cpu@1 { ++ proc-supply = <&mt6323_vproc_reg>; ++ }; ++ ++ cpu@2 { ++ proc-supply = <&mt6323_vproc_reg>; ++ }; ++ ++ cpu@3 { ++ proc-supply = <&mt6323_vproc_reg>; ++ }; ++ }; ++ ++ reg_1p8v: regulator-1p8v { ++ compatible = "regulator-fixed"; ++ regulator-name = "fixed-1.8V"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ reg_3p3v: regulator-3p3v { ++ compatible = "regulator-fixed"; ++ regulator-name = "fixed-3.3V"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ reg_5v: regulator-5v { ++ compatible = "regulator-fixed"; ++ regulator-name = "fixed-5V"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&key_pins_a>; ++ ++ factory { ++ label = "factory"; ++ linux,code = <KEY_RESTART>; ++ gpios = <&pio 256 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&led_pins_unielec>; ++ ++ led3 { ++ label = "u7623-01:green:led3"; ++ gpios = <&pio 14 GPIO_ACTIVE_LOW>; ++ default-state = "off"; ++ }; ++ ++ led4 { ++ label = "u7623-01:green:led4"; ++ gpios = <&pio 15 GPIO_ACTIVE_LOW>; ++ default-state = "off"; ++ }; ++ }; ++ ++ memory@80000000 { ++ reg = <0 0x80000000 0 0x40000000>; ++ }; ++ ++ mt7530: switch@0 { ++ compatible = "mediatek,mt7530"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++}; ++ ++&crypto { ++ status = "okay"; ++}; ++ ++ð { ++ status = "okay"; ++ ++ gmac0: mac@0 { ++ compatible = "mediatek,eth-mac"; ++ reg = <0>; ++ phy-mode = "trgmii"; ++ ++ fixed-link { ++ speed = <1000>; ++ full-duplex; ++ pause; ++ }; ++ }; ++ ++ mdio: mdio-bus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ phy5: ethernet-phy@5 { ++ reg = <5>; ++ phy-mode = "rgmii-rxid"; ++ }; ++ }; ++}; ++ ++&mt7530 { ++ compatible = "mediatek,mt7530"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0>; ++ pinctrl-names = "default"; ++ mediatek,mcm; ++ resets = <ðsys 2>; ++ reset-names = "mcm"; ++ core-supply = <&mt6323_vpa_reg>; ++ io-supply = <&mt6323_vemc3v3_reg>; ++ ++ dsa,mii-bus = <&mdio>; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0>; ++ ++ port@0 { ++ reg = <0>; ++ label = "lan0"; ++ cpu = <&cpu_port0>; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ label = "lan1"; ++ cpu = <&cpu_port0>; ++ }; ++ ++ port@2 { ++ reg = <2>; ++ label = "lan2"; ++ cpu = <&cpu_port0>; ++ }; ++ ++ port@3 { ++ reg = <3>; ++ label = "lan3"; ++ cpu = <&cpu_port0>; ++ }; ++ ++ port@4 { ++ reg = <4>; ++ label = "wan"; ++ cpu = <&cpu_port0>; ++ }; ++ ++ cpu_port0: port@6 { ++ reg = <6>; ++ label = "cpu"; ++ ethernet = <&gmac0>; ++ phy-mode = "trgmii"; ++ ++ fixed-link { ++ speed = <1000>; ++ full-duplex; ++ }; ++ }; ++ }; ++}; ++ ++&mmc0 { ++ pinctrl-names = "default", "state_uhs"; ++ pinctrl-0 = <&mmc0_pins_default>; ++ pinctrl-1 = <&mmc0_pins_uhs>; ++ status = "okay"; ++ bus-width = <8>; ++ max-frequency = <50000000>; ++ cap-mmc-highspeed; ++ vmmc-supply = <®_3p3v>; ++ vqmmc-supply = <®_1p8v>; ++ non-removable; ++}; ++ ++&pio { ++ key_pins_a: keys-alt { ++ pins-keys { ++ pinmux = <MT7623_PIN_256_GPIO256_FUNC_GPIO256>, ++ <MT7623_PIN_257_GPIO257_FUNC_GPIO257>; ++ input-enable; ++ }; ++ }; ++ ++ led_pins_unielec: leds-unielec { ++ pins-leds { ++ pinmux = <MT7623_PIN_14_GPIO14_FUNC_GPIO14>, ++ <MT7623_PIN_15_GPIO15_FUNC_GPIO15>; ++ }; ++ }; ++ ++ mmc0_pins_default: mmc0default { ++ pins_cmd_dat { ++ pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>, ++ <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>, ++ <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>, ++ <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>, ++ <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>, ++ <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>, ++ <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>, ++ <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>, ++ <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>; ++ input-enable; ++ bias-pull-up; ++ }; ++ ++ pins_clk { ++ pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>; ++ bias-pull-down; ++ }; ++ ++ pins_rst { ++ pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>; ++ bias-pull-up; ++ }; ++ }; ++ ++ mmc0_pins_uhs: mmc0 { ++ pins_cmd_dat { ++ pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>, ++ <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>, ++ <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>, ++ <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>, ++ <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>, ++ <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>, ++ <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>, ++ <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>, ++ <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>; ++ input-enable; ++ drive-strength = <MTK_DRIVE_2mA>; ++ bias-pull-up = <MTK_PUPD_SET_R1R0_01>; ++ }; ++ ++ pins_clk { ++ pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>; ++ drive-strength = <MTK_DRIVE_2mA>; ++ bias-pull-down = <MTK_PUPD_SET_R1R0_01>; ++ }; ++ ++ pins_rst { ++ pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>; ++ bias-pull-up; ++ }; ++ }; ++ ++ pwm_pins_a: pwm@0 { ++ pins_pwm { ++ pinmux = <MT7623_PIN_203_PWM0_FUNC_PWM0>, ++ <MT7623_PIN_204_PWM1_FUNC_PWM1>, ++ <MT7623_PIN_205_PWM2_FUNC_PWM2>, ++ <MT7623_PIN_206_PWM3_FUNC_PWM3>, ++ <MT7623_PIN_207_PWM4_FUNC_PWM4>; ++ }; ++ }; ++ ++ uart2_pins_b: uart@2 { ++ pins_dat { ++ pinmux = <MT7623_PIN_200_URXD2_FUNC_URXD2>, ++ <MT7623_PIN_201_UTXD2_FUNC_UTXD2>; ++ }; ++ }; ++ ++ pcie_default: pcie_pin_default { ++ pins_cmd_dat { ++ pinmux = <MT7623_PIN_208_AUD_EXT_CK1_FUNC_PCIE0_PERST_N>, ++ <MT7623_PIN_209_AUD_EXT_CK2_FUNC_PCIE1_PERST_N>; ++ bias-disable; ++ }; ++ }; ++}; ++ ++&pwm { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm_pins_a>; ++ status = "okay"; ++}; ++ ++&pwrap { ++ mt6323 { ++ mt6323led: led { ++ compatible = "mediatek,mt6323-led"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ led@0 { ++ reg = <0>; ++ label = "led0"; ++ default-state = "off"; ++ }; ++ }; ++ }; ++}; ++ ++&uart2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart2_pins_b>; ++ status = "okay"; ++}; ++ ++&usb1 { ++ vusb33-supply = <®_3p3v>; ++ vbus-supply = <®_3p3v>; ++ status = "okay"; ++}; ++ ++&u3phy1 { ++ status = "okay"; ++}; ++ ++&u3phy2 { ++ status = "okay"; ++ mediatek,phy-switch = <&hifsys>; ++}; ++ ++&pcie { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie_default>; ++ status = "okay"; ++ ++ pcie@1,0 { ++ status = "okay"; ++ }; ++ ++ pcie@2,0 { ++ status = "okay"; ++ }; ++}; ++ ++&pcie1_phy { ++ status = "okay"; ++}; ++ +-- +2.14.1 + |