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| author | Felix Fietkau <nbd@openwrt.org> | 2015-09-11 16:32:45 +0000 |
|---|---|---|
| committer | Felix Fietkau <nbd@openwrt.org> | 2015-09-11 16:32:45 +0000 |
| commit | bc4f2c5ce4fa70444f5f59a23852fc81e4c092bb (patch) | |
| tree | 166747c55981286ad33fd105d3962c5933f6c199 /tools/mtd-utils | |
| parent | b7933a47bb8ef485fe503425a817780905372068 (diff) | |
| download | upstream-bc4f2c5ce4fa70444f5f59a23852fc81e4c092bb.tar.gz upstream-bc4f2c5ce4fa70444f5f59a23852fc81e4c092bb.tar.bz2 upstream-bc4f2c5ce4fa70444f5f59a23852fc81e4c092bb.zip | |
ar71xx: fix ar724x clock calculation
According to the AR7242 datasheet section 2.8, AR724X CPUs use a 40MHz
input clock as the REF_CLK instead of 5MHz.
The correct CPU PLL calculation procedure is as follows:
CPU_PLL = (DIV * REF_CLK) / REF_DIV / 2.
This patch is compatible with the current calculation procedure with default
DIV and REF_DIV values.
Test on both AR7240, AR7241 and AR7242.
Signed-off-by: Weijie Gao <hackpascal@gmail.com>
SVN-Revision: 46856
Diffstat (limited to 'tools/mtd-utils')
0 files changed, 0 insertions, 0 deletions