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| author | Rosen Penev <rosenp@gmail.com> | 2017-12-04 11:40:23 -0800 |
|---|---|---|
| committer | Felix Fietkau <nbd@nbd.name> | 2018-02-05 10:16:25 +0100 |
| commit | 4e03a742e0e59a0b996196500d06bb72ff224c02 (patch) | |
| tree | 13461e741e0212465067e2c9565bfd93b999b725 /toolchain/uClibc/config/mips64el | |
| parent | cde71a543c629f63e6f01850fd8b6f3f94cdd25d (diff) | |
| download | upstream-4e03a742e0e59a0b996196500d06bb72ff224c02.tar.gz upstream-4e03a742e0e59a0b996196500d06bb72ff224c02.tar.bz2 upstream-4e03a742e0e59a0b996196500d06bb72ff224c02.zip | |
ag71xx: Reorder ag71xx struct members for better cache performance
Qualcomm claims this improves the D-cache footprint. Origina commit message below:
From: Ben Menchaca <ben.menchaca@qca.qualcomm.com>
Date: Fri, 7 Jun 2013 10:57:28 -0500
Subject: [ag71xx] cluster/align structs for cache perf
Cluster the frequently used, per-packet structures in ag71xx near
to each other, and cacheline-align them. Some other re-ordering
occurred to move "warmer" structures near the per-packet structures.
Signed-off-by: Ben Menchaca <ben.menchaca@qca.qualcomm.com>
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Diffstat (limited to 'toolchain/uClibc/config/mips64el')
0 files changed, 0 insertions, 0 deletions