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authorPavel Kubelun <be.dissent@gmail.com>2018-01-18 19:45:15 +0300
committerJohn Crispin <john@phrozen.org>2018-05-22 20:34:14 +0200
commit7f694ef3d9f1121c03935c330093c594b8437098 (patch)
treeeb078f0a51483ebf6f2250754b82058d3d275fa7 /target
parent7a4f9c5993a726a3009a93dcd6aacb93d2aea6e1 (diff)
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ipq806x: fix EA8500 switch control
EA8500 has pcie2 slot unequipped. By EA8500 hw design default pcie2 reset gpio (gpio63) is used to reset the switch. That's why enabling pcie2 brings the switch into a working state. So let's just control the gpio63 without enabling the pcie2 slot. We have to remove the pcie2_pins node so the gpio63 is not defined twice. Because pcie2 node has a reference to pcie2_pins we have to remove it as well. Signed-off-by: Pavel Kubelun <be.dissent@gmail.com> [slh: rebase for kernel v4.14 as well] Signed-off-by: Stefan Lippers-Hollmann <s.l-h@gmx.de>
Diffstat (limited to 'target')
-rw-r--r--target/linux/ipq806x/files-4.14/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts22
-rw-r--r--target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts22
2 files changed, 36 insertions, 8 deletions
diff --git a/target/linux/ipq806x/files-4.14/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts b/target/linux/ipq806x/files-4.14/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts
index 2c8fe922f4..cd8fa633b1 100644
--- a/target/linux/ipq806x/files-4.14/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts
+++ b/target/linux/ipq806x/files-4.14/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts
@@ -39,6 +39,10 @@
soc {
pinmux@800000 {
+
+ pinctrl-0 = <&switch_reset>;
+ pinctrl-names = "default";
+
button_pins: button_pins {
mux {
pins = "gpio65", "gpio67", "gpio68";
@@ -66,6 +70,16 @@
};
};
+ switch_reset: switch_reset_pins {
+ mux {
+ pins = "gpio63";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ output-low;
+ };
+ };
+
mdio0_pins: mdio0_pins {
mux {
pins = "gpio0", "gpio1";
@@ -164,10 +178,6 @@
status = "ok";
};
- pcie2: pci@1b900000 {
- status = "ok";
- };
-
nand@1ac00000 {
status = "ok";
@@ -404,3 +414,7 @@
};
};
};
+
+/delete-node/ &pcie2_pins;
+/delete-node/ &pcie2;
+
diff --git a/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts b/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts
index 7f49db2828..8e1a9c4183 100644
--- a/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts
+++ b/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts
@@ -39,6 +39,10 @@
soc {
pinmux@800000 {
+
+ pinctrl-0 = <&switch_reset>;
+ pinctrl-names = "default";
+
button_pins: button_pins {
mux {
pins = "gpio65", "gpio67", "gpio68";
@@ -66,6 +70,16 @@
};
};
+ switch_reset: switch_reset_pins {
+ mux {
+ pins = "gpio63";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ output-low;
+ };
+ };
+
mdio0_pins: mdio0_pins {
mux {
pins = "gpio0", "gpio1";
@@ -164,10 +178,6 @@
status = "ok";
};
- pcie2: pci@1b900000 {
- status = "ok";
- };
-
nand@1ac00000 {
status = "ok";
@@ -404,3 +414,7 @@
};
};
};
+
+/delete-node/ &pcie2_pins;
+/delete-node/ &pcie2;
+