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| author | Pawel Dembicki <paweldembicki@gmail.com> | 2018-07-18 04:31:36 +0000 |
|---|---|---|
| committer | Mathias Kresin <dev@kresin.me> | 2018-08-15 07:42:36 +0200 |
| commit | 4877ad44c718debfa75533aedaaf3dfd0faeb6f0 (patch) | |
| tree | e7a074b808f5d75b8b855b76c592fb633d90e927 /target | |
| parent | 5762efd8b29d68e219fc9d00b681269727cbf5d5 (diff) | |
| download | upstream-4877ad44c718debfa75533aedaaf3dfd0faeb6f0.tar.gz upstream-4877ad44c718debfa75533aedaaf3dfd0faeb6f0.tar.bz2 upstream-4877ad44c718debfa75533aedaaf3dfd0faeb6f0.zip | |
ramips: mt7620: enable all ports unconditionally
This patch make all mt7620 ephy ports turned on.
It is necessary for some JBOOT devices.
Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
Diffstat (limited to 'target')
| -rw-r--r-- | target/linux/ramips/files-4.14/drivers/net/ethernet/mediatek/gsw_mt7620.c | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/target/linux/ramips/files-4.14/drivers/net/ethernet/mediatek/gsw_mt7620.c b/target/linux/ramips/files-4.14/drivers/net/ethernet/mediatek/gsw_mt7620.c index b1f1794bc9..ecd056e27b 100644 --- a/target/linux/ramips/files-4.14/drivers/net/ethernet/mediatek/gsw_mt7620.c +++ b/target/linux/ramips/files-4.14/drivers/net/ethernet/mediatek/gsw_mt7620.c @@ -83,6 +83,8 @@ static int mt7620_mdio_mode(struct device_node *eth_node) static void mt7620_hw_init(struct mt7620_gsw *gsw, int mdio_mode) { + u32 i; + u32 val; u32 is_BGA = (rt_sysc_r32(0x0c) >> 16) & 1; rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | BIT(8), SYSC_REG_CFG1); @@ -151,6 +153,14 @@ static void mt7620_hw_init(struct mt7620_gsw *gsw, int mdio_mode) /* global page 1 */ _mt7620_mii_write(gsw, 1, 31, 0x1000); _mt7620_mii_write(gsw, 1, 17, 0xe7f8); + + /* turn on all PHYs */ + for (i = 0; i <= 4; i++) { + val = _mt7620_mii_read(gsw, i, 0); + val &= ~BIT(11); + _mt7620_mii_write(gsw, i, 0, val); + } + } /* global page 0 */ @@ -187,7 +197,6 @@ static void mt7620_hw_init(struct mt7620_gsw *gsw, int mdio_mode) _mt7620_mii_write(gsw, 4, 30, 0xa000); _mt7620_mii_write(gsw, 4, 4, 0x05e1); _mt7620_mii_write(gsw, 4, 16, 0x1313); - _mt7620_mii_write(gsw, 4, 0, 0x3100); pr_info("gsw: setting port4 to ephy mode\n"); } else if (!mdio_mode) { u32 val = rt_sysc_r32(SYSC_REG_CFG1); |