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| author | Michael Pratt <mcpratt@pm.me> | 2021-05-01 14:17:11 -0400 |
|---|---|---|
| committer | Chuanhong Guo <gch981213@gmail.com> | 2021-06-23 14:22:19 +0800 |
| commit | 26c84b2e46caba1ae17bc82a533c99eee65e7004 (patch) | |
| tree | bb302592fcd36994182cf10160468efb3ca30d54 /target | |
| parent | cc6fd6fbb505071e08011f7998afaffefcf08fd3 (diff) | |
| download | upstream-26c84b2e46caba1ae17bc82a533c99eee65e7004.tar.gz upstream-26c84b2e46caba1ae17bc82a533c99eee65e7004.tar.bz2 upstream-26c84b2e46caba1ae17bc82a533c99eee65e7004.zip | |
ramips: mt7620: fix RGMII TXID PHY mode
the register bits for TX delay and RX delay are opposites:
when TX delay bit is set, delay is enabled
when RX delay bit is set, delay is disabled
So, when both bits are unset, it is RX delay
and when both bits are set, it is TX delay
Note: TXID is the default RGMII mode of the SOC
Fixes: 5410a8e2959a ("ramips: mt7620: add rgmii delays support")
Signed-off-by: Michael Pratt <mcpratt@pm.me>
Diffstat (limited to 'target')
| -rw-r--r-- | target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c b/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c index 4d012afa14..c9104aa375 100644 --- a/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c +++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c @@ -205,7 +205,7 @@ static void mt7620_port_init(struct fe_priv *priv, struct device_node *np) break; case PHY_INTERFACE_MODE_RGMII_TXID: mask = 0; - val_delay &= ~GSW_REG_GPCx_TXDELAY; + val_delay |= GSW_REG_GPCx_TXDELAY; val_delay |= GSW_REG_GPCx_RXDELAY; break; case PHY_INTERFACE_MODE_MII: |