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authorFelix Fietkau <nbd@openwrt.org>2012-10-10 11:38:58 +0000
committerFelix Fietkau <nbd@openwrt.org>2012-10-10 11:38:58 +0000
commitec94f89147c536af065287cdc7cd34172f9f1461 (patch)
tree4e15dd00380aef9f0a40541e99e0cdc8b04219bd /target/linux
parent53d9b133405fadb8412f9a7e505c7a5070baf7da (diff)
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cns3xxx: Fix laguna arm11mpcore watchdog
The ARM11MPCore Timer/Watchdog registers start at offset 0x600 which is where all mpcore-wdt boards point the driver base too. I believe this is wrong because 0x600 is aliased to the timer/watchdog of the 'current CPU' where 0x700 is CPU0's timer/watchdog, and 0x800 is CPU1's timer/watchdog. Thus if your timer/watchdog application is switching between CPU's it can end up writing to the wrong CPU's registers which results in random board resets from watchdog timeouts etc. This patch forces the timer/watchdog driver to use CPU0's registers always. Its my opinion that other mpcore-wdt boards should be doing the same thing. Signed-off-by: Tim Harvey <tharvey@gateworks.com> git-svn-id: svn://svn.openwrt.org/openwrt/trunk@33683 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux')
-rw-r--r--target/linux/cns3xxx/patches-3.3/300-laguna_support.patch2
1 files changed, 1 insertions, 1 deletions
diff --git a/target/linux/cns3xxx/patches-3.3/300-laguna_support.patch b/target/linux/cns3xxx/patches-3.3/300-laguna_support.patch
index 7fe970a4dd..a4602f9292 100644
--- a/target/linux/cns3xxx/patches-3.3/300-laguna_support.patch
+++ b/target/linux/cns3xxx/patches-3.3/300-laguna_support.patch
@@ -563,7 +563,7 @@
+
+static struct resource laguna_watchdog_resources[] = {
+ [0] = {
-+ .start = CNS3XXX_TC11MP_TWD_BASE,
++ .start = CNS3XXX_TC11MP_TWD_BASE + 0x100, // CPU0 watchdog
+ .end = CNS3XXX_TC11MP_TWD_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },