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authorMartin Blumenstingl <martin.blumenstingl@googlemail.com>2019-06-22 10:37:45 +0200
committerMathias Kresin <dev@kresin.me>2019-07-04 08:29:13 +0200
commiteb72439dbb4acc936cbabf16cb0683a5a230e897 (patch)
tree3d741f55f7e142b2c35e3de35a6c18f0b7cfb954 /target/linux
parentf0c740650b466ffacae64a6f7b67ffacdaf28efd (diff)
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lantiq: 4.19: increase usb reset timeouts
With kernel 4.19 dwc2 would not want to initialize due to reset timeouts, while it worked fine with 4.14. Increase the reset timeouts to 1 second, as it was used by the old lantiq ifxhcd usb driver. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Mathias Kresin <dev@kresin.me>
Diffstat (limited to 'target/linux')
-rw-r--r--target/linux/lantiq/patches-4.19/0002-usb-dwc2-use-a-longer-AHB-idle-timeout-in-dwc2_core_.patch35
-rw-r--r--target/linux/lantiq/patches-4.19/0003-usb-dwc2-use-a-longer-core-rest-timeout-in-dwc2_core.patch29
2 files changed, 64 insertions, 0 deletions
diff --git a/target/linux/lantiq/patches-4.19/0002-usb-dwc2-use-a-longer-AHB-idle-timeout-in-dwc2_core_.patch b/target/linux/lantiq/patches-4.19/0002-usb-dwc2-use-a-longer-AHB-idle-timeout-in-dwc2_core_.patch
new file mode 100644
index 0000000000..c004e44e4a
--- /dev/null
+++ b/target/linux/lantiq/patches-4.19/0002-usb-dwc2-use-a-longer-AHB-idle-timeout-in-dwc2_core_.patch
@@ -0,0 +1,35 @@
+From bfe92b01cafebb10f0d7f38dceb37433687b7887 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Thu, 20 Jun 2019 19:50:22 +0200
+Subject: [PATCH] usb: dwc2: use a longer AHB idle timeout in dwc2_core_reset()
+
+Use a 10000us AHB idle timeout in dwc2_core_reset() and make it
+consistent with the other "wait for AHB master IDLE state" ocurrences.
+
+This fixes a problem for me where dwc2 would not want to initialize when
+updating to 4.19 on a MIPS Lantiq VRX200 SoC. dwc2 worked fine with
+4.14.
+Testing on my board shows that it takes 180us until AHB master IDLE
+state is signalled. The very old vendor driver for this SoC (ifxhcd)
+used a 1 second timeout.
+Use the same timeout that is used everywhere when polling for
+GRSTCTL_AHBIDLE instead of using a timeout that "works for one board"
+(180us in my case) to have consistent behavior across the dwc2 driver.
+
+Cc: linux-stable <stable@vger.kernel.org> # 4.19+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/usb/dwc2/core.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/usb/dwc2/core.c
++++ b/drivers/usb/dwc2/core.c
+@@ -531,7 +531,7 @@ int dwc2_core_reset(struct dwc2_hsotg *h
+ }
+
+ /* Wait for AHB master IDLE state */
+- if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, GRSTCTL_AHBIDLE, 50)) {
++ if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, GRSTCTL_AHBIDLE, 10000)) {
+ dev_warn(hsotg->dev, "%s: HANG! AHB Idle timeout GRSTCTL GRSTCTL_AHBIDLE\n",
+ __func__);
+ return -EBUSY;
diff --git a/target/linux/lantiq/patches-4.19/0003-usb-dwc2-use-a-longer-core-rest-timeout-in-dwc2_core.patch b/target/linux/lantiq/patches-4.19/0003-usb-dwc2-use-a-longer-core-rest-timeout-in-dwc2_core.patch
new file mode 100644
index 0000000000..dde7b3f23b
--- /dev/null
+++ b/target/linux/lantiq/patches-4.19/0003-usb-dwc2-use-a-longer-core-rest-timeout-in-dwc2_core.patch
@@ -0,0 +1,29 @@
+From 09bbf8c732e7a6ce290fc7c2d5a3e79ec6c3e8d2 Mon Sep 17 00:00:00 2001
+From: Mathias Kresin <dev@kresin.me>
+Date: Wed, 3 Jul 2019 17:03:02 +0200
+Subject: [PATCH] usb: dwc2: use a longer core rest timeout in
+ dwc2_core_reset()
+
+Testing on different generations of Lantiq MIPS SoC based boards, showed
+that it takes up to 1500 us until the core reset bit is cleared.
+
+The driver from the vendor SDK (ifxhcd) uses a 1 second timeout. Use the
+same timeout to fix wrong hang detections and make the driver work for
+Lantiq MIPS SoCs.
+
+Signed-off-by: Mathias Kresin <dev@kresin.me>
+---
+ drivers/usb/dwc2/core.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/usb/dwc2/core.c
++++ b/drivers/usb/dwc2/core.c
+@@ -524,7 +524,7 @@ int dwc2_core_reset(struct dwc2_hsotg *h
+ greset |= GRSTCTL_CSFTRST;
+ dwc2_writel(hsotg, greset, GRSTCTL);
+
+- if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_CSFTRST, 50)) {
++ if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_CSFTRST, 10000)) {
+ dev_warn(hsotg->dev, "%s: HANG! Soft Reset timeout GRSTCTL GRSTCTL_CSFTRST\n",
+ __func__);
+ return -EBUSY;