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authorGabor Juhos <juhosg@openwrt.org>2008-11-26 17:17:13 +0000
committerGabor Juhos <juhosg@openwrt.org>2008-11-26 17:17:13 +0000
commit9f93bd51cfb695111000605877602089622e42f0 (patch)
tree3874ea9eaaaa40932203566bd309f24608fd4f9a /target/linux
parent4fc7535fc7a84d75361a028095ebec24fb6535ee (diff)
downloadupstream-9f93bd51cfb695111000605877602089622e42f0.tar.gz
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rename DDR registers
SVN-Revision: 13363
Diffstat (limited to 'target/linux')
-rw-r--r--target/linux/ar71xx/files/arch/mips/ar71xx/platform.c4
-rw-r--r--target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c16
-rw-r--r--target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h24
3 files changed, 22 insertions, 22 deletions
diff --git a/target/linux/ar71xx/files/arch/mips/ar71xx/platform.c b/target/linux/ar71xx/files/arch/mips/ar71xx/platform.c
index 81cd20a4e8..deda410279 100644
--- a/target/linux/ar71xx/files/arch/mips/ar71xx/platform.c
+++ b/target/linux/ar71xx/files/arch/mips/ar71xx/platform.c
@@ -198,7 +198,7 @@ static struct resource ar71xx_eth0_resources[] = {
struct ag71xx_platform_data ar71xx_eth0_data = {
.reset_bit = RESET_MODULE_GE0_MAC,
- .flush_reg = DDR_REG_FLUSH_GE0,
+ .flush_reg = AR71XX_DDR_REG_FLUSH_GE0,
};
static struct platform_device ar71xx_eth0_device = {
@@ -237,7 +237,7 @@ static struct resource ar71xx_eth1_resources[] = {
struct ag71xx_platform_data ar71xx_eth1_data = {
.reset_bit = RESET_MODULE_GE1_MAC,
- .flush_reg = DDR_REG_FLUSH_GE1,
+ .flush_reg = AR71XX_DDR_REG_FLUSH_GE1,
};
static struct platform_device ar71xx_eth1_device = {
diff --git a/target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c b/target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c
index f27c171a63..383a708b8c 100644
--- a/target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c
+++ b/target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c
@@ -316,14 +316,14 @@ static int __init __ar71xx_pci_bios_init(unsigned nr_irqs,
ar71xx_pcicfg_base = ioremap_nocache(AR71XX_PCI_CFG_BASE,
AR71XX_PCI_CFG_SIZE);
- ar71xx_ddr_wr(DDR_REG_PCI_WIN0, PCI_WIN0_OFFS);
- ar71xx_ddr_wr(DDR_REG_PCI_WIN1, PCI_WIN1_OFFS);
- ar71xx_ddr_wr(DDR_REG_PCI_WIN2, PCI_WIN2_OFFS);
- ar71xx_ddr_wr(DDR_REG_PCI_WIN3, PCI_WIN3_OFFS);
- ar71xx_ddr_wr(DDR_REG_PCI_WIN4, PCI_WIN4_OFFS);
- ar71xx_ddr_wr(DDR_REG_PCI_WIN5, PCI_WIN5_OFFS);
- ar71xx_ddr_wr(DDR_REG_PCI_WIN6, PCI_WIN6_OFFS);
- ar71xx_ddr_wr(DDR_REG_PCI_WIN7, PCI_WIN7_OFFS);
+ ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN0, PCI_WIN0_OFFS);
+ ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN1, PCI_WIN1_OFFS);
+ ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN2, PCI_WIN2_OFFS);
+ ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN3, PCI_WIN3_OFFS);
+ ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN4, PCI_WIN4_OFFS);
+ ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN5, PCI_WIN5_OFFS);
+ ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN6, PCI_WIN6_OFFS);
+ ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN7, PCI_WIN7_OFFS);
ar71xx_pci_delay();
diff --git a/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h b/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h
index 8dbe021614..322f3c2ec7 100644
--- a/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h
+++ b/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h
@@ -207,18 +207,18 @@ extern void ar71xx_gpio_function_disable(u32 mask);
/*
* DDR_CTRL block
*/
-#define DDR_REG_PCI_WIN0 0x7c
-#define DDR_REG_PCI_WIN1 0x80
-#define DDR_REG_PCI_WIN2 0x84
-#define DDR_REG_PCI_WIN3 0x88
-#define DDR_REG_PCI_WIN4 0x8c
-#define DDR_REG_PCI_WIN5 0x90
-#define DDR_REG_PCI_WIN6 0x94
-#define DDR_REG_PCI_WIN7 0x98
-#define DDR_REG_FLUSH_GE0 0x9c
-#define DDR_REG_FLUSH_GE1 0xa0
-#define DDR_REG_FLUSH_USB 0xa4
-#define DDR_REG_FLUSH_PCI 0xa8
+#define AR71XX_DDR_REG_PCI_WIN0 0x7c
+#define AR71XX_DDR_REG_PCI_WIN1 0x80
+#define AR71XX_DDR_REG_PCI_WIN2 0x84
+#define AR71XX_DDR_REG_PCI_WIN3 0x88
+#define AR71XX_DDR_REG_PCI_WIN4 0x8c
+#define AR71XX_DDR_REG_PCI_WIN5 0x90
+#define AR71XX_DDR_REG_PCI_WIN6 0x94
+#define AR71XX_DDR_REG_PCI_WIN7 0x98
+#define AR71XX_DDR_REG_FLUSH_GE0 0x9c
+#define AR71XX_DDR_REG_FLUSH_GE1 0xa0
+#define AR71XX_DDR_REG_FLUSH_USB 0xa4
+#define AR71XX_DDR_REG_FLUSH_PCI 0xa8
#define PCI_WIN0_OFFS 0x10000000
#define PCI_WIN1_OFFS 0x11000000