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| author | Jeff Kletsky <git-commits@allycomm.com> | 2019-10-23 09:55:01 -0700 |
|---|---|---|
| committer | John Crispin <john@phrozen.org> | 2019-10-24 23:00:36 +0200 |
| commit | 736d16baad35a1fcbf22edac8d7d9eccae686a33 (patch) | |
| tree | 63733faf0ff4ac8e072bf0927c6b051e06930a45 /target/linux | |
| parent | 7c5f712e4fec39cc70bef9ac0251926dfa32cc68 (diff) | |
| download | upstream-736d16baad35a1fcbf22edac8d7d9eccae686a33.tar.gz upstream-736d16baad35a1fcbf22edac8d7d9eccae686a33.tar.bz2 upstream-736d16baad35a1fcbf22edac8d7d9eccae686a33.zip | |
ath79: GL-AR300M series: Add I2C Support
The GL-AR300M series have an internal header for I2C.
Provide DTS definitions for the i2c-gpio driver.
The I2C drivers; kmod-i2c-core, kmod-i2c-gpio
consume ~20 kB of flash and can be loaded as modules,
Default clock measured ~11.4 ms period, ~88 kHz
The board has two sets of (unpopulated) headers. While facing the
back of the board (looking into the Ethernet jacks), and looking from
the top, the one on the left edge of the baord with four holes is the
I2C header. It appears to be labeled J8 on "GL-AR300M-V1.4.0" boards.
| (Patch antenna)
|
|
| O GND
| O SDA / GPIO 17
| O SCL / GPIO 16
| ⊡ 3V3 (square land)
|
| (Ethernet jacks)
https://docs.gl-inet.com/en/3/hardware/ar300m/#pcb-pinout states
"Note: I2C is not working in some early version of the router."
Signed-off-by: Jeff Kletsky <git-commits@allycomm.com>
Diffstat (limited to 'target/linux')
| -rw-r--r-- | target/linux/ath79/dts/qca9531_glinet_gl-ar300m.dtsi | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/target/linux/ath79/dts/qca9531_glinet_gl-ar300m.dtsi b/target/linux/ath79/dts/qca9531_glinet_gl-ar300m.dtsi index 267f2f478f..b72aa65522 100644 --- a/target/linux/ath79/dts/qca9531_glinet_gl-ar300m.dtsi +++ b/target/linux/ath79/dts/qca9531_glinet_gl-ar300m.dtsi @@ -60,6 +60,13 @@ linux,default-trigger = "phy0tpt"; }; }; + + i2c: i2c { + compatible = "i2c-gpio"; + + sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + }; }; &pcie0 { |