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| author | Felix Fietkau <nbd@openwrt.org> | 2015-04-20 15:00:20 +0000 |
|---|---|---|
| committer | Felix Fietkau <nbd@openwrt.org> | 2015-04-20 15:00:20 +0000 |
| commit | 5c6925a23b84430782ab84eac75ade065c6adbb3 (patch) | |
| tree | 345d0467c4fe510e76e8d902cf77a187e3c7d856 /target/linux | |
| parent | e2e2fb168b33c24e61e01e7a2697c035a94ca7b9 (diff) | |
| download | upstream-5c6925a23b84430782ab84eac75ade065c6adbb3.tar.gz upstream-5c6925a23b84430782ab84eac75ade065c6adbb3.tar.bz2 upstream-5c6925a23b84430782ab84eac75ade065c6adbb3.zip | |
ar71xx: Remove TX/RX delay from pll_1000 for OM5P-AN
The tx/rx delay bits in the ETH_XMII_CONTROL register have to be unset when the
enable_rgmii_rx_delay/enable_rgmii_tx_delay will be set in the AT803x PHY.
Othwise the throughput in gigabit mode is heavily reduced.
Signed-off-by: Sven Eckelmann <sven@open-mesh.org>
SVN-Revision: 45521
Diffstat (limited to 'target/linux')
| -rw-r--r-- | target/linux/ar71xx/files/arch/mips/ath79/mach-om5p.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-om5p.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-om5p.c index 272e410a36..298e80ce6c 100644 --- a/target/linux/ar71xx/files/arch/mips/ath79/mach-om5p.c +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-om5p.c @@ -202,7 +202,7 @@ static void __init om5p_an_setup(void) ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; ath79_eth0_data.phy_mask = BIT(7); - ath79_eth0_pll_data.pll_1000 = 0x1a000000; + ath79_eth0_pll_data.pll_1000 = 0x02000000; ath79_eth0_pll_data.pll_100 = 0x00000101; ath79_eth0_pll_data.pll_10 = 0x00001313; ath79_register_eth(0); |