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authorRafał Miłecki <rafal@milecki.pl>2018-11-09 22:28:31 +0100
committerRafał Miłecki <rafal@milecki.pl>2018-11-09 22:29:16 +0100
commit0cf32de17c47c7625c7ee9cc7d21c3489d86311b (patch)
tree16137975e06fa6dc426d9d8c1e7317aa322e9bee /target/linux
parent7dd42aa592363a441cd24682e7f5b30dca5a493a (diff)
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bcm53xx: add DT patch describing pins mux controller
It's needed to support new devices that use specific pin functions. Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Diffstat (limited to 'target/linux')
-rw-r--r--target/linux/bcm53xx/patches-4.14/131-ARM-dts-BCM5301X-Describe-Northstar-pins-mux-control.patch73
1 files changed, 73 insertions, 0 deletions
diff --git a/target/linux/bcm53xx/patches-4.14/131-ARM-dts-BCM5301X-Describe-Northstar-pins-mux-control.patch b/target/linux/bcm53xx/patches-4.14/131-ARM-dts-BCM5301X-Describe-Northstar-pins-mux-control.patch
new file mode 100644
index 0000000000..7b2904acbc
--- /dev/null
+++ b/target/linux/bcm53xx/patches-4.14/131-ARM-dts-BCM5301X-Describe-Northstar-pins-mux-control.patch
@@ -0,0 +1,73 @@
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Fri, 9 Nov 2018 09:53:56 +0100
+Subject: [PATCH] ARM: dts: BCM5301X: Describe Northstar pins mux controller
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This describes hardware & will allow referencing pin functions. The
+first usage is UART1 which allows supporting devices using it.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+---
+
+--- a/arch/arm/boot/dts/bcm5301x.dtsi
++++ b/arch/arm/boot/dts/bcm5301x.dtsi
+@@ -37,6 +37,8 @@
+ reg = <0x0400 0x100>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&iprocslow>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinmux_uart1>;
+ status = "disabled";
+ };
+ };
+@@ -391,6 +393,48 @@
+ status = "disabled";
+ };
+
++ dmu@1800c000 {
++ compatible = "simple-bus";
++ ranges = <0 0x1800c000 0x1000>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ cru@100 {
++ compatible = "simple-bus";
++ reg = <0x100 0x1a4>;
++ ranges;
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ pin-controller@1c0 {
++ compatible = "brcm,bcm4708-pinmux";
++ reg = <0x1c0 0x24>;
++ reg-names = "cru_gpio_control";
++
++ spi-pins {
++ groups = "spi_grp";
++ function = "spi";
++ };
++
++ i2c {
++ groups = "i2c_grp";
++ function = "i2c";
++ };
++
++ pwm {
++ groups = "pwm0_grp", "pwm1_grp",
++ "pwm2_grp", "pwm3_grp";
++ function = "pwm";
++ };
++
++ pinmux_uart1: uart1 {
++ groups = "uart1_grp";
++ function = "uart1";
++ };
++ };
++ };
++ };
++
+ lcpll0: lcpll0@1800c100 {
+ #clock-cells = <1>;
+ compatible = "brcm,nsp-lcpll0";