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| author | Daniel Golle <daniel@makrotopia.org> | 2023-08-04 14:07:43 +0100 |
|---|---|---|
| committer | Daniel Golle <daniel@makrotopia.org> | 2023-08-13 15:01:36 +0100 |
| commit | 0454691960e16bb93ed01f89352cbb375008aaf5 (patch) | |
| tree | 6e3234aa3de422ca05afa05cb3d10601f4779e6b /target/linux | |
| parent | 64782497dbdf124d9f7979ae1aa48f20c9b9dec8 (diff) | |
| download | upstream-0454691960e16bb93ed01f89352cbb375008aaf5.tar.gz upstream-0454691960e16bb93ed01f89352cbb375008aaf5.tar.bz2 upstream-0454691960e16bb93ed01f89352cbb375008aaf5.zip | |
mediatek: filogic: mt7988: mark RTC clock as critical
A dependency of the MT7988 MMC host controller on the SoC's RTC clock
being running has been discovered. Mark RTC clock as critical to fix
MMC host on MT7988.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Diffstat (limited to 'target/linux')
| -rw-r--r-- | target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7988-infracfg.c | 9 | ||||
| -rw-r--r-- | target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-infracfg.c | 9 |
2 files changed, 16 insertions, 2 deletions
diff --git a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7988-infracfg.c b/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7988-infracfg.c index 77e25383b6e..bce8d563756 100644 --- a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7988-infracfg.c +++ b/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7988-infracfg.c @@ -190,6 +190,13 @@ static const struct mtk_gate_regs infra3_cg_regs = { #define GATE_INFRA3(_id, _name, _parent, _shift) \ GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, 0) +#define GATE_CRITICAL(_id, _name, _parent, _regs, _shift) { \ + .id = _id, .name = _name, .parent_name = _parent, \ + .regs = _regs, .shift = _shift, \ + .flags = CLK_IS_CRITICAL, \ + .ops = &mtk_clk_gate_ops_setclr, \ + } + static const struct mtk_gate infra_clks[] = { /* INFRA0 */ GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P0, @@ -271,7 +278,7 @@ static const struct mtk_gate infra_clks[] = { "sysaxi_sel", 17), GATE_INFRA2(CLK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi", "sysaxi_sel", 18), - GATE_INFRA2(CLK_INFRA_RTC, "infra_f_frtc", "top_rtc_32k", 19), + GATE_CRITICAL(CLK_INFRA_RTC, "infra_f_frtc", "top_rtc_32k", &infra2_cg_regs, 19), GATE_INFRA2(CLK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck", "csw_infra_f26m_sel", 20), GATE_INFRA2(CLK_INFRA_RC_ADC, "infra_f_frc_adc", "infra_f_26m_adc_bck", diff --git a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-infracfg.c b/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-infracfg.c index 111b516ae56..a5d21d756d5 100644 --- a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-infracfg.c +++ b/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-infracfg.c @@ -190,6 +190,13 @@ static const struct mtk_gate_regs infra3_cg_regs = { #define GATE_INFRA3(_id, _name, _parent, _shift) \ GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, 0) +#define GATE_CRITICAL(_id, _name, _parent, _regs, _shift) { \ + .id = _id, .name = _name, .parent_name = _parent, \ + .regs = _regs, .shift = _shift, \ + .flags = CLK_IS_CRITICAL, \ + .ops = &mtk_clk_gate_ops_setclr, \ + } + static const struct mtk_gate infra_clks[] = { /* INFRA0 */ GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P0, @@ -271,7 +278,7 @@ static const struct mtk_gate infra_clks[] = { "sysaxi_sel", 17), GATE_INFRA2(CLK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi", "sysaxi_sel", 18), - GATE_INFRA2(CLK_INFRA_RTC, "infra_f_frtc", "top_rtc_32k", 19), + GATE_CRITICAL(CLK_INFRA_RTC, "infra_f_frtc", "top_rtc_32k", &infra2_cg_regs, 19), GATE_INFRA2(CLK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck", "csw_infra_f26m_sel", 20), GATE_INFRA2(CLK_INFRA_RC_ADC, "infra_f_frc_adc", "infra_f_26m_adc_bck", |