rtl838x: add new architecture

This adds support for the RTL838x Architecture.
SoCs of this type are used in managed and un-managed Switches and Routers
with 8-28 ports. Drivers are provided for SoC initialization, GPIOs, Flash,
Ethernet including a DSA switch driver and internal and external PHYs used
with these switches.

Supported SoCs:

	RTL8380M
	RTL8381M
	RTL8382M

The kernel will also boot on the following RTL839x SoCs, however driver
support apart from spi-nor is missing:

	RTL8390
	RTL8391
	RTL8393

The following PHYs are supported:

	RTL8214FC (Quad QSGMII multiplexing GMAC and SFP port)
	RTL8218B internal: internal PHY of the RTL838x chips
	RTL8318b external (QSGMII 8-port GMAC phy)
	RTL8382M SerDes for 2 SFP ports
	Initialization sequences for the PHYs are provided in the form of
	firmware files.

Flash driver supports 3 / 4 byte access

DSA switch driver supports VLANs, port isolation, STP and port mirroring.

The ALLNET ALL-SG8208M is supported as Proof of Concept:

	RTL8382M SoC
	1 MIPS 4KEc core @ 500MHz
	8 Internal PHYs (RTL8218B)
	128MB DRAM (Nanya NT5TU128MB)
	16MB NOR Flash (MXIC 25L128)
	8 GBEthernet ports with one green status LED each (SoC controlled)
	1 Power LED (not configurable)
	1 SYS LED (configurable)
	1 On-Off switch (not configurable)
	1 Reset button at the right behind right air-vent (not configurable)
	1 Reset button on front panel (configurable)
	12V 1A barrel connector
	1 serial header with populated standard pin connector and with markings
	  GND TX RX Vcc(3.3V), connection properties: 115200 8N1

To install, upload the sysupgrade image to the OEM webpage.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>

1 files changed, 221 insertions, 0 deletions

diff --git a/target/linux/rtl838x/dts/rtl8382_allnet_all-sg8208m.dts b/target/linux/rtl838x/dts/rtl8382_allnet_all-sg8208m.dts
new file mode 100644
index 0000000000..09d5aff0fe
--- /dev/null
+++ b/target/linux/rtl838x/dts/rtl8382_allnet_all-sg8208m.dts
@@ -0,0 +1,221 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/dts-v1/;
+
+#include "rtl838x.dtsi"
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	compatible = "allnet,all-sg8208m", "realtek,rtl838x-soc";
+	model = "ALLNET ALL-SG8208M";
+
+	aliases {
+		led-boot = &led_sys;
+		led-failsafe = &led_sys;
+		led-running = &led_sys;
+		led-upgrade = &led_sys;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200";
+	};
+
+	keys {
+		compatible = "gpio-keys-polled";
+		poll-interval = <20>;
+
+		reset {
+			label = "reset";
+			gpios = <&gpio0 67 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led_sys: sys {
+			label = "all-sg8208m:green:sys";
+			gpios = <&gpio0 47 GPIO_ACTIVE_HIGH>;
+		};
+		// GPIO 25: power on/off all port leds
+	};
+};
+
+&gpio0 {
+	indirect-access-bus-id = <0>;
+};
+
+&spi0 {
+	status = "okay";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <10000000>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "u-boot";
+				reg = <0x0 0x80000>;
+				read-only;
+			};
+
+			partition@80000 {
+				label = "u-boot-env";
+				reg = <0x80000 0x10000>;
+				read-only;
+			};
+
+			partition@90000 {
+				label = "u-boot-env2";
+				reg = <0x90000 0x10000>;
+				read-only;
+			};
+
+			partition@a0000 {
+				label = "jffs";
+				reg = <0xa0000 0x100000>;
+			};
+
+			partition@1a0000 {
+				label = "jffs2";
+				reg = <0x1a0000 0x100000>;
+			};
+
+			partition@2a0000 {
+				label = "firmware";
+				reg = <0x2a0000 0xd60000>;
+				compatible = "allnet,uimage";
+			};
+		};
+	};
+};
+
+&ethernet0 {
+	mdio: mdio-bus {
+		compatible = "realtek,rtl838x-mdio";
+		regmap = <&ethernet0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		/* Internal phy */
+		phy8: ethernet-phy@8 {
+			reg = <8>;
+			compatible = "ethernet-phy-ieee802.3-c22";
+		};
+
+		phy9: ethernet-phy@9 {
+			reg = <9>;
+			compatible = "ethernet-phy-ieee802.3-c22";
+		};
+
+		phy10: ethernet-phy@10 {
+			reg = <10>;
+			compatible = "ethernet-phy-ieee802.3-c22";
+		};
+
+		phy11: ethernet-phy@11 {
+			reg = <11>;
+			compatible = "ethernet-phy-ieee802.3-c22";
+		};
+
+		phy12: ethernet-phy@12 {
+			reg = <12>;
+			compatible = "ethernet-phy-ieee802.3-c22";
+		};
+
+		phy13: ethernet-phy@13 {
+			reg = <13>;
+			compatible = "ethernet-phy-ieee802.3-c22";
+		};
+
+		phy14: ethernet-phy@14 {
+			reg = <14>;
+			compatible = "ethernet-phy-ieee802.3-c22";
+		};
+
+		phy15: ethernet-phy@15 {
+			reg = <15>;
+			compatible = "ethernet-phy-ieee802.3-c22";
+		};
+	};
+};
+
+&switch0 {
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <8>;
+			label = "lan1";
+			phy-handle = <&phy8>;
+			phy-mode = "internal";
+		};
+
+		port@1 {
+			reg = <9>;
+			label = "lan2";
+			phy-handle = <&phy9>;
+			phy-mode = "internal";
+		};
+
+		port@2 {
+			reg = <10>;
+			label = "lan3";
+			phy-handle = <&phy10>;
+			phy-mode = "internal";
+		};
+
+		port@3 {
+			reg = <11>;
+			label = "lan4";
+			phy-handle = <&phy11>;
+			phy-mode = "internal";
+		};
+
+		port@4 {
+			reg = <12>;
+			label = "lan5";
+			phy-handle = <&phy12>;
+			phy-mode = "internal";
+		};
+
+		port@5 {
+			reg = <13>;
+			label = "lan6";
+			phy-handle = <&phy13>;
+			phy-mode = "internal";
+		};
+
+		port@6 {
+			reg = <14>;
+			label = "lan7";
+			phy-handle = <&phy14>;
+			phy-mode = "internal";
+		};
+
+		port@7 {
+			reg = <15>;
+			label = "lan8";
+			phy-handle = <&phy15>;
+			phy-mode = "internal";
+		};
+
+		port@28 {
+			ethernet = <&ethernet0>;
+			reg = <28>;
+			phy-mode = "internal";
+			fixed-link {
+				speed = <1000>;
+				full-duplex;
+			};
+		};
+	};
+};