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| author | Birger Koblitz <git@birger-koblitz.de> | 2022-01-06 20:27:01 +0100 |
|---|---|---|
| committer | Daniel Golle <daniel@makrotopia.org> | 2022-02-17 15:21:47 +0000 |
| commit | 775d903216a08c2a8009863d2f9c33f62657ba94 (patch) | |
| tree | b16ff251bb9024bbdfa098d77277556c48952546 /target/linux/realtek/patches-5.10/309-cevt-rtl9300-support.patch | |
| parent | 0536c582e673aa292377f4b8cb11002238a39d32 (diff) | |
| download | upstream-775d903216a08c2a8009863d2f9c33f62657ba94.tar.gz upstream-775d903216a08c2a8009863d2f9c33f62657ba94.tar.bz2 upstream-775d903216a08c2a8009863d2f9c33f62657ba94.zip | |
realtek: Replace the RTL9300 generic timer with a CEVT timer
The RTL9300 has a broken R4K MIPS timer interrupt, however, the
R4K clocksource works. We replace the RTL9300 timer with a
Clock Event Timer (CEVT), which is VSMP aware and can be instantiated
as part of brining a VSMTP cpu up instead of the R4K CEVT source.
For this we place the RTL9300 CEVT timer in arch/mips/kernel
together with other MIPS CEVT timers, initialize the SoC IRQs
from a modified smp-mt.c and instantiate each timer as part
of the MIPS time setup in arch/mips/include/asm/time.h instead
of the R4K CEVT, similarly as is done by other MIPS CEVT timers.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Diffstat (limited to 'target/linux/realtek/patches-5.10/309-cevt-rtl9300-support.patch')
| -rw-r--r-- | target/linux/realtek/patches-5.10/309-cevt-rtl9300-support.patch | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/target/linux/realtek/patches-5.10/309-cevt-rtl9300-support.patch b/target/linux/realtek/patches-5.10/309-cevt-rtl9300-support.patch new file mode 100644 index 0000000000..6a0038d86b --- /dev/null +++ b/target/linux/realtek/patches-5.10/309-cevt-rtl9300-support.patch @@ -0,0 +1,54 @@ +--- a/arch/mips/kernel/Makefile ++++ b/arch/mips/kernel/Makefile +@@ -27,6 +27,7 @@ obj-$(CONFIG_CEVT_BCM1480) += cevt-bcm14 + obj-$(CONFIG_CEVT_R4K) += cevt-r4k.o + obj-$(CONFIG_CEVT_DS1287) += cevt-ds1287.o + obj-$(CONFIG_CEVT_GT641XX) += cevt-gt641xx.o ++obj-$(CONFIG_CEVT_RTL9300) += cevt-rtl9300.o + obj-$(CONFIG_CEVT_SB1250) += cevt-sb1250.o + obj-$(CONFIG_CEVT_TXX9) += cevt-txx9.o + obj-$(CONFIG_CSRC_BCM1480) += csrc-bcm1480.o +--- a/arch/mips/include/asm/time.h ++++ b/arch/mips/include/asm/time.h +@@ -15,6 +15,8 @@ + #include <linux/clockchips.h> + #include <linux/clocksource.h> + ++extern void rtl9300_clockevent_init(void); ++ + extern spinlock_t rtc_lock; + + /* +@@ -43,6 +45,11 @@ extern int r4k_clockevent_init(void); + + static inline int mips_clockevent_init(void) + { ++#ifdef CONFIG_CEVT_RTL9300 ++ rtl9300_clockevent_init(); ++ return 0; ++#endif ++ + #ifdef CONFIG_CEVT_R4K + return r4k_clockevent_init(); + #else +--- a/arch/mips/kernel/smp-mt.c ++++ b/arch/mips/kernel/smp-mt.c +@@ -108,12 +108,18 @@ static void __init smvp_tc_init(unsigned + static void vsmp_init_secondary(void) + { + /* This is Malta specific: IPI,performance and timer interrupts */ ++ ++ /* RTL9300 Clear internal timer interrupt */ ++ write_c0_compare(0); ++ + if (mips_gic_present()) + change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 | + STATUSF_IP4 | STATUSF_IP5 | + STATUSF_IP6 | STATUSF_IP7); + else + change_c0_status(ST0_IM, STATUSF_IP0 | STATUSF_IP1 | ++ STATUSF_IP2 | STATUSF_IP3 | ++ STATUSF_IP4 | STATUSF_IP5 | + STATUSF_IP6 | STATUSF_IP7); + } + |