realtek: update the tree to the latest refactored version

* rename the target to realtek
* add refactored DSA driver
* add latest gpio driver
* lots of arch cleanups
* new irq driver
* additional boards

Signed-off-by: Bert Vermeulen <bert@biot.com>
Signed-off-by: Birger Koblitz <mail@birger-koblitz.de>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Signed-off-by: Bjørn Mork <bjorn@mork.no>
Signed-off-by: John Crispin <john@phrozen.org>

26 files changed, 8769 insertions, 0 deletions

diff --git a/target/linux/realtek/files-5.4/arch/mips/include/asm/mach-rtl838x/ioremap.h b/target/linux/realtek/files-5.4/arch/mips/include/asm/mach-rtl838x/ioremap.h
new file mode 100644
index 0000000000..e7a5bfaffc
--- /dev/null
+++ b/target/linux/realtek/files-5.4/arch/mips/include/asm/mach-rtl838x/ioremap.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef RTL838X_IOREMAP_H_
+#define RTL838X_IOREMAP_H_
+
+static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
+{
+	return phys_addr;
+}
+
+static inline int is_rtl838x_internal_registers(phys_addr_t offset)
+{
+	/* IO-Block */
+	if (offset >= 0xb8000000 && offset < 0xb9000000)
+		return 1;
+	/* Switch block */
+	if (offset >= 0xbb000000 && offset < 0xbc000000)
+		return 1;
+	return 0;
+}
+
+static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
+					 unsigned long flags)
+{
+	if (is_rtl838x_internal_registers(offset))
+		return (void __iomem *)offset;
+	return NULL;
+}
+
+static inline int plat_iounmap(const volatile void __iomem *addr)
+{
+	return is_rtl838x_internal_registers((unsigned long)addr);
+}
+
+#endif
diff --git a/target/linux/realtek/files-5.4/arch/mips/include/asm/mach-rtl838x/irq.h b/target/linux/realtek/files-5.4/arch/mips/include/asm/mach-rtl838x/irq.h
new file mode 100644
index 0000000000..580c3d8d61
--- /dev/null
+++ b/target/linux/realtek/files-5.4/arch/mips/include/asm/mach-rtl838x/irq.h
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#ifndef _RTL83XX_IRQ_H_
+#define _RTL83XX_IRQ_H_
+
+#define NR_IRQS 32
+#include_next <irq.h>
+
+/* Global Interrupt Mask Register */
+#define RTL83XX_ICTL_GIMR	0x00
+/* Global Interrupt Status Register */
+#define RTL83XX_ICTL_GISR	0x04
+
+#define RTL83XX_IRQ_CPU_BASE	0
+#define RTL83XX_IRQ_CPU_NUM	8
+#define RTL83XX_IRQ_ICTL_BASE	(RTL83XX_IRQ_CPU_BASE + RTL83XX_IRQ_CPU_NUM)
+#define RTL83XX_IRQ_ICTL_NUM	32
+
+/* Cascaded interrupts */
+#define RTL83XX_ICTL1_IRQ	(RTL83XX_IRQ_CPU_BASE + 2)
+#define RTL83XX_ICTL2_IRQ	(RTL83XX_IRQ_CPU_BASE + 3)
+#define RTL83XX_ICTL3_IRQ	(RTL83XX_IRQ_CPU_BASE + 4)
+#define RTL83XX_ICTL4_IRQ	(RTL83XX_IRQ_CPU_BASE + 5)
+#define RTL83XX_ICTL5_IRQ	(RTL83XX_IRQ_CPU_BASE + 6)
+
+/* Interrupt routing register */
+#define RTL83XX_IRR0		0x08
+#define RTL83XX_IRR1		0x0c
+#define RTL83XX_IRR2		0x10
+#define RTL83XX_IRR3		0x14
+
+/* Cascade map */
+#define UART0_CASCADE		2
+#define UART1_CASCADE		1
+#define TC0_CASCADE		5
+#define TC1_CASCADE		1
+#define OCPTO_CASCADE		1
+#define HLXTO_CASCADE		1
+#define SLXTO_CASCADE		1
+#define NIC_CASCADE		4
+#define GPIO_ABCD_CASCADE	4
+#define GPIO_EFGH_CASCADE	4
+#define RTC_CASCADE		4
+#define	SWCORE_CASCADE		3
+#define WDT_IP1_CASCADE		4
+#define WDT_IP2_CASCADE		5
+
+/* Pack cascade map into interrupt routing registers */
+#define RTL83XX_IRR0_SETTING (\
+	(UART0_CASCADE		<< 28) | \
+	(UART1_CASCADE		<< 24) | \
+	(TC0_CASCADE		<< 20) | \
+	(TC1_CASCADE		<< 16) | \
+	(OCPTO_CASCADE		<< 12) | \
+	(HLXTO_CASCADE		<< 8)  | \
+	(SLXTO_CASCADE		<< 4)  | \
+	(NIC_CASCADE		<< 0))
+#define RTL83XX_IRR1_SETTING (\
+	(GPIO_ABCD_CASCADE	<< 28) | \
+	(GPIO_EFGH_CASCADE	<< 24) | \
+	(RTC_CASCADE		<< 20) | \
+	(SWCORE_CASCADE		<< 16))
+#define RTL83XX_IRR2_SETTING	0
+#define RTL83XX_IRR3_SETTING	0
+
+#endif /* _RTL83XX_IRQ_H_ */
diff --git a/target/linux/realtek/files-5.4/arch/mips/include/asm/mach-rtl838x/mach-rtl83xx.h b/target/linux/realtek/files-5.4/arch/mips/include/asm/mach-rtl838x/mach-rtl83xx.h
new file mode 100644
index 0000000000..b7d2a6f037
--- /dev/null
+++ b/target/linux/realtek/files-5.4/arch/mips/include/asm/mach-rtl838x/mach-rtl83xx.h
@@ -0,0 +1,458 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com)
+ * Copyright (C) 2020 B. Koblitz
+ */
+#ifndef _MACH_RTL838X_H_
+#define _MACH_RTL838X_H_
+
+#include <asm/types.h>
+/*
+ * Register access macros
+ */
+
+#define RTL838X_SW_BASE		((volatile void *) 0xBB000000)
+
+#define rtl83xx_r32(reg)	readl(reg)
+#define rtl83xx_w32(val, reg)	writel(val, reg)
+#define rtl83xx_w32_mask(clear, set, reg) rtl83xx_w32((rtl83xx_r32(reg) & ~(clear)) | (set), reg)
+
+#define rtl83xx_r8(reg)		readb(reg)
+#define rtl83xx_w8(val, reg)	writeb(val, reg)
+
+#define sw_r32(reg)		readl(RTL838X_SW_BASE + reg)
+#define sw_w32(val, reg)	writel(val, RTL838X_SW_BASE + reg)
+#define sw_w32_mask(clear, set, reg)	\
+				sw_w32((sw_r32(reg) & ~(clear)) | (set), reg)
+#define sw_r64(reg)		((((u64)readl(RTL838X_SW_BASE + reg)) << 32) | \
+				readl(RTL838X_SW_BASE + reg + 4))
+
+#define sw_w64(val, reg)	do { \
+					writel((u32)((val) >> 32), RTL838X_SW_BASE + reg); \
+					writel((u32)((val) & 0xffffffff), \
+							RTL838X_SW_BASE + reg + 4); \
+				} while (0)
+
+/*
+ * SPRAM
+ */
+#define RTL838X_ISPRAM_BASE	0x0
+#define RTL838X_DSPRAM_BASE	0x0
+
+/*
+ * IRQ Controller
+ */
+#define RTL838X_IRQ_CPU_BASE	0
+#define RTL838X_IRQ_CPU_NUM	8
+#define RTL838X_IRQ_ICTL_BASE	(RTL838X_IRQ_CPU_BASE + RTL838X_IRQ_CPU_NUM)
+#define RTL838X_IRQ_ICTL_NUM	32
+
+#define RTL83XX_IRQ_UART0               31
+#define RTL83XX_IRQ_UART1               30
+#define RTL83XX_IRQ_TC0                 29
+#define RTL83XX_IRQ_TC1                 28
+#define RTL83XX_IRQ_OCPTO               27
+#define RTL83XX_IRQ_HLXTO               26
+#define RTL83XX_IRQ_SLXTO               25
+#define RTL83XX_IRQ_NIC                 24
+#define RTL83XX_IRQ_GPIO_ABCD           23
+#define RTL83XX_IRQ_GPIO_EFGH           22
+#define RTL83XX_IRQ_RTC                 21
+#define RTL83XX_IRQ_SWCORE              20
+#define RTL83XX_IRQ_WDT_IP1             19
+#define RTL83XX_IRQ_WDT_IP2             18
+
+
+/*
+ * MIPS32R2 counter
+ */
+#define RTL838X_COMPARE_IRQ	(RTL838X_IRQ_CPU_BASE + 7)
+
+/*
+ *  ICTL
+ *  Base address 0xb8003000UL
+ */
+#define RTL838X_ICTL1_IRQ	(RTL838X_IRQ_CPU_BASE + 2)
+#define RTL838X_ICTL2_IRQ	(RTL838X_IRQ_CPU_BASE + 3)
+#define RTL838X_ICTL3_IRQ	(RTL838X_IRQ_CPU_BASE + 4)
+#define RTL838X_ICTL4_IRQ	(RTL838X_IRQ_CPU_BASE + 5)
+#define RTL838X_ICTL5_IRQ	(RTL838X_IRQ_CPU_BASE + 6)
+
+#define GIMR			(0x00)
+#define UART0_IE		(1 << 31)
+#define UART1_IE		(1 << 30)
+#define TC0_IE			(1 << 29)
+#define TC1_IE			(1 << 28)
+#define OCPTO_IE		(1 << 27)
+#define HLXTO_IE		(1 << 26)
+#define SLXTO_IE		(1 << 25)
+#define NIC_IE			(1 << 24)
+#define GPIO_ABCD_IE		(1 << 23)
+#define GPIO_EFGH_IE		(1 << 22)
+#define RTC_IE			(1 << 21)
+#define WDT_IP1_IE		(1 << 19)
+#define WDT_IP2_IE		(1 << 18)
+
+#define GISR			(0x04)
+#define UART0_IP		(1 << 31)
+#define UART1_IP		(1 << 30)
+#define TC0_IP			(1 << 29)
+#define TC1_IP			(1 << 28)
+#define OCPTO_IP		(1 << 27)
+#define HLXTO_IP		(1 << 26)
+#define SLXTO_IP		(1 << 25)
+#define NIC_IP			(1 << 24)
+#define GPIO_ABCD_IP		(1 << 23)
+#define GPIO_EFGH_IP		(1 << 22)
+#define RTC_IP			(1 << 21)
+#define WDT_IP1_IP		(1 << 19)
+#define WDT_IP2_IP		(1 << 18)
+
+#define IRR0			(0x08)
+#define IRR0_SETTING		((UART0_RS  << 28) | \
+				 (UART1_RS  << 24) | \
+				 (TC0_RS    << 20) | \
+				 (TC1_RS    << 16) | \
+				 (OCPTO_RS  << 12) | \
+				 (HLXTO_RS  << 8)  | \
+				 (SLXTO_RS  << 4)  | \
+				 (NIC_RS    << 0)    \
+				)
+
+#define IRR1			(0x0c)
+#define IRR1_SETTING_RTL838X	((GPIO_ABCD_RS << 28) | \
+				 (GPIO_EFGH_RS << 24) | \
+				 (RTC_RS       << 20) | \
+				 (SWCORE_RS    << 16)   \
+				)
+#define IRR1_SETTING_RTL839X	((GPIO_ABCD_RS << 28) | \
+				 (SWCORE_RS    << 16)   \
+				)
+
+#define IRR2			(0x10)
+#define IRR2_SETTING		0
+
+#define IRR3			(0x14)
+#define IRR3_SETTING		0
+
+/* Interrupt Routing Selection */
+#define UART0_RS		2
+#define UART1_RS		1
+#define TC0_RS			5
+#define TC1_RS			1
+#define OCPTO_RS		1
+#define HLXTO_RS		1
+#define SLXTO_RS		1
+#define NIC_RS			4
+#define GPIO_ABCD_RS		4
+#define GPIO_EFGH_RS		4
+#define RTC_RS			4
+#define	SWCORE_RS		3
+#define WDT_IP1_RS		4
+#define WDT_IP2_RS		5
+
+/* Interrupt IRQ Assignments */
+#define UART0_IRQ		31
+#define UART1_IRQ		30
+#define TC0_IRQ			29
+#define TC1_IRQ			28
+#define OCPTO_IRQ		27
+#define HLXTO_IRQ		26
+#define SLXTO_IRQ		25
+#define NIC_IRQ			24
+#define GPIO_ABCD_IRQ		23
+#define GPIO_EFGH_IRQ		22
+#define RTC_IRQ			21
+#define	SWCORE_IRQ		20
+#define WDT_IP1_IRQ		19
+#define WDT_IP2_IRQ		18
+
+#define SYSTEM_FREQ		200000000
+#define RTL838X_UART0_BASE	((volatile void *)(0xb8002000UL))
+#define RTL838X_UART0_BAUD	38400  /* ex. 19200 or 38400 or 57600 or 115200 */
+#define RTL838X_UART0_FREQ	(SYSTEM_FREQ - RTL838X_UART0_BAUD * 24)
+#define RTL838X_UART0_MAPBASE	0x18002000UL
+#define RTL838X_UART0_MAPSIZE	0x100
+#define RTL838X_UART0_IRQ	UART0_IRQ
+
+#define RTL838X_UART1_BASE	((volatile void *)(0xb8002100UL))
+#define RTL838X_UART1_BAUD	38400  /* ex. 19200 or 38400 or 57600 or 115200 */
+#define RTL838X_UART1_FREQ	(SYSTEM_FREQ - RTL838X_UART1_BAUD * 24)
+#define RTL838X_UART1_MAPBASE	0x18002100UL
+#define RTL838X_UART1_MAPSIZE	0x100
+#define RTL838X_UART1_IRQ	UART1_IRQ
+
+#define UART0_RBR		(RTL838X_UART0_BASE + 0x000)
+#define UART0_THR		(RTL838X_UART0_BASE + 0x000)
+#define UART0_DLL		(RTL838X_UART0_BASE + 0x000)
+#define UART0_IER		(RTL838X_UART0_BASE + 0x004)
+#define UART0_DLM		(RTL838X_UART0_BASE + 0x004)
+#define UART0_IIR		(RTL838X_UART0_BASE + 0x008)
+#define UART0_FCR		(RTL838X_UART0_BASE + 0x008)
+#define UART0_LCR		(RTL838X_UART0_BASE + 0x00C)
+#define UART0_MCR		(RTL838X_UART0_BASE + 0x010)
+#define UART0_LSR		(RTL838X_UART0_BASE + 0x014)
+
+#define UART1_RBR		(RTL838X_UART1_BASE + 0x000)
+#define UART1_THR		(RTL838X_UART1_BASE + 0x000)
+#define UART1_DLL		(RTL838X_UART1_BASE + 0x000)
+#define UART1_IER		(RTL838X_UART1_BASE + 0x004)
+#define UART1_DLM		(RTL838X_UART1_BASE + 0x004)
+#define UART1_IIR		(RTL838X_UART1_BASE + 0x008)
+#define UART1_FCR		(RTL838X_UART1_BASE + 0x008)
+   #define FCR_EN		0x01
+   #define FCR_RXRST		0x02
+   #define XRST			0x02
+   #define FCR_TXRST		0x04
+   #define TXRST		0x04
+   #define FCR_DMA		0x08
+   #define FCR_RTRG		0xC0
+   #define CHAR_TRIGGER_01	0x00
+   #define CHAR_TRIGGER_04	0x40
+   #define CHAR_TRIGGER_08	0x80
+   #define CHAR_TRIGGER_14	0xC0
+#define UART1_LCR		(RTL838X_UART1_BASE + 0x00C)
+   #define LCR_WLN		0x03
+   #define CHAR_LEN_5		0x00
+   #define CHAR_LEN_6		0x01
+   #define CHAR_LEN_7		0x02
+   #define CHAR_LEN_8		0x03
+   #define LCR_STB		0x04
+   #define ONE_STOP		0x00
+   #define TWO_STOP		0x04
+   #define LCR_PEN		0x08
+   #define PARITY_ENABLE	0x01
+   #define PARITY_DISABLE	0x00
+   #define LCR_EPS		0x30
+   #define PARITY_ODD		0x00
+   #define PARITY_EVEN		0x10
+   #define PARITY_MARK		0x20
+   #define PARITY_SPACE		0x30
+   #define LCR_BRK		0x40
+   #define LCR_DLAB		0x80
+   #define DLAB			0x80
+#define UART1_MCR		(RTL838X_UART1_BASE + 0x010)
+#define UART1_LSR		(RTL838X_UART1_BASE + 0x014)
+   #define LSR_DR		0x01
+   #define RxCHAR_AVAIL		0x01
+   #define LSR_OE		0x02
+   #define LSR_PE		0x04
+   #define LSR_FE		0x08
+   #define LSR_BI		0x10
+   #define LSR_THRE		0x20
+   #define TxCHAR_AVAIL		0x00
+   #define TxCHAR_EMPTY		0x20
+   #define LSR_TEMT		0x40
+   #define LSR_RFE		0x80
+
+/*
+ *  Timer/counter for 8390/80/28 TC & MP chip
+ */
+#define RTL838X_TIMER0_BASE	((volatile void *)(0xb8003100UL))
+#define RTL838X_TIMER0_IRQ	RTL838X_TC0_EXT_IRQ
+
+#define RTL8390TC_TC1DATA	(RTL838X_TIMER0_BASE + 0x04)
+#define RTL8390TC_TCD_OFFSET	8
+#define RTL8390TC_TC0CNT	(RTL838X_TIMER0_BASE + 0x08)
+#define RTL8390TC_TC1CNT	(RTL838X_TIMER0_BASE + 0x0C)
+#define RTL8390TC_TCCNR		(RTL838X_TIMER0_BASE + 0x10)
+#define RTL8390TC_TC0EN		(1 << 31)
+#define RTL8390TC_TC0MODE_TIMER	(1 << 30)
+#define RTL8390TC_TC1EN		(1 << 29)
+#define RTL8390TC_TC1MODE_TIMER	(1 << 28)
+#define RTL8390TC_TCIR		(RTL838X_TIMER0_BASE + 0x14)
+#define RTL8390TC_TC0IE		(1 << 31)
+#define RTL8390TC_TC1IE		(1 << 30)
+#define RTL8390TC_TC0IP		(1 << 29)
+#define RTL8390TC_TC1IP		(1 << 28)
+#define RTL8390TC_CDBR		(RTL838X_TIMER0_BASE + 0x18)
+#define RTL8390TC_DIVF_OFFSET	16
+#define RTL8390TC_WDTCNR	(RTL838X_TIMER0_BASE + 0x1C)
+
+#define RTL8390MP_TC1DATA	(RTL838X_TIMER0_BASE + 0x10)
+#define RTL8390MP_TC0CNT	(RTL838X_TIMER0_BASE + 0x04)
+#define RTL8390MP_TC1CNT	(RTL838X_TIMER0_BASE + 0x14)
+#define RTL8390MP_TC0CTL	(RTL838X_TIMER0_BASE + 0x08)
+#define RTL8390MP_TC1CTL	(RTL838X_TIMER0_BASE + 0x18)
+#define RTL8390MP_TCEN		(1 << 28)
+#define RTL8390MP_TCMODE_TIMER	(1 << 24)
+#define RTL8390MP_TCDIV_FACTOR	(0xFFFF << 0)
+#define RTL8390MP_TC0INT	(RTL838X_TIMER0_BASE + 0xC)
+#define RTL8390MP_TC1INT	(RTL838X_TIMER0_BASE + 0x1C)
+#define RTL8390MP_TCIE		(1 << 20)
+#define RTL8390MP_TCIP		(1 << 16)
+#define RTL8390MP_WDTCNR	(RTL838X_TIMER0_BASE + 0x50)
+
+#define RTL8380MP_TC0DATA	(RTL838X_TIMER0_BASE + 0x00)
+#define RTL8380MP_TC1DATA	(RTL838X_TIMER0_BASE + 0x10)
+#define RTL8380MP_TC0CNT	(RTL838X_TIMER0_BASE + 0x04)
+#define RTL8380MP_TC1CNT	(RTL838X_TIMER0_BASE + 0x14)
+#define RTL8380MP_TC0CTL	(RTL838X_TIMER0_BASE + 0x08)
+#define RTL8380MP_TC1CTL	(RTL838X_TIMER0_BASE + 0x18)
+#define RTL8380MP_TCEN		(1 << 28)
+#define RTL8380MP_TCMODE_TIMER	(1 << 24)
+#define RTL8380MP_TCDIV_FACTOR	(0xFFFF << 0)
+#define RTL8380MP_TC0INT	(RTL838X_TIMER0_BASE + 0xC)
+#define RTL8380MP_TC1INT	(RTL838X_TIMER0_BASE + 0x1C)
+#define RTL8380MP_TCIE		(1 << 20)
+#define RTL8380MP_TCIP		(1 << 16)
+#define RTL8380MP_WDTCNR	(RTL838X_TIMER0_BASE + 0x50)
+
+#define DIVISOR_RTL8390		55
+#define DIVISOR_RTL8380		2500
+#define DIVISOR_MAX		16834
+
+/*
+ * Memory Controller
+ */
+#define MC_MCR			0xB8001000
+#define MC_MCR_VAL		0x00000000
+
+#define MC_DCR			0xB8001004
+#define MC_DCR0_VAL		0x54480000
+
+#define MC_DTCR			0xB8001008
+#define MC_DTCR_VAL		0xFFFF05C0
+
+/*
+ * GPIO
+ */
+#define GPIO_CTRL_REG_BASE		((volatile void *) 0xb8003500)
+#define RTL838X_GPIO_PABC_CNR		(GPIO_CTRL_REG_BASE + 0x0)
+#define RTL838X_GPIO_PABC_TYPE		(GPIO_CTRL_REG_BASE + 0x04)
+#define RTL838X_GPIO_PABC_DIR		(GPIO_CTRL_REG_BASE + 0x8)
+#define RTL838X_GPIO_PABC_DATA		(GPIO_CTRL_REG_BASE + 0xc)
+#define RTL838X_GPIO_PABC_ISR		(GPIO_CTRL_REG_BASE + 0x10)
+#define RTL838X_GPIO_PAB_IMR		(GPIO_CTRL_REG_BASE + 0x14)
+#define RTL838X_GPIO_PC_IMR		(GPIO_CTRL_REG_BASE + 0x18)
+
+#define RTL838X_MODEL_NAME_INFO		(0x00D4)
+#define RTL839X_MODEL_NAME_INFO		(0x0FF0)
+#define RTL838X_LED_GLB_CTRL		(0xA000)
+#define RTL839X_LED_GLB_CTRL		(0x00E4)
+#define RTL838X_EXT_GPIO_DIR		(0xA08C)
+#define RTL839X_EXT_GPIO_DIR		(0x0214)
+#define RTL838X_EXT_GPIO_DATA		(0xA094)
+#define RTL839X_EXT_GPIO_DATA		(0x021c)
+#define RTL838X_EXT_GPIO_INDRT_ACCESS	(0xA09C)
+#define RTL839X_EXT_GPIO_INDRT_ACCESS	(0x0224)
+#define RTL838X_EXTRA_GPIO_CTRL		(0xA0E0)
+#define RTL838X_DMY_REG5		(0x0144)
+#define RTL838X_EXTRA_GPIO_CTRL		(0xA0E0)
+
+#define RTL838X_GMII_INTF_SEL		(0x1000)
+#define RTL838X_IO_DRIVING_ABILITY_CTRL	(0x1010)
+
+#define RTL838X_GPIO_A7		31
+#define RTL838X_GPIO_A6		30
+#define RTL838X_GPIO_A5		29
+#define RTL838X_GPIO_A4		28
+#define RTL838X_GPIO_A3		27
+#define RTL838X_GPIO_A2		26
+#define RTL838X_GPIO_A1		25
+#define RTL838X_GPIO_A0		24
+#define RTL838X_GPIO_B7		23
+#define RTL838X_GPIO_B6		22
+#define RTL838X_GPIO_B5		21
+#define RTL838X_GPIO_B4		20
+#define RTL838X_GPIO_B3		19
+#define RTL838X_GPIO_B2		18
+#define RTL838X_GPIO_B1		17
+#define RTL838X_GPIO_B0		16
+#define RTL838X_GPIO_C7		15
+#define RTL838X_GPIO_C6		14
+#define RTL838X_GPIO_C5		13
+#define RTL838X_GPIO_C4		12
+#define RTL838X_GPIO_C3		11
+#define RTL838X_GPIO_C2		10
+#define RTL838X_GPIO_C1		9
+#define RTL838X_GPIO_C0		8
+
+#define RTL838X_INT_RW_CTRL		(0x0058)
+#define RTL838X_EXT_VERSION		(0x00D0)
+#define RTL838X_PLL_CML_CTRL		(0x0FF8)
+#define RTL838X_STRAP_DBG		(0x100C)
+
+/*
+ * Reset
+ */
+#define	RGCR				(0x1E70)
+#define RTL839X_RST_GLB_CTRL		(0x0014)
+#define RTL838X_RST_GLB_CTRL_1		(0x0040)
+
+/* LED control by switch */
+#define RTL838X_LED_MODE_SEL		(0x1004)
+#define RTL838X_LED_MODE_CTRL		(0xA004)
+#define RTL838X_LED_P_EN_CTRL		(0xA008)
+
+/* LED control by software */
+#define RTL838X_LED_SW_CTRL		(0x0128)
+#define RTL839X_LED_SW_CTRL		(0xA00C)
+#define RTL838X_LED_SW_P_EN_CTRL	(0xA010)
+#define RTL839X_LED_SW_P_EN_CTRL	(0x012C)
+#define RTL838X_LED0_SW_P_EN_CTRL	(0xA010)
+#define RTL839X_LED0_SW_P_EN_CTRL	(0x012C)
+#define RTL838X_LED1_SW_P_EN_CTRL	(0xA014)
+#define RTL839X_LED1_SW_P_EN_CTRL	(0x0130)
+#define RTL838X_LED2_SW_P_EN_CTRL	(0xA018)
+#define RTL839X_LED2_SW_P_EN_CTRL	(0x0134)
+#define RTL838X_LED_SW_P_CTRL		(0xA01C)
+#define RTL839X_LED_SW_P_CTRL		(0x0144)
+
+#define RTL839X_MAC_EFUSE_CTRL		(0x02ac)
+
+/*
+ * MDIO via Realtek's SMI interface
+ */
+#define RTL838X_SMI_GLB_CTRL		(0xa100)
+#define RTL838X_SMI_ACCESS_PHY_CTRL_0	(0xa1b8)
+#define RTL838X_SMI_ACCESS_PHY_CTRL_1	(0xa1bc)
+#define RTL838X_SMI_ACCESS_PHY_CTRL_2	(0xa1c0)
+#define RTL838X_SMI_ACCESS_PHY_CTRL_3	(0xa1c4)
+#define RTL838X_SMI_PORT0_5_ADDR_CTRL	(0xa1c8)
+#define RTL838X_SMI_POLL_CTRL		(0xa17c)
+
+#define RTL839X_SMI_GLB_CTRL		(0x03f8)
+#define RTL839X_SMI_PORT_POLLING_CTRL	(0x03fc)
+#define RTL839X_PHYREG_ACCESS_CTRL	(0x03DC)
+#define RTL839X_PHYREG_CTRL		(0x03E0)
+#define RTL839X_PHYREG_PORT_CTRL(p)	(0x03E4 + ((p >> 5) << 2))
+#define RTL839X_PHYREG_DATA_CTRL	(0x03F0)
+
+/*
+ * Switch interrupts
+ */
+#define RTL838X_IMR_GLB			(0x1100)
+#define RTL838X_IMR_PORT_LINK_STS_CHG	(0x1104)
+#define RTL838X_ISR_GLB_SRC		(0x1148)
+#define RTL838X_ISR_PORT_LINK_STS_CHG	(0x114C)
+#define RTL839X_IMR_GLB			(0x0064)
+#define RTL839X_IMR_PORT_LINK_STS_CHG	(0x0068)
+#define RTL839X_ISR_GLB_SRC		(0x009c)
+#define RTL839X_ISR_PORT_LINK_STS_CHG	(0x00a0)
+
+/* Definition of family IDs */
+#define RTL8389_FAMILY_ID   (0x8389)
+#define RTL8328_FAMILY_ID   (0x8328)
+#define RTL8390_FAMILY_ID   (0x8390)
+#define RTL8350_FAMILY_ID   (0x8350)
+#define RTL8380_FAMILY_ID   (0x8380)
+#define RTL8330_FAMILY_ID   (0x8330)
+
+struct rtl83xx_soc_info {
+	unsigned char *name;
+	unsigned int id;
+	unsigned int family;
+	unsigned char *compatible;
+	volatile void *sw_base;
+	volatile void *icu_base;
+};
+
+/* rtl83xx-related functions used across subsystems */
+int rtl838x_smi_wait_op(int timeout);
+int rtl838x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
+int rtl838x_write_phy(u32 port, u32 page, u32 reg, u32 val);
+int rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
+int rtl839x_write_phy(u32 port, u32 page, u32 reg, u32 val);
+
+#endif   /* _MACH_RTL838X_H_ */
diff --git a/target/linux/realtek/files-5.4/arch/mips/rtl838x/Makefile b/target/linux/realtek/files-5.4/arch/mips/rtl838x/Makefile
new file mode 100644
index 0000000000..8212dc3f48
--- /dev/null
+++ b/target/linux/realtek/files-5.4/arch/mips/rtl838x/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for the rtl838x specific parts of the kernel
+#
+
+obj-y := setup.o prom.o irq.o
diff --git a/target/linux/realtek/files-5.4/arch/mips/rtl838x/Platform b/target/linux/realtek/files-5.4/arch/mips/rtl838x/Platform
new file mode 100644
index 0000000000..4d48932d80
--- /dev/null
+++ b/target/linux/realtek/files-5.4/arch/mips/rtl838x/Platform
@@ -0,0 +1,6 @@
+#
+# Realtek RTL838x SoCs
+#
+platform-$(CONFIG_RTL838X) += rtl838x/
+cflags-$(CONFIG_RTL838X)   += -I$(srctree)/arch/mips/include/asm/mach-rtl838x/
+load-$(CONFIG_RTL838X)     += 0xffffffff80000000
diff --git a/target/linux/realtek/files-5.4/arch/mips/rtl838x/irq.c b/target/linux/realtek/files-5.4/arch/mips/rtl838x/irq.c
new file mode 100644
index 0000000000..9057d48543
--- /dev/null
+++ b/target/linux/realtek/files-5.4/arch/mips/rtl838x/irq.c
@@ -0,0 +1,167 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Realtek RTL83XX architecture specific IRQ handling
+ *
+ * based on the original BSP
+ * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com)
+ * Copyright (C) 2020 B. Koblitz
+ * Copyright (C) 2020 Bert Vermeulen <bert@biot.com>
+ * Copyright (C) 2020 John Crispin <john@phrozen.org>
+ */
+
+#include <linux/irqchip.h>
+#include <linux/spinlock.h>
+#include <linux/of_address.h>
+#include <asm/irq_cpu.h>
+#include <linux/of_irq.h>
+#include <asm/cevt-r4k.h>
+
+#include <mach-rtl83xx.h>
+#include "irq.h"
+
+#define REALTEK_CPU_IRQ_SHARED0		(MIPS_CPU_IRQ_BASE + 2)
+#define REALTEK_CPU_IRQ_UART		(MIPS_CPU_IRQ_BASE + 3)
+#define REALTEK_CPU_IRQ_SWITCH		(MIPS_CPU_IRQ_BASE + 4)
+#define REALTEK_CPU_IRQ_SHARED1		(MIPS_CPU_IRQ_BASE + 5)
+#define REALTEK_CPU_IRQ_EXTERNAL	(MIPS_CPU_IRQ_BASE + 6)
+#define REALTEK_CPU_IRQ_COUNTER		(MIPS_CPU_IRQ_BASE + 7)
+
+#define REG(x)				(rtl83xx_ictl_base + x)
+
+extern struct rtl83xx_soc_info soc_info;
+
+static DEFINE_RAW_SPINLOCK(irq_lock);
+static void __iomem *rtl83xx_ictl_base;
+
+static void rtl83xx_ictl_enable_irq(struct irq_data *i)
+{
+	unsigned long flags;
+	u32 value;
+
+	raw_spin_lock_irqsave(&irq_lock, flags);
+
+	value = rtl83xx_r32(REG(RTL83XX_ICTL_GIMR));
+	value |= BIT(i->hwirq);
+	rtl83xx_w32(value, REG(RTL83XX_ICTL_GIMR));
+
+	raw_spin_unlock_irqrestore(&irq_lock, flags);
+}
+
+static void rtl83xx_ictl_disable_irq(struct irq_data *i)
+{
+	unsigned long flags;
+	u32 value;
+
+	raw_spin_lock_irqsave(&irq_lock, flags);
+
+	value = rtl83xx_r32(REG(RTL83XX_ICTL_GIMR));
+	value &= ~BIT(i->hwirq);
+	rtl83xx_w32(value, REG(RTL83XX_ICTL_GIMR));
+
+	raw_spin_unlock_irqrestore(&irq_lock, flags);
+}
+
+static struct irq_chip rtl83xx_ictl_irq = {
+	.name = "RTL83xx",
+	.irq_enable = rtl83xx_ictl_enable_irq,
+	.irq_disable = rtl83xx_ictl_disable_irq,
+	.irq_ack = rtl83xx_ictl_disable_irq,
+	.irq_mask = rtl83xx_ictl_disable_irq,
+	.irq_unmask = rtl83xx_ictl_enable_irq,
+	.irq_eoi = rtl83xx_ictl_enable_irq,
+};
+
+static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
+{
+	irq_set_chip_and_handler(hw, &rtl83xx_ictl_irq, handle_level_irq);
+
+	return 0;
+}
+
+static const struct irq_domain_ops irq_domain_ops = {
+	.map = intc_map,
+	.xlate = irq_domain_xlate_onecell,
+};
+
+static void rtl838x_irq_dispatch(struct irq_desc *desc)
+{
+	unsigned int pending = rtl83xx_r32(REG(RTL83XX_ICTL_GIMR)) & rtl83xx_r32(REG(RTL83XX_ICTL_GISR));
+
+	if (pending) {
+		struct irq_domain *domain = irq_desc_get_handler_data(desc);
+		generic_handle_irq(irq_find_mapping(domain, __ffs(pending)));
+	} else {
+		spurious_interrupt();
+	}
+}
+
+asmlinkage void plat_irq_dispatch(void)
+{
+	unsigned int pending;
+
+	pending =  read_c0_cause() & read_c0_status() & ST0_IM;
+
+	if (pending & CAUSEF_IP7)
+		do_IRQ(REALTEK_CPU_IRQ_COUNTER);
+
+	else if (pending & CAUSEF_IP6)
+		do_IRQ(REALTEK_CPU_IRQ_EXTERNAL);
+
+	else if (pending & CAUSEF_IP5)
+		do_IRQ(REALTEK_CPU_IRQ_SHARED1);
+
+	else if (pending & CAUSEF_IP4)
+		do_IRQ(REALTEK_CPU_IRQ_SWITCH);
+
+	else if (pending & CAUSEF_IP3)
+		do_IRQ(REALTEK_CPU_IRQ_UART);
+
+	else if (pending & CAUSEF_IP2)
+		do_IRQ(REALTEK_CPU_IRQ_SHARED0);
+
+	else
+		spurious_interrupt();
+}
+
+static void __init icu_of_init(struct device_node *node, struct device_node *parent)
+{
+	struct irq_domain *domain;
+
+	domain = irq_domain_add_simple(node, 32, 0,
+				       &irq_domain_ops, NULL);
+        irq_set_chained_handler_and_data(2, rtl838x_irq_dispatch, domain);
+        irq_set_chained_handler_and_data(5, rtl838x_irq_dispatch, domain);
+
+	rtl83xx_ictl_base = of_iomap(node, 0);
+	if (!rtl83xx_ictl_base)
+		return;
+
+	/* Disable all cascaded interrupts */
+	rtl83xx_w32(0, REG(RTL83XX_ICTL_GIMR));
+
+	/* Set up interrupt routing */
+	rtl83xx_w32(RTL83XX_IRR0_SETTING, REG(RTL83XX_IRR0));
+	rtl83xx_w32(RTL83XX_IRR1_SETTING, REG(RTL83XX_IRR1));
+	rtl83xx_w32(RTL83XX_IRR2_SETTING, REG(RTL83XX_IRR2));
+	rtl83xx_w32(RTL83XX_IRR3_SETTING, REG(RTL83XX_IRR3));
+
+	/* Clear timer interrupt */
+	write_c0_compare(0);
+
+	/* Enable all CPU interrupts */
+	write_c0_status(read_c0_status() | ST0_IM);
+
+	/* Enable timer0 and uart0 interrupts */
+	rtl83xx_w32(BIT(RTL83XX_IRQ_TC0) | BIT(RTL83XX_IRQ_UART0), REG(RTL83XX_ICTL_GIMR));
+}
+
+static struct of_device_id __initdata of_irq_ids[] = {
+	{ .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_irq_of_init },
+	{ .compatible = "realtek,rt8380-intc", .data = icu_of_init },
+	{},
+};
+
+void __init arch_init_irq(void)
+{
+	of_irq_init(of_irq_ids);
+}
diff --git a/target/linux/realtek/files-5.4/arch/mips/rtl838x/prom.c b/target/linux/realtek/files-5.4/arch/mips/rtl838x/prom.c
new file mode 100644
index 0000000000..5278afae03
--- /dev/null
+++ b/target/linux/realtek/files-5.4/arch/mips/rtl838x/prom.c
@@ -0,0 +1,124 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * prom.c
+ * Early intialization code for the Realtek RTL838X SoC
+ *
+ * based on the original BSP by
+ * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com)
+ * Copyright (C) 2020 B. Koblitz
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/of_fdt.h>
+#include <linux/libfdt.h>
+#include <asm/bootinfo.h>
+#include <asm/addrspace.h>
+#include <asm/page.h>
+#include <asm/cpu.h>
+
+#include <mach-rtl83xx.h>
+
+extern char arcs_cmdline[];
+extern const char __appended_dtb;
+
+struct rtl83xx_soc_info soc_info;
+const void *fdt;
+
+const char *get_system_type(void)
+{
+	return soc_info.name;
+}
+
+void __init prom_free_prom_memory(void)
+{
+
+}
+
+void __init device_tree_init(void)
+{
+	if (!fdt_check_header(&__appended_dtb)) {
+		fdt = &__appended_dtb;
+		pr_info("Using appended Device Tree.\n");
+	}
+	initial_boot_params = (void *)fdt;
+	unflatten_and_copy_device_tree();
+}
+
+static void __init prom_init_cmdline(void)
+{
+	int argc = fw_arg0;
+	char **argv = (char **) KSEG1ADDR(fw_arg1);
+	int i;
+
+	arcs_cmdline[0] = '\0';
+
+	for (i = 0; i < argc; i++) {
+		char *p = (char *) KSEG1ADDR(argv[i]);
+
+		if (CPHYSADDR(p) && *p) {
+			strlcat(arcs_cmdline, p, sizeof(arcs_cmdline));
+			strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline));
+		}
+	}
+	pr_info("Kernel command line: %s\n", arcs_cmdline);
+}
+
+void __init prom_init(void)
+{
+	uint32_t model;
+
+	/* uart0 */
+        setup_8250_early_printk_port(0xb8002000, 2, 0);
+
+	soc_info.sw_base = RTL838X_SW_BASE;
+
+	model = sw_r32(RTL838X_MODEL_NAME_INFO) >> 16;
+	if (model != 0x8328 && model != 0x8330 && model != 0x8332 &&
+	    model != 0x8380 && model != 0x8382)
+		model = sw_r32(RTL839X_MODEL_NAME_INFO) >> 16;
+
+	soc_info.id = model;
+
+	switch (model) {
+	case 0x8328:
+		soc_info.name = "RTL8328";
+		soc_info.family = RTL8328_FAMILY_ID;
+		break;
+	case 0x8332:
+		soc_info.name = "RTL8332";
+		soc_info.family = RTL8380_FAMILY_ID;
+		break;
+	case 0x8380:
+		soc_info.name = "RTL8380";
+		soc_info.family = RTL8380_FAMILY_ID;
+		break;
+	case 0x8382:
+		soc_info.name = "RTL8382";
+		soc_info.family = RTL8380_FAMILY_ID;
+		break;
+	case 0x8390:
+		soc_info.name = "RTL8390";
+		soc_info.family = RTL8390_FAMILY_ID;
+		break;
+	case 0x8391:
+		soc_info.name = "RTL8391";
+		soc_info.family = RTL8390_FAMILY_ID;
+		break;
+	case 0x8392:
+		soc_info.name = "RTL8392";
+		soc_info.family = RTL8390_FAMILY_ID;
+		break;
+	case 0x8393:
+		soc_info.name = "RTL8393";
+		soc_info.family = RTL8390_FAMILY_ID;
+		break;
+	default:
+		soc_info.name = "DEFAULT";
+		soc_info.family = 0;
+	}
+	pr_info("SoC Type: %s\n", get_system_type());
+	prom_init_cmdline();
+}
diff --git a/target/linux/realtek/files-5.4/arch/mips/rtl838x/setup.c b/target/linux/realtek/files-5.4/arch/mips/rtl838x/setup.c
new file mode 100644
index 0000000000..dbabb0354b
--- /dev/null
+++ b/target/linux/realtek/files-5.4/arch/mips/rtl838x/setup.c
@@ -0,0 +1,109 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Setup for the Realtek RTL838X SoC:
+ *	Memory, Timer and Serial
+ *
+ * Copyright (C) 2020 B. Koblitz
+ * based on the original BSP by
+ * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com)
+ *
+ */
+
+#include <linux/console.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+
+#include <asm/addrspace.h>
+#include <asm/io.h>
+
+#include <asm/bootinfo.h>
+#include <linux/of_fdt.h>
+#include <asm/reboot.h>
+#include <asm/time.h>		/* for mips_hpt_frequency */
+#include <asm/prom.h>
+#include <asm/smp-ops.h>
+
+#include "mach-rtl83xx.h"
+
+extern int rtl838x_serial_init(void);
+extern struct rtl83xx_soc_info soc_info;
+
+u32 pll_reset_value;
+
+static void rtl838x_restart(char *command)
+{
+	u32 pll = sw_r32(RTL838X_PLL_CML_CTRL);
+	 /* SoC reset vector (in flash memory): on RTL839x platform preferred way to reset */
+	void (*f)(void) = (void *) 0xbfc00000;
+
+	pr_info("System restart.\n");
+	if (soc_info.family == RTL8390_FAMILY_ID) {
+		f();
+		/* If calling reset vector fails, reset entire chip */
+		sw_w32(0xFFFFFFFF, RTL839X_RST_GLB_CTRL);
+		/* If this fails, halt the CPU */
+		while
+			(1);
+	}
+
+	pr_info("PLL control register: %x, applying reset value %x\n",
+		pll, pll_reset_value);
+	sw_w32(3, RTL838X_INT_RW_CTRL);
+	sw_w32(pll_reset_value, RTL838X_PLL_CML_CTRL);
+	sw_w32(0, RTL838X_INT_RW_CTRL);
+
+	pr_info("Resetting RTL838X SoC\n");
+	/* Reset Global Control1 Register */
+	sw_w32(1, RTL838X_RST_GLB_CTRL_1);
+}
+
+static void rtl838x_halt(void)
+{
+	pr_info("System halted.\n");
+	while(1);
+}
+
+void __init plat_mem_setup(void)
+{
+	void *dtb;
+
+	set_io_port_base(KSEG1);
+	_machine_restart = rtl838x_restart;
+	_machine_halt = rtl838x_halt;
+
+	if (fw_passed_dtb) /* UHI interface */
+		dtb = (void *)fw_passed_dtb;
+	else if (__dtb_start != __dtb_end)
+		dtb = (void *)__dtb_start;
+	else
+		panic("no dtb found");
+
+	/*
+	 * Load the devicetree. This causes the chosen node to be
+	 * parsed resulting in our memory appearing
+	 */
+	__dt_setup_arch(dtb);
+}
+
+void __init plat_time_init(void)
+{
+	struct device_node *np;
+	u32 freq = 500000000;
+
+	np = of_find_node_by_name(NULL, "cpus");
+	if (!np) {
+		pr_err("Missing 'cpus' DT node, using default frequency.");
+	} else {
+		if (of_property_read_u32(np, "frequency", &freq) < 0)
+			pr_err("No 'frequency' property in DT, using default.");
+		else
+			pr_info("CPU frequency from device tree: %d", freq);
+		of_node_put(np);
+	}
+
+	mips_hpt_frequency = freq / 2;
+
+	pll_reset_value = sw_r32(RTL838X_PLL_CML_CTRL);
+}
diff --git a/target/linux/realtek/files-5.4/drivers/gpio/gpio-rtl8231.c b/target/linux/realtek/files-5.4/drivers/gpio/gpio-rtl8231.c
new file mode 100644
index 0000000000..be5efc2997
--- /dev/null
+++ b/target/linux/realtek/files-5.4/drivers/gpio/gpio-rtl8231.c
@@ -0,0 +1,321 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <linux/gpio/driver.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <asm/mach-rtl838x/mach-rtl83xx.h>
+
+/* RTL8231 registers for LED control */
+#define RTL8231_LED_FUNC0			0x0000
+#define RTL8231_GPIO_PIN_SEL(gpio)		((0x0002) + ((gpio) >> 4))
+#define RTL8231_GPIO_DIR(gpio)			((0x0005) + ((gpio) >> 4))
+#define RTL8231_GPIO_DATA(gpio)			((0x001C) + ((gpio) >> 4))
+
+struct rtl8231_gpios {
+	struct gpio_chip gc;
+	struct device *dev;
+	u32 id;
+	int smi_bus_id;
+	u16 reg_shadow[0x20];
+	u32 reg_cached;
+	int ext_gpio_indrt_access;
+};
+
+extern struct mutex smi_lock;
+extern struct rtl83xx_soc_info soc_info;
+
+static u32 rtl8231_read(struct rtl8231_gpios *gpios, u32 reg)
+{
+	u32 t = 0;
+	u8 bus_id = gpios->smi_bus_id;
+
+	reg &= 0x1f;
+	bus_id &= 0x1f;
+
+	/* Calculate read register address */
+	t = (bus_id << 2) | (reg << 7);
+
+	/* Set execution bit: cleared when operation completed */
+	t |= 1;
+	sw_w32(t, gpios->ext_gpio_indrt_access);
+	do {	/* TODO: Return 0x80000000 if timeout */
+		t = sw_r32(gpios->ext_gpio_indrt_access);
+	} while (t & 1);
+	pr_debug("%s: %x, %x, %x\n", __func__, bus_id, reg, (t & 0xffff0000) >> 16);
+
+	return (t & 0xffff0000) >> 16;
+}
+
+static int rtl8231_write(struct rtl8231_gpios *gpios, u32 reg, u32 data)
+{
+	u32 t = 0;
+	u8 bus_id = gpios->smi_bus_id;
+
+	pr_debug("%s: %x, %x, %x\n", __func__, bus_id, reg, data);
+	reg &= 0x1f;
+	bus_id &= 0x1f;
+
+	t = (bus_id << 2) | (reg << 7) | (data << 16);
+	/* Set write bit */
+	t |= 2;
+
+	/* Set execution bit: cleared when operation completed */
+	t |= 1;
+	sw_w32(t, gpios->ext_gpio_indrt_access);
+	do {	/* TODO: Return -1 if timeout */
+		t = sw_r32(gpios->ext_gpio_indrt_access);
+	} while (t & 1);
+
+	return 0;
+}
+
+static u32 rtl8231_read_cached(struct rtl8231_gpios *gpios, u32 reg)
+{
+	if (reg > 0x1f)
+		return 0;
+
+	if (gpios->reg_cached & (1 << reg))
+		return gpios->reg_shadow[reg];
+
+	return rtl8231_read(gpios, reg);
+}
+
+/* Set Direction of the RTL8231 pin:
+ * dir 1: input
+ * dir 0: output
+ */
+static int rtl8231_pin_dir(struct rtl8231_gpios *gpios, u32 gpio, u32 dir)
+{
+	u32 v;
+	int pin_sel_addr = RTL8231_GPIO_PIN_SEL(gpio);
+	int pin_dir_addr = RTL8231_GPIO_DIR(gpio);
+	int pin = gpio % 16;
+	int dpin = pin;
+
+	if (gpio > 31) {
+		pr_info("WARNING: HIGH pin\n");
+		dpin = pin << 5;
+		pin_dir_addr = pin_sel_addr;
+	}
+
+	v = rtl8231_read_cached(gpios, pin_dir_addr);
+	if (v & 0x80000000) {
+		pr_err("Error reading RTL8231\n");
+		return -1;
+	}
+
+	v = (v & ~(1 << dpin)) | (dir << dpin);
+	rtl8231_write(gpios, pin_dir_addr, v);
+	gpios->reg_shadow[pin_dir_addr] = v;
+	gpios->reg_cached |= 1 << pin_dir_addr;
+	return 0;
+}
+
+static int rtl8231_pin_dir_get(struct rtl8231_gpios *gpios, u32 gpio, u32 *dir)
+{
+	/* dir 1: input
+	 * dir 0: output
+	 */
+
+	u32  v;
+	int pin_dir_addr = RTL8231_GPIO_DIR(gpio);
+	int pin = gpio % 16;
+
+	if (gpio > 31) {
+		pin_dir_addr = RTL8231_GPIO_PIN_SEL(gpio);
+		pin = pin << 5;
+	}
+
+	v = rtl8231_read(gpios, pin_dir_addr);
+	if (v & (1 << pin))
+		*dir = 1;
+	else
+		*dir = 0;
+	return 0;
+}
+
+static int rtl8231_pin_set(struct rtl8231_gpios *gpios, u32 gpio, u32 data)
+{
+	u32 v = rtl8231_read(gpios, RTL8231_GPIO_DATA(gpio));
+
+	pr_debug("%s: %d to %d\n", __func__, gpio, data);
+	if (v & 0x80000000) {
+		pr_err("Error reading RTL8231\n");
+		return -1;
+	}
+	v = (v & ~(1 << (gpio % 16))) | (data << (gpio % 16));
+	rtl8231_write(gpios, RTL8231_GPIO_DATA(gpio), v);
+	gpios->reg_shadow[RTL8231_GPIO_DATA(gpio)] = v;
+	gpios->reg_cached |= 1 << RTL8231_GPIO_DATA(gpio);
+	return 0;
+}
+
+static int rtl8231_pin_get(struct rtl8231_gpios *gpios, u32 gpio, u16 *state)
+{
+	u32 v = rtl8231_read(gpios, RTL8231_GPIO_DATA(gpio));
+
+	if (v & 0x80000000) {
+		pr_err("Error reading RTL8231\n");
+		return -1;
+	}
+
+	*state = v & 0xffff;
+	return 0;
+}
+
+static int rtl8231_direction_input(struct gpio_chip *gc, unsigned int offset)
+{
+	int err;
+	struct rtl8231_gpios *gpios = gpiochip_get_data(gc);
+
+	pr_debug("%s: %d\n", __func__, offset);
+	mutex_lock(&smi_lock);
+	err = rtl8231_pin_dir(gpios, offset, 1);
+	mutex_unlock(&smi_lock);
+	return err;
+}
+
+static int rtl8231_direction_output(struct gpio_chip *gc, unsigned int offset, int value)
+{
+	int err;
+	struct rtl8231_gpios *gpios = gpiochip_get_data(gc);
+
+	pr_debug("%s: %d\n", __func__, offset);
+	mutex_lock(&smi_lock);
+	err = rtl8231_pin_dir(gpios, offset, 0);
+	mutex_unlock(&smi_lock);
+	if (!err)
+		err = rtl8231_pin_set(gpios, offset, value);
+	return err;
+}
+
+static int rtl8231_get_direction(struct gpio_chip *gc, unsigned int offset)
+{
+	u32 v = 0;
+	struct rtl8231_gpios *gpios = gpiochip_get_data(gc);
+
+	pr_debug("%s: %d\n", __func__, offset);
+	mutex_lock(&smi_lock);
+	rtl8231_pin_dir_get(gpios, offset, &v);
+	mutex_unlock(&smi_lock);
+	return v;
+}
+
+static int rtl8231_gpio_get(struct gpio_chip *gc, unsigned int offset)
+{
+	u16 state = 0;
+	struct rtl8231_gpios *gpios = gpiochip_get_data(gc);
+
+	mutex_lock(&smi_lock);
+	rtl8231_pin_get(gpios, offset, &state);
+	mutex_unlock(&smi_lock);
+	if (state & (1 << (offset % 16)))
+		return 1;
+	return 0;
+}
+
+void rtl8231_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
+{
+	struct rtl8231_gpios *gpios = gpiochip_get_data(gc);
+
+	rtl8231_pin_set(gpios, offset, value);
+}
+
+int rtl8231_init(struct rtl8231_gpios *gpios)
+{
+	pr_info("%s called, MDIO bus ID: %d\n", __func__, gpios->smi_bus_id);
+
+	if (soc_info.family == RTL8390_FAMILY_ID) {
+		sw_w32_mask(0x7 << 18, 0x4 << 18, RTL839X_LED_GLB_CTRL);
+		return 0;
+	}
+
+	/* Enable RTL8231 indirect access mode */
+	sw_w32_mask(0, 1, RTL838X_EXTRA_GPIO_CTRL);
+	sw_w32_mask(3, 1, RTL838X_DMY_REG5);
+
+	/* Enable RTL8231 via GPIO_A1 line
+	rtl838x_w32_mask(0, 1 << RTL838X_GPIO_A1, RTL838X_GPIO_PABC_DIR);
+	rtl838x_w32_mask(0, 1 << RTL838X_GPIO_A1, RTL838X_GPIO_PABC_DATA); */
+	mdelay(50); /* wait 50ms for reset */
+
+	/*Select GPIO functionality for pins 0-15, 16-31 and 32-37 */
+	rtl8231_write(gpios, RTL8231_GPIO_PIN_SEL(0), 0xffff);
+	rtl8231_write(gpios, RTL8231_GPIO_PIN_SEL(16), 0xffff);
+
+	gpios->reg_cached = 0;
+
+	return 0;
+}
+
+static const struct of_device_id rtl8231_gpio_of_match[] = {
+	{ .compatible = "realtek,rtl8231-gpio" },
+	{},
+};
+
+MODULE_DEVICE_TABLE(of, rtl8231_gpio_of_match);
+
+static int rtl8231_gpio_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
+	struct rtl8231_gpios *gpios;
+	int err;
+	u8 indirect_bus_id;
+
+	pr_info("Probing RTL8231 GPIOs\n");
+
+	if (!np) {
+		dev_err(&pdev->dev, "No DT found\n");
+		return -EINVAL;
+	}
+
+	gpios = devm_kzalloc(dev, sizeof(*gpios), GFP_KERNEL);
+	if (!gpios)
+		return -ENOMEM;
+
+	gpios->id = soc_info.id;
+	if (soc_info.family == RTL8380_FAMILY_ID) {
+		gpios->ext_gpio_indrt_access = RTL838X_EXT_GPIO_INDRT_ACCESS;
+	}
+
+	if (soc_info.family == RTL8390_FAMILY_ID) {
+		gpios->ext_gpio_indrt_access = RTL839X_EXT_GPIO_INDRT_ACCESS;
+	}
+
+	if (!of_property_read_u8(np, "indirect-access-bus-id", &indirect_bus_id)) {
+		gpios->smi_bus_id = indirect_bus_id;
+		rtl8231_init(gpios);
+	}
+
+	gpios->dev = dev;
+	gpios->gc.base = 160;
+	gpios->gc.ngpio = 36;
+	gpios->gc.label = "rtl8231";
+	gpios->gc.parent = dev;
+	gpios->gc.owner = THIS_MODULE;
+	gpios->gc.can_sleep = true;
+
+	gpios->gc.direction_input = rtl8231_direction_input;
+	gpios->gc.direction_output = rtl8231_direction_output;
+	gpios->gc.set = rtl8231_gpio_set;
+	gpios->gc.get = rtl8231_gpio_get;
+	gpios->gc.get_direction = rtl8231_get_direction;
+
+	err = devm_gpiochip_add_data(dev, &gpios->gc, gpios);
+	return err;
+}
+
+static struct platform_driver rtl8231_gpio_driver = {
+	.driver = {
+		.name = "rtl8231-gpio",
+		.of_match_table	= rtl8231_gpio_of_match,
+	},
+	.probe = rtl8231_gpio_probe,
+};
+
+module_platform_driver(rtl8231_gpio_driver);
+
+MODULE_DESCRIPTION("Realtek RTL8231 GPIO expansion chip support");
+MODULE_LICENSE("GPL v2");
diff --git a/target/linux/realtek/files-5.4/drivers/gpio/gpio-rtl838x.c b/target/linux/realtek/files-5.4/drivers/gpio/gpio-rtl838x.c
new file mode 100644
index 0000000000..92cf5f765a
--- /dev/null
+++ b/target/linux/realtek/files-5.4/drivers/gpio/gpio-rtl838x.c
@@ -0,0 +1,425 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <linux/gpio/driver.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <asm/mach-rtl838x/mach-rtl83xx.h>
+
+/* RTL8231 registers for LED control */
+#define RTL8231_LED_FUNC0			0x0000
+#define RTL8231_GPIO_PIN_SEL(gpio)		((0x0002) + ((gpio) >> 4))
+#define RTL8231_GPIO_DIR(gpio)			((0x0005) + ((gpio) >> 4))
+#define RTL8231_GPIO_DATA(gpio)			((0x001C) + ((gpio) >> 4))
+
+struct rtl838x_gpios {
+	struct gpio_chip gc;
+	u32 id;
+	struct device *dev;
+	int irq;
+	int num_leds;
+	int min_led;
+	int leds_per_port;
+	u32 led_mode;
+	int led_glb_ctrl;
+	int led_sw_ctrl;
+	int (*led_sw_p_ctrl)(int port);
+	int (*led_sw_p_en_ctrl)(int port);
+	int (*ext_gpio_dir)(int i);
+	int (*ext_gpio_data)(int i);
+};
+
+inline int rtl838x_ext_gpio_dir(int i)
+{
+	return RTL838X_EXT_GPIO_DIR + ((i >>5) << 2);
+}
+
+inline int rtl839x_ext_gpio_dir(int i)
+{
+	return RTL839X_EXT_GPIO_DIR + ((i >>5) << 2);
+}
+
+inline int rtl838x_ext_gpio_data(int i)
+{
+	return RTL838X_EXT_GPIO_DATA + ((i >>5) << 2);
+}
+
+inline int rtl839x_ext_gpio_data(int i)
+{
+	return RTL839X_EXT_GPIO_DATA + ((i >>5) << 2);
+}
+
+inline int rtl838x_led_sw_p_ctrl(int p)
+{
+	return RTL838X_LED_SW_P_CTRL + (p << 2);
+}
+
+inline int rtl839x_led_sw_p_ctrl(int p)
+{
+	return RTL839X_LED_SW_P_CTRL + (p << 2);
+}
+
+inline int rtl838x_led_sw_p_en_ctrl(int p)
+{
+	return RTL838X_LED_SW_P_EN_CTRL + ((p / 10) << 2);
+}
+
+inline int rtl839x_led_sw_p_en_ctrl(int p)
+{
+	return RTL839X_LED_SW_P_EN_CTRL + ((p / 10) << 2);
+}
+
+extern struct mutex smi_lock;
+extern struct rtl83xx_soc_info soc_info;
+
+
+void rtl838x_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
+{
+	int bit;
+	struct rtl838x_gpios *gpios = gpiochip_get_data(gc);
+
+	pr_debug("rtl838x_set: %d, value: %d\n", offset, value);
+	/* Internal GPIO of the RTL8380 */
+	if (offset < 32) {
+		if (value)
+			rtl83xx_w32_mask(0, BIT(offset), RTL838X_GPIO_PABC_DATA);
+		else
+			rtl83xx_w32_mask(BIT(offset), 0, RTL838X_GPIO_PABC_DATA);
+	}
+
+	/* LED driver for PWR and SYS */
+	if (offset >= 32 && offset < 64) {
+		bit = offset - 32;
+		if (value)
+			sw_w32_mask(0, BIT(bit), gpios->led_glb_ctrl);
+		else
+			sw_w32_mask(BIT(bit), 0, gpios->led_glb_ctrl);
+		return;
+	}
+
+	bit = (offset - 64) % 32;
+	/* First Port-LED */
+	if (offset >= 64 && offset < 96
+	   && offset >= (64 + gpios->min_led)
+	   && offset < (64 + gpios->min_led + gpios->num_leds)) {
+		if (value)
+			sw_w32_mask(7, 5, gpios->led_sw_p_ctrl(bit));
+		else
+			sw_w32_mask(7, 0, gpios->led_sw_p_ctrl(bit));
+	}
+	if (offset >= 96 && offset < 128
+	    && offset >= (96 + gpios->min_led)
+	    && offset < (96 + gpios->min_led + gpios->num_leds)) {
+		if (value)
+			sw_w32_mask(7 << 3, 5 << 3, gpios->led_sw_p_ctrl(bit));
+		else
+			sw_w32_mask(7 << 3, 0, gpios->led_sw_p_ctrl(bit));
+	}
+	if (offset >= 128 && offset < 160
+	    && offset >= (128 + gpios->min_led)
+	    && offset < (128 + gpios->min_led + gpios->num_leds)) {
+		if (value)
+			sw_w32_mask(7 << 6, 5 << 6, gpios->led_sw_p_ctrl(bit));
+		else
+			sw_w32_mask(7 << 6, 0, gpios->led_sw_p_ctrl(bit));
+	}
+	__asm__ volatile ("sync");
+}
+
+static int rtl838x_direction_input(struct gpio_chip *gc, unsigned int offset)
+{
+	pr_debug("%s: %d\n", __func__, offset);
+
+	if (offset < 32) {
+		rtl83xx_w32_mask(BIT(offset), 0, RTL838X_GPIO_PABC_DIR);
+		return 0;
+	}
+
+	/* Internal LED driver does not support input */
+	return -ENOTSUPP;
+}
+
+static int rtl838x_direction_output(struct gpio_chip *gc, unsigned int offset, int value)
+{
+	pr_debug("%s: %d\n", __func__, offset);
+	if (offset < 32)
+		rtl83xx_w32_mask(0, BIT(offset), RTL838X_GPIO_PABC_DIR);
+	rtl838x_gpio_set(gc, offset, value);
+
+	/* LED for PWR and SYS driver is direction output by default */
+	return 0;
+}
+
+static int rtl838x_get_direction(struct gpio_chip *gc, unsigned int offset)
+{
+	u32 v = 0;
+
+	pr_debug("%s: %d\n", __func__, offset);
+	if (offset < 32) {
+		v = rtl83xx_r32(RTL838X_GPIO_PABC_DIR);
+		if (v & BIT(offset))
+			return 0;
+		return 1;
+	}
+
+	/* LED driver for PWR and SYS is direction output by default */
+	if (offset >= 32 && offset < 64)
+		return 0;
+
+	return 0;
+}
+
+static int rtl838x_gpio_get(struct gpio_chip *gc, unsigned int offset)
+{
+	u32 v;
+	struct rtl838x_gpios *gpios = gpiochip_get_data(gc);
+
+	pr_debug("%s: %d\n", __func__, offset);
+
+	/* Internal GPIO of the RTL8380 */
+	if (offset < 32) {
+		v = rtl83xx_r32(RTL838X_GPIO_PABC_DATA);
+		if (v & BIT(offset))
+			return 1;
+		return 0;
+	}
+
+	/* LED driver for PWR and SYS */
+	if (offset >= 32 && offset < 64) {
+		v = sw_r32(gpios->led_glb_ctrl);
+		if (v & BIT(offset-32))
+			return 1;
+		return 0;
+	}
+
+/* BUG:
+	bit = (offset - 64) % 32;
+	if (offset >= 64 && offset < 96) {
+		if (sw_r32(RTL838X_LED1_SW_P_EN_CTRL) & BIT(bit))
+			return 1;
+		return 0;
+	}
+	if (offset >= 96 && offset < 128) {
+		if (sw_r32(RTL838X_LED1_SW_P_EN_CTRL) & BIT(bit))
+			return 1;
+		return 0;
+	}
+	if (offset >= 128 && offset < 160) {
+		if (sw_r32(RTL838X_LED1_SW_P_EN_CTRL) & BIT(bit))
+			return 1;
+		return 0;
+	}
+	*/ 
+	return 0;
+}
+
+void rtl8380_led_test(struct rtl838x_gpios *gpios, u32 mask)
+{
+	int i;
+	u32 led_gbl = sw_r32(gpios->led_glb_ctrl);
+	u32 mode_sel, led_p_en;
+
+	if (soc_info.family == RTL8380_FAMILY_ID) {
+		mode_sel = sw_r32(RTL838X_LED_MODE_SEL);
+		led_p_en = sw_r32(RTL838X_LED_P_EN_CTRL);
+	}
+
+	/* 2 Leds for ports 0-23 and 24-27, 3 would be 0x7 */
+	sw_w32_mask(0x3f, 0x3 | (0x3 << 3), gpios->led_glb_ctrl);
+
+	if(soc_info.family == RTL8380_FAMILY_ID) {
+		/* Enable all leds */
+		sw_w32(0xFFFFFFF, RTL838X_LED_P_EN_CTRL);
+	}
+	/* Enable software control of all leds */
+	sw_w32(0xFFFFFFF, gpios->led_sw_ctrl);
+	sw_w32(0xFFFFFFF, gpios->led_sw_p_en_ctrl(0));
+	sw_w32(0xFFFFFFF, gpios->led_sw_p_en_ctrl(10));
+	sw_w32(0x0000000, gpios->led_sw_p_en_ctrl(20));
+
+	for (i = 0; i < 28; i++) {
+		if (mask & BIT(i))
+			sw_w32(5 | (5 << 3) | (5 << 6), gpios->led_sw_p_ctrl(i));
+	}
+	msleep(3000);
+
+	if (soc_info.family == RTL8380_FAMILY_ID)
+		sw_w32(led_p_en, RTL838X_LED_P_EN_CTRL);
+	/* Disable software control of all leds */
+	sw_w32(0x0000000, gpios->led_sw_ctrl);
+	sw_w32(0x0000000, gpios->led_sw_p_en_ctrl(0));
+	sw_w32(0x0000000, gpios->led_sw_p_en_ctrl(10));
+	sw_w32(0x0000000, gpios->led_sw_p_en_ctrl(20));
+
+	sw_w32(led_gbl, gpios->led_glb_ctrl);
+	if (soc_info.family == RTL8380_FAMILY_ID)
+		sw_w32(mode_sel, RTL838X_LED_MODE_SEL);
+}
+
+void take_port_leds(struct rtl838x_gpios *gpios)
+{
+	int leds_per_port = gpios->leds_per_port;
+	int mode = gpios->led_mode;
+
+	pr_info("%s, %d, %x\n", __func__, leds_per_port, mode);
+	pr_debug("Bootloader settings: %x %x %x\n",
+		sw_r32(gpios->led_sw_p_en_ctrl(0)),
+		sw_r32(gpios->led_sw_p_en_ctrl(10)),
+		sw_r32(gpios->led_sw_p_en_ctrl(20))
+	);
+
+	if (soc_info.family == RTL8380_FAMILY_ID) {
+		pr_debug("led glb: %x, sel %x\n",
+			sw_r32(gpios->led_glb_ctrl), sw_r32(RTL838X_LED_MODE_SEL));
+		pr_debug("RTL838X_LED_P_EN_CTRL: %x", sw_r32(RTL838X_LED_P_EN_CTRL));
+		pr_debug("RTL838X_LED_MODE_CTRL: %x", sw_r32(RTL838X_LED_MODE_CTRL));
+		sw_w32_mask(3, 0, RTL838X_LED_MODE_SEL);
+		sw_w32(mode, RTL838X_LED_MODE_CTRL);
+	}
+
+	/* Enable software control of all leds */
+	sw_w32(0xFFFFFFF, gpios->led_sw_ctrl);
+	if (soc_info.family == RTL8380_FAMILY_ID)
+		sw_w32(0xFFFFFFF, RTL838X_LED_P_EN_CTRL);
+
+	sw_w32(0x0000000, gpios->led_sw_p_en_ctrl(0));
+	sw_w32(0x0000000, gpios->led_sw_p_en_ctrl(10));
+	sw_w32(0x0000000, gpios->led_sw_p_en_ctrl(20));
+
+	sw_w32_mask(0x3f, 0, gpios->led_glb_ctrl);
+	switch (leds_per_port) {
+	case 3:
+		sw_w32_mask(0, 0x7 | (0x7 << 3), gpios->led_glb_ctrl);
+		sw_w32(0xFFFFFFF, gpios->led_sw_p_en_ctrl(20));
+		/* FALLTHRU */
+	case 2:
+		sw_w32_mask(0, 0x3 | (0x3 << 3), gpios->led_glb_ctrl);
+		sw_w32(0xFFFFFFF, gpios->led_sw_p_en_ctrl(10));
+		/* FALLTHRU */
+	case 1:
+		sw_w32_mask(0, 0x1 | (0x1 << 3), gpios->led_glb_ctrl);
+		sw_w32(0xFFFFFFF, gpios->led_sw_p_en_ctrl(0));
+		break;
+	default:
+		pr_err("No LEDS configured for software control\n");
+	}
+}
+
+static const struct of_device_id rtl838x_gpio_of_match[] = {
+	{ .compatible = "realtek,rtl838x-gpio" },
+	{},
+};
+
+MODULE_DEVICE_TABLE(of, rtl838x_gpio_of_match);
+
+static int rtl838x_gpio_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
+	struct rtl838x_gpios *gpios;
+	int err;
+
+	pr_info("Probing RTL838X GPIOs\n");
+
+	if (!np) {
+		dev_err(&pdev->dev, "No DT found\n");
+		return -EINVAL;
+	}
+
+	gpios = devm_kzalloc(dev, sizeof(*gpios), GFP_KERNEL);
+	if (!gpios)
+		return -ENOMEM;
+
+	gpios->id = soc_info.id;
+
+	switch (gpios->id) {
+	case 0x8332:
+		pr_debug("Found RTL8332M GPIO\n");
+		break;
+	case 0x8380:
+		pr_debug("Found RTL8380M GPIO\n");
+		break;
+	case 0x8381:
+		pr_debug("Found RTL8381M GPIO\n");
+		break;
+	case 0x8382:
+		pr_debug("Found RTL8382M GPIO\n");
+		break;
+	case 0x8391:
+		pr_debug("Found RTL8391 GPIO\n");
+		break;
+	case 0x8393:
+		pr_debug("Found RTL8393 GPIO\n");
+		break;
+	default:
+		pr_err("Unknown GPIO chip id (%04x)\n", gpios->id);
+		return -ENODEV;
+	}
+
+	if (soc_info.family == RTL8380_FAMILY_ID) {
+		gpios->led_glb_ctrl = gpios->led_glb_ctrl;
+		gpios->led_sw_ctrl = RTL838X_LED_SW_CTRL;
+		gpios->led_sw_p_ctrl = rtl838x_led_sw_p_ctrl;
+		gpios->led_sw_p_en_ctrl = rtl838x_led_sw_p_en_ctrl;
+		gpios->ext_gpio_dir = rtl838x_ext_gpio_dir;
+		gpios->ext_gpio_data = rtl838x_ext_gpio_data;
+	}
+
+	if (soc_info.family == RTL8390_FAMILY_ID) {
+		gpios->led_glb_ctrl = RTL839X_LED_GLB_CTRL;
+		gpios->led_sw_ctrl = RTL839X_LED_SW_CTRL;
+		gpios->led_sw_p_ctrl = rtl839x_led_sw_p_ctrl;
+		gpios->led_sw_p_en_ctrl = rtl839x_led_sw_p_en_ctrl;
+		gpios->ext_gpio_dir = rtl839x_ext_gpio_dir;
+		gpios->ext_gpio_data = rtl839x_ext_gpio_data;
+	}
+
+	gpios->dev = dev;
+	gpios->gc.base = 0;
+	/* 0-31: internal
+	 * 32-63, LED control register
+	 * 64-95: PORT-LED 0
+	 * 96-127: PORT-LED 1
+	 * 128-159: PORT-LED 2
+	 */
+	gpios->gc.ngpio = 160;
+	gpios->gc.label = "rtl838x";
+	gpios->gc.parent = dev;
+	gpios->gc.owner = THIS_MODULE;
+	gpios->gc.can_sleep = true;
+	gpios->irq = 31;
+
+	gpios->gc.direction_input = rtl838x_direction_input;
+	gpios->gc.direction_output = rtl838x_direction_output;
+	gpios->gc.set = rtl838x_gpio_set;
+	gpios->gc.get = rtl838x_gpio_get;
+	gpios->gc.get_direction = rtl838x_get_direction;
+
+	if (of_property_read_bool(np, "take-port-leds")) {
+		if (of_property_read_u32(np, "leds-per-port", &gpios->leds_per_port))
+			gpios->leds_per_port = 2;
+		if (of_property_read_u32(np, "led-mode", &gpios->led_mode))
+			gpios->led_mode = (0x1ea << 15) | 0x1ea;
+		if (of_property_read_u32(np, "num-leds", &gpios->num_leds))
+			gpios->num_leds = 32;
+		if (of_property_read_u32(np, "min-led", &gpios->min_led))
+			gpios->min_led = 0;
+		take_port_leds(gpios);
+	}
+
+	err = devm_gpiochip_add_data(dev, &gpios->gc, gpios);
+	return err;
+}
+
+static struct platform_driver rtl838x_gpio_driver = {
+	.driver = {
+		.name = "rtl838x-gpio",
+		.of_match_table	= rtl838x_gpio_of_match,
+	},
+	.probe = rtl838x_gpio_probe,
+};
+
+module_platform_driver(rtl838x_gpio_driver);
+
+MODULE_DESCRIPTION("Realtek RTL838X GPIO API support");
+MODULE_LICENSE("GPL v2");
diff --git a/target/linux/realtek/files-5.4/drivers/mtd/spi-nor/rtl838x-nor.c b/target/linux/realtek/files-5.4/drivers/mtd/spi-nor/rtl838x-nor.c
new file mode 100644
index 0000000000..35bf53ea5a
--- /dev/null
+++ b/target/linux/realtek/files-5.4/drivers/mtd/spi-nor/rtl838x-nor.c
@@ -0,0 +1,603 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/spi-nor.h>
+
+#include "rtl838x-spi.h"
+#include <asm/mach-rtl838x/mach-rtl83xx.h>
+
+extern struct rtl83xx_soc_info soc_info;
+
+struct rtl838x_nor {
+	struct spi_nor nor;
+	struct device *dev;
+	volatile void __iomem *base;
+	bool fourByteMode;
+	u32 chipSize;
+	uint32_t flags;
+	uint32_t io_status;
+};
+
+static uint32_t spi_prep(struct rtl838x_nor *rtl838x_nor)
+{
+	/* Needed because of MMU constraints */
+	SPI_WAIT_READY;
+	spi_w32w(SPI_CS_INIT, SFCSR);	//deactivate CS0, CS1
+	spi_w32w(0, SFCSR);		//activate CS0,CS1
+	spi_w32w(SPI_CS_INIT, SFCSR);	//deactivate CS0, CS1
+
+	return (CS0 & rtl838x_nor->flags) ? (SPI_eCS0 & SPI_LEN_INIT)
+			: ((SPI_eCS1 & SPI_LEN_INIT) | SFCSR_CHIP_SEL);
+}
+
+static uint32_t rtl838x_nor_get_SR(struct rtl838x_nor *rtl838x_nor)
+{
+	uint32_t sfcsr, sfdr;
+
+	sfcsr = spi_prep(rtl838x_nor);
+	sfdr  = (SPINOR_OP_RDSR)<<24;
+
+	pr_debug("%s: rdid,sfcsr_val = %.8x,SFDR = %.8x\n", __func__, sfcsr, sfdr);
+	pr_debug("rdid,sfcsr = %.8x\n", sfcsr | SPI_LEN4);
+	spi_w32w(sfcsr, SFCSR);
+	spi_w32w(sfdr, SFDR);
+	spi_w32_mask(0, SPI_LEN4, SFCSR);
+	SPI_WAIT_READY;
+
+	return spi_r32(SFDR);
+}
+
+static void spi_write_disable(struct rtl838x_nor *rtl838x_nor)
+{
+	uint32_t sfcsr, sfdr;
+
+	sfcsr = spi_prep(rtl838x_nor);
+	sfdr = (SPINOR_OP_WRDI) << 24;
+	spi_w32w(sfcsr, SFCSR);
+	spi_w32w(sfdr, SFDR);
+	pr_debug("%s: sfcsr_val = %.8x,SFDR = %.8x", __func__, sfcsr, sfdr);
+
+	spi_prep(rtl838x_nor);
+}
+
+static void spi_write_enable(struct rtl838x_nor *rtl838x_nor)
+{
+	uint32_t sfcsr, sfdr;
+
+	sfcsr = spi_prep(rtl838x_nor);
+	sfdr = (SPINOR_OP_WREN) << 24;
+	spi_w32w(sfcsr, SFCSR);
+	spi_w32w(sfdr, SFDR);
+	pr_debug("%s: sfcsr_val = %.8x,SFDR = %.8x", __func__, sfcsr, sfdr);
+
+	spi_prep(rtl838x_nor);
+}
+
+static void spi_4b_set(struct rtl838x_nor *rtl838x_nor, bool enable)
+{
+	uint32_t sfcsr, sfdr;
+
+	sfcsr = spi_prep(rtl838x_nor);
+	if (enable)
+		sfdr = (SPINOR_OP_EN4B) << 24;
+	else
+		sfdr = (SPINOR_OP_EX4B) << 24;
+
+	spi_w32w(sfcsr, SFCSR);
+	spi_w32w(sfdr, SFDR);
+	pr_debug("%s: sfcsr_val = %.8x,SFDR = %.8x", __func__, sfcsr, sfdr);
+
+	spi_prep(rtl838x_nor);
+}
+
+static int rtl838x_get_addr_mode(struct rtl838x_nor *rtl838x_nor)
+{
+	int res = 3;
+	u32 reg;
+
+	sw_w32(0x3, RTL838X_INT_RW_CTRL);
+	if (!sw_r32(RTL838X_EXT_VERSION)) {
+		if (sw_r32(RTL838X_STRAP_DBG) & (1 << 29))
+			res = 4;
+	} else {
+		reg = sw_r32(RTL838X_PLL_CML_CTRL);
+		if ((reg & (1 << 30)) && (reg & (1 << 31)))
+			res = 4;
+		if ((!(reg & (1 << 30)))
+		     && sw_r32(RTL838X_STRAP_DBG) & (1 << 29))
+			res = 4;
+	}
+	sw_w32(0x0, RTL838X_INT_RW_CTRL);
+	return res;
+}
+
+static int rtl8390_get_addr_mode(struct rtl838x_nor *rtl838x_nor)
+{
+	if (spi_r32(RTL8390_SOC_SPI_MMIO_CONF) & (1 << 9))
+		return 4;
+	return 3;
+}
+
+ssize_t rtl838x_do_read(struct rtl838x_nor *rtl838x_nor, loff_t from,
+			       size_t length, u_char *buffer, uint8_t command)
+{
+	uint32_t sfcsr, sfdr;
+	uint32_t len = length;
+
+	sfcsr = spi_prep(rtl838x_nor);
+	sfdr = command << 24;
+
+	/* Perform SPINOR_OP_READ: 1 byte command & 3 byte addr*/
+	sfcsr |= SPI_LEN4;
+	sfdr |= from;
+
+	spi_w32w(sfcsr, SFCSR);
+	spi_w32w(sfdr, SFDR);
+
+	/* Read Data, 4 bytes at a time */
+	while (length >= 4) {
+		SPI_WAIT_READY;
+		*((uint32_t *) buffer) = spi_r32(SFDR);
+		buffer += 4;
+		length -= 4;
+	}
+
+	/* The rest needs to be read 1 byte a time */
+	sfcsr &= SPI_LEN_INIT|SPI_LEN1;
+	SPI_WAIT_READY;
+	spi_w32w(sfcsr, SFCSR);
+	while (length > 0) {
+		SPI_WAIT_READY;
+		*(buffer) = spi_r32(SFDR) >> 24;
+		buffer++;
+		length--;
+	}
+	return len;
+}
+
+/*
+ * Do fast read in 3 or 4 Byte addressing mode
+ */
+static ssize_t rtl838x_do_4bf_read(struct rtl838x_nor *rtl838x_nor, loff_t from,
+			       size_t length, u_char *buffer, uint8_t command)
+{
+	int sfcsr_addr_len = rtl838x_nor->fourByteMode ? 0x3 : 0x2;
+	int sfdr_addr_shift = rtl838x_nor->fourByteMode ? 0 : 8;
+	uint32_t sfcsr;
+	uint32_t len = length;
+
+	pr_debug("Fast read from %llx, len %x, shift %d\n",
+		 from, sfcsr_addr_len, sfdr_addr_shift);
+	sfcsr = spi_prep(rtl838x_nor);
+
+	/* Send read command */
+	spi_w32w(sfcsr | SPI_LEN1, SFCSR);
+	spi_w32w(command << 24, SFDR);
+
+	/* Send address */
+	spi_w32w(sfcsr | (sfcsr_addr_len << 28), SFCSR);
+	spi_w32w(from << sfdr_addr_shift, SFDR);
+
+	/* Dummy cycles */
+	spi_w32w(sfcsr | SPI_LEN1, SFCSR);
+	spi_w32w(0, SFDR);
+
+	/* Start reading */
+	spi_w32w(sfcsr | SPI_LEN4, SFCSR);
+
+	/* Read Data, 4 bytes at a time */
+	while (length >= 4) {
+		SPI_WAIT_READY;
+		*((uint32_t *) buffer) = spi_r32(SFDR);
+		buffer += 4;
+		length -= 4;
+	}
+
+	/* The rest needs to be read 1 byte a time */
+	sfcsr &= SPI_LEN_INIT|SPI_LEN1;
+	SPI_WAIT_READY;
+	spi_w32w(sfcsr, SFCSR);
+	while (length > 0) {
+		SPI_WAIT_READY;
+		*(buffer) = spi_r32(SFDR) >> 24;
+		buffer++;
+		length--;
+	}
+	return len;
+
+}
+
+/*
+ * Do write (Page Programming) in 3 or 4 Byte addressing mode
+ */
+static ssize_t rtl838x_do_4b_write(struct rtl838x_nor *rtl838x_nor, loff_t to,
+				    size_t length, const u_char *buffer,
+				    uint8_t command)
+{
+	int sfcsr_addr_len = rtl838x_nor->fourByteMode ? 0x3 : 0x2;
+	int sfdr_addr_shift = rtl838x_nor->fourByteMode ? 0 : 8;
+	uint32_t sfcsr;
+	uint32_t len = length;
+
+	pr_debug("Write to %llx, len %x, shift %d\n",
+		 to, sfcsr_addr_len, sfdr_addr_shift);
+	sfcsr = spi_prep(rtl838x_nor);
+
+	/* Send write command, command IO-width is 1 (bit 25/26) */
+	spi_w32w(sfcsr | SPI_LEN1 | (0 << 25), SFCSR);
+	spi_w32w(command << 24, SFDR);
+
+	/* Send address */
+	spi_w32w(sfcsr | (sfcsr_addr_len << 28) | (0 << 25), SFCSR);
+	spi_w32w(to << sfdr_addr_shift, SFDR);
+
+	/* Write Data, 1 byte at a time, if we are not 4-byte aligned */
+	if (((long)buffer) % 4) {
+		spi_w32w(sfcsr | SPI_LEN1, SFCSR);
+		while (length > 0 && (((long)buffer) % 4)) {
+			SPI_WAIT_READY;
+			spi_w32(*(buffer) << 24, SFDR);
+			buffer += 1;
+			length -= 1;
+		}
+	}
+
+	/* Now we can write 4 bytes at a time */
+	SPI_WAIT_READY;
+	spi_w32w(sfcsr | SPI_LEN4, SFCSR);
+	while (length >= 4) {
+		SPI_WAIT_READY;
+		spi_w32(*((uint32_t *)buffer), SFDR);
+		buffer += 4;
+		length -= 4;
+	}
+
+	/* Final bytes might need to be written 1 byte at a time, again */
+	SPI_WAIT_READY;
+	spi_w32w(sfcsr | SPI_LEN1, SFCSR);
+	while (length > 0) {
+		SPI_WAIT_READY;
+		spi_w32(*(buffer) << 24, SFDR);
+		buffer++;
+		length--;
+	}
+	return len;
+}
+
+static ssize_t rtl838x_nor_write(struct spi_nor *nor, loff_t to, size_t len,
+				 const u_char *buffer)
+{
+	int ret = 0;
+	uint32_t offset = 0;
+	struct rtl838x_nor *rtl838x_nor = nor->priv;
+	size_t l = len;
+	uint8_t cmd = SPINOR_OP_PP;
+
+	/* Do write in 4-byte mode on large Macronix chips */
+	if (rtl838x_nor->fourByteMode) {
+		cmd = SPINOR_OP_PP_4B;
+		spi_4b_set(rtl838x_nor, true);
+	}
+
+	pr_debug("In %s %8x to: %llx\n", __func__,
+		 (unsigned int) rtl838x_nor, to);
+
+	while (l >= SPI_MAX_TRANSFER_SIZE) {
+		while
+			(rtl838x_nor_get_SR(rtl838x_nor) & SPI_WIP);
+		do {
+			spi_write_enable(rtl838x_nor);
+		} while (!(rtl838x_nor_get_SR(rtl838x_nor) & SPI_WEL));
+		ret = rtl838x_do_4b_write(rtl838x_nor, to + offset,
+				SPI_MAX_TRANSFER_SIZE, buffer+offset, cmd);
+		l -= SPI_MAX_TRANSFER_SIZE;
+		offset += SPI_MAX_TRANSFER_SIZE;
+	}
+
+	if (l > 0) {
+		while
+			(rtl838x_nor_get_SR(rtl838x_nor) & SPI_WIP);
+		do {
+			spi_write_enable(rtl838x_nor);
+		} while (!(rtl838x_nor_get_SR(rtl838x_nor) & SPI_WEL));
+		ret = rtl838x_do_4b_write(rtl838x_nor, to+offset,
+					  len, buffer+offset, cmd);
+	}
+
+	return len;
+}
+
+static ssize_t rtl838x_nor_read(struct spi_nor *nor, loff_t from,
+				size_t length, u_char *buffer)
+{
+	uint32_t offset = 0;
+	uint8_t cmd = SPINOR_OP_READ_FAST;
+	size_t l = length;
+	struct rtl838x_nor *rtl838x_nor = nor->priv;
+
+	/* Do fast read in 3, or 4-byte mode on large Macronix chips */
+	if (rtl838x_nor->fourByteMode) {
+		cmd = SPINOR_OP_READ_FAST_4B;
+		spi_4b_set(rtl838x_nor, true);
+	}
+
+	/* TODO: do timeout and return error */
+	pr_debug("Waiting for pending writes\n");
+	while
+		(rtl838x_nor_get_SR(rtl838x_nor) & SPI_WIP);
+	do {
+		spi_write_enable(rtl838x_nor);
+	} while (!(rtl838x_nor_get_SR(rtl838x_nor) & SPI_WEL));
+
+	pr_debug("cmd is %d\n", cmd);
+	pr_debug("%s: addr %.8llx to addr %.8x, cmd %.8x, size %d\n", __func__,
+		 from, (u32)buffer, (u32)cmd, length);
+
+	while (l >= SPI_MAX_TRANSFER_SIZE) {
+		rtl838x_do_4bf_read(rtl838x_nor, from + offset,
+				    SPI_MAX_TRANSFER_SIZE, buffer+offset, cmd);
+		l -= SPI_MAX_TRANSFER_SIZE;
+		offset += SPI_MAX_TRANSFER_SIZE;
+	}
+
+	if (l > 0)
+		rtl838x_do_4bf_read(rtl838x_nor, from + offset, l, buffer+offset, cmd);
+
+	return length;
+}
+
+static int rtl838x_erase(struct spi_nor *nor, loff_t offs)
+{
+	struct rtl838x_nor *rtl838x_nor = nor->priv;
+	int sfcsr_addr_len = rtl838x_nor->fourByteMode ? 0x3 : 0x2;
+	int sfdr_addr_shift = rtl838x_nor->fourByteMode ? 0 : 8;
+	uint32_t sfcsr;
+	uint8_t cmd = SPINOR_OP_SE;
+
+	pr_debug("Erasing sector at %llx\n", offs);
+
+	/* Do erase in 4-byte mode on large Macronix chips */
+	if (rtl838x_nor->fourByteMode) {
+		cmd = SPINOR_OP_SE_4B;
+		spi_4b_set(rtl838x_nor, true);
+	}
+	/* TODO: do timeout and return error */
+	while
+		(rtl838x_nor_get_SR(rtl838x_nor) & SPI_WIP);
+	do {
+		spi_write_enable(rtl838x_nor);
+	} while (!(rtl838x_nor_get_SR(rtl838x_nor) & SPI_WEL));
+
+	sfcsr = spi_prep(rtl838x_nor);
+
+	/* Send erase command, command IO-width is 1 (bit 25/26) */
+	spi_w32w(sfcsr | SPI_LEN1 | (0 << 25), SFCSR);
+	spi_w32w(cmd << 24, SFDR);
+
+	/* Send address */
+	spi_w32w(sfcsr | (sfcsr_addr_len << 28) | (0 << 25), SFCSR);
+	spi_w32w(offs << sfdr_addr_shift, SFDR);
+
+	return 0;
+}
+
+static int rtl838x_nor_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
+{
+	int length = len;
+	u8 *buffer = buf;
+	uint32_t sfcsr, sfdr;
+	struct rtl838x_nor *rtl838x_nor = nor->priv;
+
+	pr_debug("In %s: opcode %x, len %x\n", __func__, opcode, len);
+
+	sfcsr = spi_prep(rtl838x_nor);
+	sfdr = opcode << 24;
+
+	sfcsr |= SPI_LEN1;
+
+	spi_w32w(sfcsr, SFCSR);
+	spi_w32w(sfdr, SFDR);
+
+	while (length > 0) {
+		SPI_WAIT_READY;
+		*(buffer) = spi_r32(SFDR) >> 24;
+		buffer++;
+		length--;
+	}
+
+	return len;
+}
+
+static int rtl838x_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
+{
+	uint32_t sfcsr, sfdr;
+	struct rtl838x_nor *rtl838x_nor = nor->priv;
+
+	pr_debug("In %s, opcode %x, len %x\n", __func__, opcode, len);
+	sfcsr = spi_prep(rtl838x_nor);
+	sfdr = opcode << 24;
+
+	if (len == 1) { /* SPINOR_OP_WRSR */
+		sfdr |= buf[0];
+		sfcsr |= SPI_LEN2;
+	}
+	spi_w32w(sfcsr, SFCSR);
+	spi_w32w(sfdr, SFDR);
+	return 0;
+}
+
+static int spi_enter_sio(struct spi_nor *nor)
+{
+	uint32_t sfcsr, sfcr2, sfdr;
+	uint32_t ret = 0, reg = 0, size_bits;
+	struct rtl838x_nor *rtl838x_nor = nor->priv;
+
+	pr_debug("In %s\n", __func__);
+	rtl838x_nor->io_status = 0;
+	sfdr = SPI_C_RSTQIO << 24;
+	sfcsr = spi_prep(rtl838x_nor);
+
+	reg = spi_r32(SFCR2);
+	pr_debug("SFCR2: %x, size %x, rdopt: %x\n", reg, SFCR2_GETSIZE(reg),
+						  (reg & SFCR2_RDOPT));
+	size_bits = rtl838x_nor->fourByteMode ? SFCR2_SIZE(0x6) : SFCR2_SIZE(0x7);
+
+	sfcr2 = SFCR2_HOLD_TILL_SFDR2 | size_bits
+		| (reg & SFCR2_RDOPT) | SFCR2_CMDIO(0)
+		| SFCR2_ADDRIO(0) | SFCR2_DUMMYCYCLE(4)
+		| SFCR2_DATAIO(0) | SFCR2_SFCMD(SPINOR_OP_READ_FAST);
+	pr_debug("SFCR2: %x, size %x\n", reg, SFCR2_GETSIZE(reg));
+
+	SPI_WAIT_READY;
+	spi_w32w(sfcr2, SFCR2);
+	spi_w32w(sfcsr, SFCSR);
+	spi_w32w(sfdr, SFDR);
+
+	spi_w32_mask(SFCR2_HOLD_TILL_SFDR2, 0, SFCR2);
+	rtl838x_nor->io_status &= ~IOSTATUS_CIO_MASK;
+	rtl838x_nor->io_status |= CIO1;
+
+	spi_prep(rtl838x_nor);
+
+	return ret;
+}
+
+int rtl838x_spi_nor_scan(struct spi_nor *nor, const char *name)
+{
+	static const struct spi_nor_hwcaps hwcaps = {
+		.mask = SNOR_HWCAPS_READ | SNOR_HWCAPS_PP
+			| SNOR_HWCAPS_READ_FAST
+	};
+
+	struct rtl838x_nor *rtl838x_nor = nor->priv;
+
+	pr_debug("In %s\n", __func__);
+
+	spi_w32_mask(0, SFCR_EnableWBO, SFCR);
+	spi_w32_mask(0, SFCR_EnableRBO, SFCR);
+
+	rtl838x_nor->flags = CS0 | R_MODE;
+
+	spi_nor_scan(nor, NULL, &hwcaps);
+	pr_debug("------------- Got size: %llx\n", nor->mtd.size);
+
+	return 0;
+}
+
+int rtl838x_nor_init(struct rtl838x_nor *rtl838x_nor,
+			struct device_node *flash_node)
+{
+	int ret;
+	struct spi_nor *nor;
+
+	pr_info("%s called\n", __func__);
+	nor = &rtl838x_nor->nor;
+	nor->dev = rtl838x_nor->dev;
+	nor->priv = rtl838x_nor;
+	spi_nor_set_flash_node(nor, flash_node);
+
+	nor->read_reg = rtl838x_nor_read_reg;
+	nor->write_reg = rtl838x_nor_write_reg;
+	nor->read = rtl838x_nor_read;
+	nor->write = rtl838x_nor_write;
+	nor->erase = rtl838x_erase;
+	nor->mtd.name = "rtl838x_nor";
+	nor->erase_opcode = rtl838x_nor->fourByteMode ? SPINOR_OP_SE_4B
+					: SPINOR_OP_SE;
+	/* initialized with NULL */
+	ret = rtl838x_spi_nor_scan(nor, NULL);
+	if (ret)
+		return ret;
+
+	spi_enter_sio(nor);
+	spi_write_disable(rtl838x_nor);
+
+	ret = mtd_device_parse_register(&nor->mtd, NULL, NULL, NULL, 0);
+	return ret;
+}
+
+static int rtl838x_nor_drv_probe(struct platform_device *pdev)
+{
+	struct device_node *flash_np;
+	struct resource *res;
+	int ret;
+	struct rtl838x_nor *rtl838x_nor;
+	int addrMode;
+
+	pr_info("Initializing rtl838x_nor_driver\n");
+	if (!pdev->dev.of_node) {
+		dev_err(&pdev->dev, "No DT found\n");
+		return -EINVAL;
+	}
+
+	rtl838x_nor = devm_kzalloc(&pdev->dev, sizeof(*rtl838x_nor), GFP_KERNEL);
+	if (!rtl838x_nor)
+		return -ENOMEM;
+	platform_set_drvdata(pdev, rtl838x_nor);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	rtl838x_nor->base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR((void *)rtl838x_nor->base))
+		return PTR_ERR((void *)rtl838x_nor->base);
+
+	pr_info("SPI resource base is %08x\n", (u32)rtl838x_nor->base);
+	rtl838x_nor->dev = &pdev->dev;
+
+	/* only support one attached flash */
+	flash_np = of_get_next_available_child(pdev->dev.of_node, NULL);
+	if (!flash_np) {
+		dev_err(&pdev->dev, "no SPI flash device to configure\n");
+		ret = -ENODEV;
+		goto nor_free;
+	}
+
+	/* Get the 3/4 byte address mode as configure by bootloader */
+	if (soc_info.family == RTL8390_FAMILY_ID)
+		addrMode = rtl8390_get_addr_mode(rtl838x_nor);
+	else
+		addrMode = rtl838x_get_addr_mode(rtl838x_nor);
+	pr_info("Address mode is %d bytes\n", addrMode);
+	if (addrMode == 4)
+		rtl838x_nor->fourByteMode = true;
+
+	ret = rtl838x_nor_init(rtl838x_nor, flash_np);
+
+nor_free:
+	return ret;
+}
+
+static int rtl838x_nor_drv_remove(struct platform_device *pdev)
+{
+/*	struct rtl8xx_nor *rtl838x_nor = platform_get_drvdata(pdev); */
+	return 0;
+}
+
+static const struct of_device_id rtl838x_nor_of_ids[] = {
+	{ .compatible = "realtek,rtl838x-nor"},
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, rtl838x_nor_of_ids);
+
+static struct platform_driver rtl838x_nor_driver = {
+	.probe = rtl838x_nor_drv_probe,
+	.remove = rtl838x_nor_drv_remove,
+	.driver = {
+		.name = "rtl838x-nor",
+		.pm = NULL,
+		.of_match_table = rtl838x_nor_of_ids,
+	},
+};
+
+module_platform_driver(rtl838x_nor_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("RTL838x SPI NOR Flash Driver");
diff --git a/target/linux/realtek/files-5.4/drivers/mtd/spi-nor/rtl838x-spi.h b/target/linux/realtek/files-5.4/drivers/mtd/spi-nor/rtl838x-spi.h
new file mode 100644
index 0000000000..de424c647a
--- /dev/null
+++ b/target/linux/realtek/files-5.4/drivers/mtd/spi-nor/rtl838x-spi.h
@@ -0,0 +1,111 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2009 Realtek Semiconductor Corp.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _RTL838X_SPI_H
+#define _RTL838X_SPI_H
+
+
+/*
+ * Register access macros
+ */
+
+#define spi_r32(reg)		readl(rtl838x_nor->base + reg)
+#define spi_w32(val, reg)	writel(val, rtl838x_nor->base + reg)
+#define spi_w32_mask(clear, set, reg)	\
+	spi_w32((spi_r32(reg) & ~(clear)) | (set), reg)
+
+#define SPI_WAIT_READY		do { \
+				} while (!(spi_r32(SFCSR) & SFCSR_SPI_RDY))
+
+#define spi_w32w(val, reg)	do { \
+					writel(val, rtl838x_nor->base + reg); \
+					SPI_WAIT_READY; \
+				} while (0)
+
+#define SFCR   (0x00)			/*SPI Flash Configuration Register*/
+	#define SFCR_CLK_DIV(val)	((val)<<29)
+	#define SFCR_EnableRBO		(1<<28)
+	#define SFCR_EnableWBO		(1<<27)
+	#define SFCR_SPI_TCS(val)	((val)<<23) /*4 bit, 1111 */
+
+#define SFCR2  (0x04)	/*For memory mapped I/O */
+	#define SFCR2_SFCMD(val)	((val)<<24) /*8 bit, 1111_1111 */
+	#define SFCR2_SIZE(val)		((val)<<21) /*3 bit, 111 */
+	#define SFCR2_RDOPT		(1<<20)
+	#define SFCR2_CMDIO(val)	((val)<<18) /*2 bit, 11 */
+	#define SFCR2_ADDRIO(val)	((val)<<16) /*2 bit, 11 */
+	#define SFCR2_DUMMYCYCLE(val)	((val)<<13) /*3 bit, 111 */
+	#define SFCR2_DATAIO(val)	((val)<<11) /*2 bit, 11 */
+	#define SFCR2_HOLD_TILL_SFDR2	(1<<10)
+	#define SFCR2_GETSIZE(x)	(((x)&0x00E00000)>>21)
+
+#define SFCSR  (0x08)	/*SPI Flash Control&Status Register*/
+	#define SFCSR_SPI_CSB0		(1<<31)
+	#define SFCSR_SPI_CSB1		(1<<30)
+	#define SFCSR_LEN(val)		((val)<<28)  /*2 bits*/
+	#define SFCSR_SPI_RDY		(1<<27)
+	#define SFCSR_IO_WIDTH(val)	((val)<<25)  /*2 bits*/
+	#define SFCSR_CHIP_SEL		(1<<24)
+	#define SFCSR_CMD_BYTE(val)	((val)<<16)  /*8 bit, 1111_1111 */
+
+#define SFDR   (0x0C)	/*SPI Flash Data Register*/
+#define SFDR2  (0x10)	/*SPI Flash Data Register - for post SPI bootup setting*/
+	#define SPI_CS_INIT		(SFCSR_SPI_CSB0 | SFCSR_SPI_CSB1 | SPI_LEN1)
+	#define SPI_CS0			SFCSR_SPI_CSB0
+	#define SPI_CS1			SFCSR_SPI_CSB1
+	#define SPI_eCS0		((SFCSR_SPI_CSB1)) /*and SFCSR to active CS0*/
+	#define SPI_eCS1		((SFCSR_SPI_CSB0)) /*and SFCSR to active CS1*/
+
+	#define SPI_WIP (1)		/* Write In Progress */
+	#define SPI_WEL (1<<1)		/* Write Enable Latch*/
+	#define SPI_SST_QIO_WIP (1<<7)	/* SST QIO Flash Write In Progress */
+	#define SPI_LEN_INIT 0xCFFFFFFF /* and SFCSR to init   */
+	#define SPI_LEN4    0x30000000	/* or SFCSR to set */
+	#define SPI_LEN3    0x20000000	/* or SFCSR to set */
+	#define SPI_LEN2    0x10000000	/* or SFCSR to set */
+	#define SPI_LEN1    0x00000000	/* or SFCSR to set */
+	#define SPI_SETLEN(val) do {		\
+			SPI_REG(SFCSR) &= 0xCFFFFFFF;   \
+			SPI_REG(SFCSR) |= (val-1)<<28;	\
+		} while (0)
+/*
+ * SPI interface control
+ */
+#define RTL8390_SOC_SPI_MMIO_CONF (0x04)
+
+#define IOSTATUS_CIO_MASK (0x00000038)
+
+/* Chip select: bits 4-7*/
+#define CS0 (1<<4)
+#define R_MODE 0x04
+
+/* io_status */
+#define IO1 (1<<0)
+#define IO2 (1<<1)
+#define CIO1 (1<<3)
+#define CIO2 (1<<4)
+#define CMD_IO1 (1<<6)
+#define W_ADDR_IO1 ((1)<<12)
+#define R_ADDR_IO2 ((2)<<9)
+#define R_DATA_IO2 ((2)<<15)
+#define W_DATA_IO1 ((1)<<18)
+
+/* Commands */
+#define SPI_C_RSTQIO 0xFF
+
+#define SPI_MAX_TRANSFER_SIZE 256
+
+#endif		/* _RTL838X_SPI_H */
diff --git a/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/Kconfig b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/Kconfig
new file mode 100644
index 0000000000..f293832eb5
--- /dev/null
+++ b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/Kconfig
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-only
+config NET_DSA_RTL83XX
+	tristate "Realtek RTL838x/RTL839x switch support"
+	depends on RTL838X
+	select NET_DSA_TAG_TRAILER
+	---help---
+	  This driver adds support for Realtek RTL83xx series switching.
+
diff --git a/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/Makefile b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/Makefile
new file mode 100644
index 0000000000..52cc151a56
--- /dev/null
+++ b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_NET_DSA_RTL83XX)	+= common.o dsa.o \
+	rtl838x.o rtl839x.o storm.o debugfs.o
diff --git a/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/common.c b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/common.c
new file mode 100644
index 0000000000..1b57ddc92c
--- /dev/null
+++ b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/common.c
@@ -0,0 +1,407 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <linux/of_mdio.h>
+#include <linux/of_platform.h>
+
+#include <asm/mach-rtl838x/mach-rtl83xx.h>
+#include "rtl83xx.h"
+
+extern struct rtl83xx_soc_info soc_info;
+
+extern const struct rtl838x_reg rtl838x_reg;
+extern const struct rtl838x_reg rtl839x_reg;
+extern const struct dsa_switch_ops rtl83xx_switch_ops;
+
+DEFINE_MUTEX(smi_lock);
+
+
+// TODO: unused
+static void dump_fdb(struct rtl838x_switch_priv *priv)
+{
+	struct rtl838x_l2_entry e;
+	int i;
+
+	mutex_lock(&priv->reg_mutex);
+
+	for (i = 0; i < priv->fib_entries; i++) {
+		priv->r->read_l2_entry_using_hash(i >> 2, i & 0x3, &e);
+
+		if (!e.valid) /* Check for invalid entry */
+			continue;
+
+		pr_debug("-> port %02d: mac %pM, vid: %d, rvid: %d, MC: %d, %d\n",
+			e.port, &e.mac[0], e.vid, e.rvid, e.is_ip_mc, e.is_ipv6_mc);
+	}
+
+	mutex_unlock(&priv->reg_mutex);
+}
+
+// TODO: unused
+static void rtl83xx_port_get_stp_state(struct rtl838x_switch_priv *priv, int port)
+{
+	u32 cmd, msti = 0;
+	u32 port_state[4];
+	int index, bit, i;
+	int pos = port;
+	int n = priv->family_id == RTL8380_FAMILY_ID ? 2 : 4;
+
+	/* CPU PORT can only be configured on RTL838x */
+	if (port >= priv->cpu_port || port > 51)
+		return;
+
+	mutex_lock(&priv->reg_mutex);
+
+	/* For the RTL839x, the bits are left-aligned in the 128 bit field */
+	if (priv->family_id == RTL8390_FAMILY_ID)
+		pos += 12;
+
+	index = n - (pos >> 4) - 1;
+	bit = (pos << 1) % 32;
+
+	if (priv->family_id == RTL8380_FAMILY_ID) {
+		cmd = BIT(15) /* Execute cmd */
+			| BIT(14) /* Read */
+			| 2 << 12 /* Table type 0b10 */
+			| (msti & 0xfff);
+	} else {
+		cmd = BIT(16) /* Execute cmd */
+			| 0 << 15 /* Read */
+			| 5 << 12 /* Table type 0b101 */
+			| (msti & 0xfff);
+	}
+	priv->r->exec_tbl0_cmd(cmd);
+
+	for (i = 0; i < n; i++)
+		port_state[i] = sw_r32(priv->r->tbl_access_data_0(i));
+
+	mutex_unlock(&priv->reg_mutex);
+}
+
+int rtl83xx_dsa_phy_read(struct dsa_switch *ds, int phy_addr, int phy_reg)
+{
+	u32 val;
+	u32 offset = 0;
+	struct rtl838x_switch_priv *priv = ds->priv;
+
+	if (phy_addr >= 24 && phy_addr <= 27
+		&& priv->ports[24].phy == PHY_RTL838X_SDS) {
+		if (phy_addr == 26)
+			offset = 0x100;
+		val = sw_r32(MAPLE_SDS4_FIB_REG0r + offset + (phy_reg << 2)) & 0xffff;
+		return val;
+	}
+
+	if (soc_info.family == RTL8390_FAMILY_ID)
+		rtl839x_read_phy(phy_addr, 0, phy_reg, &val);
+	else
+		rtl838x_read_phy(phy_addr, 0, phy_reg, &val);
+	return val;
+}
+
+int rtl83xx_dsa_phy_write(struct dsa_switch *ds, int phy_addr, int phy_reg, u16 val)
+{
+	u32 offset = 0;
+	struct rtl838x_switch_priv *priv = ds->priv;
+
+	if (phy_addr >= 24 && phy_addr <= 27
+	     && priv->ports[24].phy == PHY_RTL838X_SDS) {
+		if (phy_addr == 26)
+			offset = 0x100;
+		sw_w32(val, MAPLE_SDS4_FIB_REG0r + offset + (phy_reg << 2));
+		return 0;
+	}
+	if (soc_info.family == RTL8390_FAMILY_ID)
+		return rtl839x_write_phy(phy_addr, 0, phy_reg, val);
+	else
+		return rtl838x_write_phy(phy_addr, 0, phy_reg, val);
+}
+
+static int rtl83xx_mdio_read(struct mii_bus *bus, int addr, int regnum)
+{
+	int ret;
+	struct rtl838x_switch_priv *priv = bus->priv;
+
+	ret = rtl83xx_dsa_phy_read(priv->ds, addr, regnum);
+	return ret;
+}
+
+static int rtl83xx_mdio_write(struct mii_bus *bus, int addr, int regnum,
+				 u16 val)
+{
+	struct rtl838x_switch_priv *priv = bus->priv;
+
+	return rtl83xx_dsa_phy_write(priv->ds, addr, regnum, val);
+}
+
+static void rtl8380_sds_rst(int mac)
+{
+	u32 offset = (mac == 24) ? 0 : 0x100;
+
+	sw_w32_mask(1 << 11, 0, RTL8380_SDS4_FIB_REG0 + offset);
+	sw_w32_mask(0x3, 0, RTL838X_SDS4_REG28 + offset);
+	sw_w32_mask(0x3, 0x3, RTL838X_SDS4_REG28 + offset);
+	sw_w32_mask(0, 0x1 << 6, RTL838X_SDS4_DUMMY0 + offset);
+	sw_w32_mask(0x1 << 6, 0, RTL838X_SDS4_DUMMY0 + offset);
+	pr_debug("SERDES reset: %d\n", mac);
+}
+
+static int __init rtl8380_sds_power(int mac, int val)
+{
+	u32 mode = (val == 1) ? 0x4 : 0x9;
+	u32 offset = (mac == 24) ? 5 : 0;
+
+	if ((mac != 24) && (mac != 26)) {
+		pr_err("%s: not a fibre port: %d\n", __func__, mac);
+		return -1;
+	}
+
+	sw_w32_mask(0x1f << offset, mode << offset, RTL838X_SDS_MODE_SEL);
+
+	rtl8380_sds_rst(mac);
+
+	return 0;
+}
+
+static int __init rtl83xx_mdio_probe(struct rtl838x_switch_priv *priv)
+{
+	struct device *dev = priv->dev;
+	struct device_node *dn, *mii_np = dev->of_node;
+	struct mii_bus *bus;
+	int ret;
+	u32 pn;
+
+	pr_debug("In %s\n", __func__);
+	mii_np = of_find_compatible_node(NULL, NULL, "realtek,rtl838x-mdio");
+	if (mii_np) {
+		pr_debug("Found compatible MDIO node!\n");
+	} else {
+		dev_err(priv->dev, "no %s child node found", "mdio-bus");
+		return -ENODEV;
+	}
+
+	priv->mii_bus = of_mdio_find_bus(mii_np);
+	if (!priv->mii_bus) {
+		pr_debug("Deferring probe of mdio bus\n");
+		return -EPROBE_DEFER;
+	}
+	if (!of_device_is_available(mii_np))
+		ret = -ENODEV;
+
+	bus = devm_mdiobus_alloc(priv->ds->dev);
+	if (!bus)
+		return -ENOMEM;
+
+	bus->name = "rtl838x slave mii";
+	bus->read = &rtl83xx_mdio_read;
+	bus->write = &rtl83xx_mdio_write;
+	snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d", bus->name, dev->id);
+	bus->parent = dev;
+	priv->ds->slave_mii_bus = bus;
+	priv->ds->slave_mii_bus->priv = priv;
+
+	ret = mdiobus_register(priv->ds->slave_mii_bus);
+	if (ret && mii_np) {
+		of_node_put(dn);
+		return ret;
+	}
+
+	dn = mii_np;
+	for_each_node_by_name(dn, "ethernet-phy") {
+		if (of_property_read_u32(dn, "reg", &pn))
+			continue;
+
+		priv->ports[pn].dp = dsa_to_port(priv->ds, pn);
+
+		// Check for the integrated SerDes of the RTL8380M first
+		if (of_property_read_bool(dn, "phy-is-integrated")
+			&& priv->id == 0x8380 && pn >= 24) {
+			pr_debug("----> FÓUND A SERDES\n");
+			priv->ports[pn].phy = PHY_RTL838X_SDS;
+			continue;
+		}
+
+		if (of_property_read_bool(dn, "phy-is-integrated")
+			&& !of_property_read_bool(dn, "sfp")) {
+			priv->ports[pn].phy = PHY_RTL8218B_INT;
+			continue;
+		}
+
+		if (!of_property_read_bool(dn, "phy-is-integrated")
+			&& of_property_read_bool(dn, "sfp")) {
+			priv->ports[pn].phy = PHY_RTL8214FC;
+			continue;
+		}
+
+		if (!of_property_read_bool(dn, "phy-is-integrated")
+			&& !of_property_read_bool(dn, "sfp")) {
+			priv->ports[pn].phy = PHY_RTL8218B_EXT;
+			continue;
+		}
+	}
+
+	/* Disable MAC polling the PHY so that we can start configuration */
+	priv->r->set_port_reg_le(0ULL, priv->r->smi_poll_ctrl);
+
+	/* Enable PHY control via SoC */
+	if (priv->family_id == RTL8380_FAMILY_ID) {
+		/* Enable PHY control via SoC */
+		sw_w32_mask(0, BIT(15), RTL838X_SMI_GLB_CTRL);
+	} else {
+		/* Disable PHY polling via SoC */
+		sw_w32_mask(BIT(7), 0, RTL839X_SMI_GLB_CTRL);
+	}
+
+	/* Power on fibre ports and reset them if necessary */
+	if (priv->ports[24].phy == PHY_RTL838X_SDS) {
+		pr_debug("Powering on fibre ports & reset\n");
+		rtl8380_sds_power(24, 1);
+		rtl8380_sds_power(26, 1);
+	}
+
+	pr_debug("%s done\n", __func__);
+	return 0;
+}
+
+static int __init rtl83xx_get_l2aging(struct rtl838x_switch_priv *priv)
+{
+	int t = sw_r32(priv->r->l2_ctrl_1);
+
+	t &= priv->family_id == RTL8380_FAMILY_ID ? 0x7fffff : 0x1FFFFF;
+
+	if (priv->family_id == RTL8380_FAMILY_ID)
+		t = t * 128 / 625; /* Aging time in seconds. 0: L2 aging disabled */
+	else
+		t = (t * 3) / 5;
+
+	pr_debug("L2 AGING time: %d sec\n", t);
+	pr_debug("Dynamic aging for ports: %x\n", sw_r32(priv->r->l2_port_aging_out));
+	return t;
+}
+
+static int __init rtl83xx_sw_probe(struct platform_device *pdev)
+{
+	int err = 0, i;
+	struct rtl838x_switch_priv *priv;
+	struct device *dev = &pdev->dev;
+	u64 irq_mask;
+
+	pr_debug("Probing RTL838X switch device\n");
+	if (!pdev->dev.of_node) {
+		dev_err(dev, "No DT found\n");
+		return -EINVAL;
+	}
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->ds = dsa_switch_alloc(dev, DSA_MAX_PORTS);
+
+	if (!priv->ds)
+		return -ENOMEM;
+	priv->ds->dev = dev;
+	priv->ds->priv = priv;
+	priv->ds->ops = &rtl83xx_switch_ops;
+	priv->dev = dev;
+
+	priv->family_id = soc_info.family;
+	priv->id = soc_info.id;
+	if (soc_info.family == RTL8380_FAMILY_ID) {
+		priv->cpu_port = RTL838X_CPU_PORT;
+		priv->port_mask = 0x1f;
+		priv->r = &rtl838x_reg;
+		priv->ds->num_ports = 30;
+		priv->fib_entries = 8192;
+		rtl8380_get_version(priv);
+	} else {
+		priv->cpu_port = RTL839X_CPU_PORT;
+		priv->port_mask = 0x3f;
+		priv->r = &rtl839x_reg;
+		priv->ds->num_ports = 53;
+		priv->fib_entries = 16384;
+		rtl8390_get_version(priv);
+	}
+	pr_debug("Chip version %c\n", priv->version);
+
+	err = rtl83xx_mdio_probe(priv);
+	if (err) {
+		/* Probing fails the 1st time because of missing ethernet driver
+		 * initialization. Use this to disable traffic in case the bootloader left if on
+		 */
+		return err;
+	}
+	err = dsa_register_switch(priv->ds);
+	if (err) {
+		dev_err(dev, "Error registering switch: %d\n", err);
+		return err;
+	}
+
+	/* Enable link and media change interrupts. Are the SERDES masks needed? */
+	sw_w32_mask(0, 3, priv->r->isr_glb_src);
+	/* ... for all ports */
+	irq_mask = soc_info.family == RTL8380_FAMILY_ID ? 0x0FFFFFFF : 0xFFFFFFFFFFFFFULL;
+	priv->r->set_port_reg_le(irq_mask, priv->r->isr_port_link_sts_chg);
+	priv->r->set_port_reg_le(irq_mask, priv->r->imr_port_link_sts_chg);
+
+	priv->link_state_irq = platform_get_irq(pdev, 0);;
+	if (priv->family_id == RTL8380_FAMILY_ID) {
+		err = request_irq(priv->link_state_irq, rtl838x_switch_irq,
+				IRQF_SHARED, "rtl838x-link-state", priv->ds);
+	} else {
+		err = request_irq(priv->link_state_irq, rtl839x_switch_irq,
+				IRQF_SHARED, "rtl839x-link-state", priv->ds);
+	}
+	if (err) {
+		dev_err(dev, "Error setting up switch interrupt.\n");
+		/* Need to free allocated switch here */
+	}
+
+	/* Enable interrupts for switch */
+	sw_w32(0x1, priv->r->imr_glb);
+
+	rtl83xx_get_l2aging(priv);
+
+/*
+	if (priv->family_id == RTL8380_FAMILY_ID)
+		rtl83xx_storm_control_init(priv);
+*/
+
+	/* Clear all destination ports for mirror groups */
+	for (i = 0; i < 4; i++)
+		priv->mirror_group_ports[i] = -1;
+
+	rtl838x_dbgfs_init(priv);
+
+	return err;
+}
+
+static int rtl83xx_sw_remove(struct platform_device *pdev)
+{
+	// TODO:
+	pr_debug("Removing platform driver for rtl83xx-sw\n");
+	return 0;
+}
+
+static const struct of_device_id rtl83xx_switch_of_ids[] = {
+	{ .compatible = "realtek,rtl83xx-switch"},
+	{ /* sentinel */ }
+};
+
+
+MODULE_DEVICE_TABLE(of, rtl83xx_switch_of_ids);
+
+static struct platform_driver rtl83xx_switch_driver = {
+	.probe = rtl83xx_sw_probe,
+	.remove = rtl83xx_sw_remove,
+	.driver = {
+		.name = "rtl83xx-switch",
+		.pm = NULL,
+		.of_match_table = rtl83xx_switch_of_ids,
+	},
+};
+
+module_platform_driver(rtl83xx_switch_driver);
+
+MODULE_AUTHOR("B. Koblitz");
+MODULE_DESCRIPTION("RTL83XX SoC Switch Driver");
+MODULE_LICENSE("GPL");
diff --git a/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/debugfs.c b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/debugfs.c
new file mode 100644
index 0000000000..af24e8fa42
--- /dev/null
+++ b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/debugfs.c
@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <linux/debugfs.h>
+
+#include <asm/mach-rtl838x/mach-rtl83xx.h>
+#include "rtl838x.h"
+
+#define RTL838X_DRIVER_NAME "rtl838x"
+
+static const struct debugfs_reg32 port_ctrl_regs[] = {
+	{ .name = "port_isolation", .offset = RTL838X_PORT_ISO_CTRL(0), },
+	{ .name = "mac_force_mode", .offset = RTL838X_MAC_FORCE_MODE_CTRL, },
+};
+
+void rtl838x_dbgfs_cleanup(struct rtl838x_switch_priv *priv)
+{
+	debugfs_remove_recursive(priv->dbgfs_dir);
+
+//	kfree(priv->dbgfs_entries);
+}
+
+static int rtl838x_dbgfs_port_init(struct dentry *parent, struct rtl838x_switch_priv *priv,
+				   int port)
+{
+	struct dentry *port_dir;
+	struct debugfs_regset32 *port_ctrl_regset;
+
+	port_dir = debugfs_create_dir(priv->ports[port].dp->name, parent);
+
+	debugfs_create_x32("rate_uc", 0644, port_dir,
+			    (u32 *)(RTL838X_SW_BASE + RTL838X_STORM_CTRL_PORT_UC(port)));
+
+	debugfs_create_x32("rate_mc", 0644, port_dir,
+			    (u32 *)(RTL838X_SW_BASE + RTL838X_STORM_CTRL_PORT_BC(port)));
+
+	debugfs_create_x32("rate_bc", 0644, port_dir,
+			    (u32 *)(RTL838X_SW_BASE + RTL838X_STORM_CTRL_PORT_BC(port)));
+
+	debugfs_create_u32("id", 0444, port_dir, &priv->ports[port].dp->index);
+
+
+	debugfs_create_x32("vlan_port_tag_sts_ctrl", 0644, port_dir,
+			   (u32 *)(RTL838X_SW_BASE + RTL838X_VLAN_PORT_TAG_STS_CTRL(port)));
+
+	port_ctrl_regset = devm_kzalloc(priv->dev, sizeof(*port_ctrl_regset), GFP_KERNEL);
+	if (!port_ctrl_regset)
+		return -ENOMEM;
+
+	port_ctrl_regset->regs = port_ctrl_regs;
+	port_ctrl_regset->nregs = ARRAY_SIZE(port_ctrl_regs);
+	port_ctrl_regset->base = RTL838X_SW_BASE + (port << 2);
+	debugfs_create_regset32("port_ctrl", 0400, port_dir, port_ctrl_regset);
+
+	return 0;
+}
+
+void rtl838x_dbgfs_init(struct rtl838x_switch_priv *priv)
+{
+	struct dentry *rtl838x_dir;
+	struct dentry *port_dir;
+	struct debugfs_regset32 *port_ctrl_regset;
+	int ret, i;
+
+	rtl838x_dir = debugfs_lookup(RTL838X_DRIVER_NAME, NULL);
+	if (!rtl838x_dir)
+		rtl838x_dir = debugfs_create_dir(RTL838X_DRIVER_NAME, NULL);
+
+	priv->dbgfs_dir = rtl838x_dir;
+
+	debugfs_create_u32("soc", 0444, rtl838x_dir,
+			   (u32 *)(RTL838X_SW_BASE + RTL838X_MODEL_NAME_INFO));
+
+	/* Create one directory per port */
+	for (i = 0; i < priv->cpu_port; i++) {
+		if (priv->ports[i].phy) {
+			pr_debug("debugfs, port %d\n", i);
+			ret = rtl838x_dbgfs_port_init(rtl838x_dir, priv, i);
+			if (ret)
+				goto err;
+		}
+	}
+
+	/* Create directory for CPU-port */
+	port_dir = debugfs_create_dir("cpu_port", rtl838x_dir);	port_ctrl_regset = devm_kzalloc(priv->dev, sizeof(*port_ctrl_regset), GFP_KERNEL);
+	if (!port_ctrl_regset) {
+		ret = -ENOMEM;
+		goto err;
+	}
+
+	port_ctrl_regset->regs = port_ctrl_regs;
+	port_ctrl_regset->nregs = ARRAY_SIZE(port_ctrl_regs);
+	port_ctrl_regset->base = RTL838X_SW_BASE + (priv->cpu_port << 2);
+	debugfs_create_regset32("port_ctrl", 0400, port_dir, port_ctrl_regset);
+	debugfs_create_u8("id", 0444, port_dir, &priv->cpu_port);
+
+	return;
+err:
+	rtl838x_dbgfs_cleanup(priv);
+}
diff --git a/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/dsa.c b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/dsa.c
new file mode 100644
index 0000000000..a0717e1d9a
--- /dev/null
+++ b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/dsa.c
@@ -0,0 +1,1170 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <net/dsa.h>
+#include <linux/if_bridge.h>
+
+#include <asm/mach-rtl838x/mach-rtl83xx.h>
+#include "rtl83xx.h"
+
+
+extern struct rtl83xx_soc_info soc_info;
+
+
+static void rtl83xx_print_matrix(void)
+{
+	unsigned volatile int *ptr8;
+	volatile u64 *ptr9;
+	int i;
+
+	if (soc_info.family == RTL8380_FAMILY_ID) {
+		ptr8 = RTL838X_SW_BASE + RTL838X_PORT_ISO_CTRL(0);
+		for (i = 0; i < 28; i += 8)
+			pr_debug("> %8x %8x %8x %8x %8x %8x %8x %8x\n",
+				ptr8[i + 0], ptr8[i + 1], ptr8[i + 2], ptr8[i + 3],
+				ptr8[i + 4], ptr8[i + 5], ptr8[i + 6], ptr8[i + 7]);
+		pr_debug("CPU_PORT> %8x\n", ptr8[28]);
+	} else {
+		ptr9 = RTL838X_SW_BASE + RTL839X_PORT_ISO_CTRL(0);
+		for (i = 0; i < 52; i += 4)
+			pr_debug("> %16llx %16llx %16llx %16llx\n",
+				ptr9[i + 0], ptr9[i + 1], ptr9[i + 2], ptr9[i + 3]);
+		pr_debug("CPU_PORT> %16llx\n", ptr9[52]);
+	}
+
+}
+
+static void rtl83xx_init_stats(struct rtl838x_switch_priv *priv)
+{
+	mutex_lock(&priv->reg_mutex);
+
+	/* Enable statistics module: all counters plus debug.
+	 * On RTL839x all counters are enabled by default
+	 */
+	if (priv->family_id == RTL8380_FAMILY_ID)
+		sw_w32_mask(0, 3, RTL838X_STAT_CTRL);
+
+	/* Reset statistics counters */
+	sw_w32_mask(0, 1, priv->r->stat_rst);
+
+	mutex_unlock(&priv->reg_mutex);
+}
+
+static void rtl83xx_write_cam(int idx, u32 *r)
+{
+	u32 cmd = BIT(16) /* Execute cmd */
+		| BIT(15) /* Read */
+		| BIT(13) /* Table type 0b01 */
+		| (idx & 0x3f);
+
+	sw_w32(r[0], RTL838X_TBL_ACCESS_L2_DATA(0));
+	sw_w32(r[1], RTL838X_TBL_ACCESS_L2_DATA(1));
+	sw_w32(r[2], RTL838X_TBL_ACCESS_L2_DATA(2));
+
+	sw_w32(cmd, RTL838X_TBL_ACCESS_L2_CTRL);
+	do { }  while (sw_r32(RTL838X_TBL_ACCESS_L2_CTRL) & BIT(16));
+}
+
+static u64 rtl83xx_hash_key(struct rtl838x_switch_priv *priv, u64 mac, u32 vid)
+{
+	if (priv->family_id == RTL8380_FAMILY_ID)
+		return rtl838x_hash(priv, mac << 12 | vid);
+	else
+		return rtl839x_hash(priv, mac << 12 | vid);
+}
+
+static void rtl83xx_write_hash(int idx, u32 *r)
+{
+	u32 cmd = BIT(16) /* Execute cmd */
+		| 0 << 15 /* Write */
+		| 0 << 13 /* Table type 0b00 */
+		| (idx & 0x1fff);
+
+	sw_w32(0, RTL838X_TBL_ACCESS_L2_DATA(0));
+	sw_w32(0, RTL838X_TBL_ACCESS_L2_DATA(1));
+	sw_w32(0, RTL838X_TBL_ACCESS_L2_DATA(2));
+	sw_w32(cmd, RTL838X_TBL_ACCESS_L2_CTRL);
+	do { }  while (sw_r32(RTL838X_TBL_ACCESS_L2_CTRL) & BIT(16));
+}
+
+static void rtl83xx_enable_phy_polling(struct rtl838x_switch_priv *priv)
+{
+	int i;
+	u64 v = 0;
+
+	msleep(1000);
+	/* Enable all ports with a PHY, including the SFP-ports */
+	for (i = 0; i < priv->cpu_port; i++) {
+		if (priv->ports[i].phy)
+			v |= BIT(i);
+	}
+
+	pr_debug("%s: %16llx\n", __func__, v);
+	priv->r->set_port_reg_le(v, priv->r->smi_poll_ctrl);
+
+	/* PHY update complete */
+	if (priv->family_id == RTL8390_FAMILY_ID)
+		sw_w32_mask(0, BIT(7), RTL839X_SMI_GLB_CTRL);
+	else
+		sw_w32_mask(0, 0x8000, RTL838X_SMI_GLB_CTRL);
+}
+
+const struct rtl83xx_mib_desc rtl83xx_mib[] = {
+	MIB_DESC(2, 0xf8, "ifInOctets"),
+	MIB_DESC(2, 0xf0, "ifOutOctets"),
+	MIB_DESC(1, 0xec, "dot1dTpPortInDiscards"),
+	MIB_DESC(1, 0xe8, "ifInUcastPkts"),
+	MIB_DESC(1, 0xe4, "ifInMulticastPkts"),
+	MIB_DESC(1, 0xe0, "ifInBroadcastPkts"),
+	MIB_DESC(1, 0xdc, "ifOutUcastPkts"),
+	MIB_DESC(1, 0xd8, "ifOutMulticastPkts"),
+	MIB_DESC(1, 0xd4, "ifOutBroadcastPkts"),
+	MIB_DESC(1, 0xd0, "ifOutDiscards"),
+	MIB_DESC(1, 0xcc, ".3SingleCollisionFrames"),
+	MIB_DESC(1, 0xc8, ".3MultipleCollisionFrames"),
+	MIB_DESC(1, 0xc4, ".3DeferredTransmissions"),
+	MIB_DESC(1, 0xc0, ".3LateCollisions"),
+	MIB_DESC(1, 0xbc, ".3ExcessiveCollisions"),
+	MIB_DESC(1, 0xb8, ".3SymbolErrors"),
+	MIB_DESC(1, 0xb4, ".3ControlInUnknownOpcodes"),
+	MIB_DESC(1, 0xb0, ".3InPauseFrames"),
+	MIB_DESC(1, 0xac, ".3OutPauseFrames"),
+	MIB_DESC(1, 0xa8, "DropEvents"),
+	MIB_DESC(1, 0xa4, "tx_BroadcastPkts"),
+	MIB_DESC(1, 0xa0, "tx_MulticastPkts"),
+	MIB_DESC(1, 0x9c, "CRCAlignErrors"),
+	MIB_DESC(1, 0x98, "tx_UndersizePkts"),
+	MIB_DESC(1, 0x94, "rx_UndersizePkts"),
+	MIB_DESC(1, 0x90, "rx_UndersizedropPkts"),
+	MIB_DESC(1, 0x8c, "tx_OversizePkts"),
+	MIB_DESC(1, 0x88, "rx_OversizePkts"),
+	MIB_DESC(1, 0x84, "Fragments"),
+	MIB_DESC(1, 0x80, "Jabbers"),
+	MIB_DESC(1, 0x7c, "Collisions"),
+	MIB_DESC(1, 0x78, "tx_Pkts64Octets"),
+	MIB_DESC(1, 0x74, "rx_Pkts64Octets"),
+	MIB_DESC(1, 0x70, "tx_Pkts65to127Octets"),
+	MIB_DESC(1, 0x6c, "rx_Pkts65to127Octets"),
+	MIB_DESC(1, 0x68, "tx_Pkts128to255Octets"),
+	MIB_DESC(1, 0x64, "rx_Pkts128to255Octets"),
+	MIB_DESC(1, 0x60, "tx_Pkts256to511Octets"),
+	MIB_DESC(1, 0x5c, "rx_Pkts256to511Octets"),
+	MIB_DESC(1, 0x58, "tx_Pkts512to1023Octets"),
+	MIB_DESC(1, 0x54, "rx_Pkts512to1023Octets"),
+	MIB_DESC(1, 0x50, "tx_Pkts1024to1518Octets"),
+	MIB_DESC(1, 0x4c, "rx_StatsPkts1024to1518Octets"),
+	MIB_DESC(1, 0x48, "tx_Pkts1519toMaxOctets"),
+	MIB_DESC(1, 0x44, "rx_Pkts1519toMaxOctets"),
+	MIB_DESC(1, 0x40, "rxMacDiscards")
+};
+
+
+/* DSA callbacks */
+
+
+static enum dsa_tag_protocol rtl83xx_get_tag_protocol(struct dsa_switch *ds, int port)
+{
+	/* The switch does not tag the frames, instead internally the header
+	 * structure for each packet is tagged accordingly.
+	 */
+	return DSA_TAG_PROTO_TRAILER;
+}
+
+static int rtl83xx_setup(struct dsa_switch *ds)
+{
+	int i;
+	struct rtl838x_switch_priv *priv = ds->priv;
+	u64 port_bitmap = BIT_ULL(priv->cpu_port);
+
+	pr_debug("%s called\n", __func__);
+
+	/* Disable MAC polling the PHY so that we can start configuration */
+	priv->r->set_port_reg_le(0ULL, priv->r->smi_poll_ctrl);
+
+	for (i = 0; i < ds->num_ports; i++)
+		priv->ports[i].enable = false;
+	priv->ports[priv->cpu_port].enable = true;
+
+	/* Isolate ports from each other: traffic only CPU <-> port */
+	/* Setting bit j in register RTL838X_PORT_ISO_CTRL(i) allows
+	 * traffic from source port i to destination port j
+	 */
+	for (i = 0; i < priv->cpu_port; i++) {
+		if (priv->ports[i].phy) {
+			priv->r->set_port_reg_be(BIT_ULL(priv->cpu_port) | BIT(i),
+					      priv->r->port_iso_ctrl(i));
+			port_bitmap |= BIT_ULL(i);
+		}
+	}
+	priv->r->set_port_reg_be(port_bitmap, priv->r->port_iso_ctrl(priv->cpu_port));
+
+	rtl83xx_print_matrix();
+
+	rtl83xx_init_stats(priv);
+
+	ds->configure_vlan_while_not_filtering = true;
+
+	/* Enable MAC Polling PHY again */
+	rtl83xx_enable_phy_polling(priv);
+	pr_debug("Please wait until PHY is settled\n");
+	msleep(1000);
+	return 0;
+}
+
+static void rtl83xx_phylink_validate(struct dsa_switch *ds, int port,
+				     unsigned long *supported,
+				     struct phylink_link_state *state)
+{
+	struct rtl838x_switch_priv *priv = ds->priv;
+	__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
+
+	pr_debug("In %s port %d", __func__, port);
+
+	if (!phy_interface_mode_is_rgmii(state->interface) &&
+	    state->interface != PHY_INTERFACE_MODE_1000BASEX &&
+	    state->interface != PHY_INTERFACE_MODE_MII &&
+	    state->interface != PHY_INTERFACE_MODE_REVMII &&
+	    state->interface != PHY_INTERFACE_MODE_GMII &&
+	    state->interface != PHY_INTERFACE_MODE_QSGMII &&
+	    state->interface != PHY_INTERFACE_MODE_INTERNAL &&
+	    state->interface != PHY_INTERFACE_MODE_SGMII) {
+		bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
+		dev_err(ds->dev,
+			"Unsupported interface: %d for port %d\n",
+			state->interface, port);
+		return;
+	}
+
+	/* Allow all the expected bits */
+	phylink_set(mask, Autoneg);
+	phylink_set_port_modes(mask);
+	phylink_set(mask, Pause);
+	phylink_set(mask, Asym_Pause);
+
+	/* With the exclusion of MII and Reverse MII, we support Gigabit,
+	 * including Half duplex
+	 */
+	if (state->interface != PHY_INTERFACE_MODE_MII &&
+	    state->interface != PHY_INTERFACE_MODE_REVMII) {
+		phylink_set(mask, 1000baseT_Full);
+		phylink_set(mask, 1000baseT_Half);
+	}
+
+	/* On both the 8380 and 8382, ports 24-27 are SFP ports */
+	if (port >= 24 && port <= 27 && priv->family_id == RTL8380_FAMILY_ID)
+		phylink_set(mask, 1000baseX_Full);
+
+	phylink_set(mask, 10baseT_Half);
+	phylink_set(mask, 10baseT_Full);
+	phylink_set(mask, 100baseT_Half);
+	phylink_set(mask, 100baseT_Full);
+
+	bitmap_and(supported, supported, mask,
+		   __ETHTOOL_LINK_MODE_MASK_NBITS);
+	bitmap_and(state->advertising, state->advertising, mask,
+		   __ETHTOOL_LINK_MODE_MASK_NBITS);
+}
+
+static int rtl83xx_phylink_mac_link_state(struct dsa_switch *ds, int port,
+					  struct phylink_link_state *state)
+{
+	struct rtl838x_switch_priv *priv = ds->priv;
+	u64 speed;
+
+	if (port < 0 || port > priv->cpu_port)
+		return -EINVAL;
+
+	state->link = 0;
+	if (priv->r->get_port_reg_le(priv->r->mac_link_sts) & BIT_ULL(port))
+		state->link = 1;
+	state->duplex = 0;
+	if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))
+		state->duplex = 1;
+
+	speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));
+	speed >>= (port % 16) << 1;
+	switch (speed & 0x3) {
+	case 0:
+		state->speed = SPEED_10;
+		break;
+	case 1:
+		state->speed = SPEED_100;
+		break;
+	case 2:
+		state->speed = SPEED_1000;
+		break;
+	case 3:
+		if (port == 24 || port == 26) /* Internal serdes */
+			state->speed = SPEED_2500;
+		else
+			state->speed = SPEED_100; /* Is in fact 500Mbit */
+	}
+
+	state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
+	if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))
+		state->pause |= MLO_PAUSE_RX;
+	if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))
+		state->pause |= MLO_PAUSE_TX;
+	return 1;
+}
+
+static void rtl83xx_phylink_mac_config(struct dsa_switch *ds, int port,
+					unsigned int mode,
+					const struct phylink_link_state *state)
+{
+	struct rtl838x_switch_priv *priv = ds->priv;
+	u32 reg;
+	int speed_bit = priv->family_id == RTL8380_FAMILY_ID ? 4 : 3;
+
+	pr_debug("%s port %d, mode %x\n", __func__, port, mode);
+
+	if (port == priv->cpu_port) {
+		/* Set Speed, duplex, flow control
+		 * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL
+		 * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN
+		 * | MEDIA_SEL
+		 */
+		if (priv->family_id == RTL8380_FAMILY_ID) {
+			sw_w32(0x6192F, priv->r->mac_force_mode_ctrl(priv->cpu_port));
+			/* allow CRC errors on CPU-port */
+			sw_w32_mask(0, 0x8, RTL838X_MAC_PORT_CTRL(priv->cpu_port));
+		} else {
+			sw_w32_mask(0, 3, priv->r->mac_force_mode_ctrl(priv->cpu_port));
+		}
+		return;
+	}
+
+	reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
+	/* Auto-Negotiation does not work for MAC in RTL8390 */
+	if (priv->family_id == RTL8380_FAMILY_ID) {
+		if (mode == MLO_AN_PHY) {
+			pr_debug("PHY autonegotiates\n");
+			reg |= BIT(2);
+			sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
+			return;
+		}
+	}
+
+	if (mode != MLO_AN_FIXED)
+		pr_debug("Fixed state.\n");
+
+	if (priv->family_id == RTL8380_FAMILY_ID) {
+		/* Clear id_mode_dis bit, and the existing port mode, let
+		 * RGMII_MODE_EN bet set by mac_link_{up,down}
+		 */
+		reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
+
+		if (state->pause & MLO_PAUSE_TXRX_MASK) {
+			if (state->pause & MLO_PAUSE_TX)
+				reg |= TX_PAUSE_EN;
+			reg |= RX_PAUSE_EN;
+		}
+	}
+
+	reg &= ~(3 << speed_bit);
+	switch (state->speed) {
+	case SPEED_1000:
+		reg |= 2 << speed_bit;
+		break;
+	case SPEED_100:
+		reg |= 1 << speed_bit;
+		break;
+	}
+
+	if (priv->family_id == RTL8380_FAMILY_ID) {
+		reg &= ~(DUPLEX_FULL | FORCE_LINK_EN);
+		if (state->link)
+			reg |= FORCE_LINK_EN;
+		if (state->duplex == DUPLEX_FULL)
+			reg |= DUPLX_MODE;
+	}
+
+	// Disable AN
+	if (priv->family_id == RTL8380_FAMILY_ID)
+		reg &= ~BIT(2);
+	sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
+}
+
+static void rtl83xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
+				     unsigned int mode,
+				     phy_interface_t interface)
+{
+	struct rtl838x_switch_priv *priv = ds->priv;
+	/* Stop TX/RX to port */
+	sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));
+}
+
+static void rtl83xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
+				   unsigned int mode,
+				   phy_interface_t interface,
+				   struct phy_device *phydev)
+{
+	struct rtl838x_switch_priv *priv = ds->priv;
+	/* Restart TX/RX to port */
+	sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));
+}
+
+static void rtl83xx_get_strings(struct dsa_switch *ds,
+				int port, u32 stringset, u8 *data)
+{
+	int i;
+
+	if (stringset != ETH_SS_STATS)
+		return;
+
+	for (i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++)
+		strncpy(data + i * ETH_GSTRING_LEN, rtl83xx_mib[i].name,
+			ETH_GSTRING_LEN);
+}
+
+static void rtl83xx_get_ethtool_stats(struct dsa_switch *ds, int port,
+				      uint64_t *data)
+{
+	struct rtl838x_switch_priv *priv = ds->priv;
+	const struct rtl83xx_mib_desc *mib;
+	int i;
+	u64 high;
+
+	for (i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++) {
+		mib = &rtl83xx_mib[i];
+
+		data[i] = sw_r32(priv->r->stat_port_std_mib(port) + 252 - mib->offset);
+		if (mib->size == 2) {
+			high = sw_r32(priv->r->stat_port_std_mib(port) + 252 - mib->offset - 4);
+			data[i] |= high << 32;
+		}
+	}
+}
+
+static int rtl83xx_get_sset_count(struct dsa_switch *ds, int port, int sset)
+{
+	if (sset != ETH_SS_STATS)
+		return 0;
+
+	return ARRAY_SIZE(rtl83xx_mib);
+}
+
+static int rtl83xx_port_enable(struct dsa_switch *ds, int port,
+				struct phy_device *phydev)
+{
+	struct rtl838x_switch_priv *priv = ds->priv;
+
+	pr_debug("%s: %x %d", __func__, (u32) priv, port);
+	priv->ports[port].enable = true;
+
+	/* enable inner tagging on egress, do not keep any tags */
+	sw_w32(1, priv->r->vlan_port_tag_sts_ctrl(port));
+
+	if (dsa_is_cpu_port(ds, port))
+		return 0;
+
+	/* add port to switch mask of CPU_PORT */
+	priv->r->mask_port_reg_be(0ULL, BIT_ULL(port), priv->r->port_iso_ctrl(priv->cpu_port));
+
+	/* add all other ports in the same bridge to switch mask of port */
+	priv->r->mask_port_reg_be(0ULL, priv->ports[port].pm, priv->r->port_iso_ctrl(port));
+
+	return 0;
+}
+
+static void rtl83xx_port_disable(struct dsa_switch *ds, int port)
+{
+	struct rtl838x_switch_priv *priv = ds->priv;
+
+	pr_debug("%s %x: %d", __func__, (u32)priv, port);
+	/* you can only disable user ports */
+	if (!dsa_is_user_port(ds, port))
+		return;
+
+	/* remove port from switch mask of CPU_PORT */
+	priv->r->mask_port_reg_be(BIT_ULL(port), 0, priv->r->port_iso_ctrl(priv->cpu_port));
+
+	/* remove all other ports in the same bridge from switch mask of port */
+	priv->r->mask_port_reg_be(priv->ports[port].pm, 0LL, priv->r->port_iso_ctrl(port));
+
+	priv->ports[port].enable = false;
+}
+
+static int rtl83xx_get_mac_eee(struct dsa_switch *ds, int port,
+			       struct ethtool_eee *e)
+{
+	struct rtl838x_switch_priv *priv = ds->priv;
+
+	pr_debug("%s: port %d", __func__, port);
+	e->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full;
+	if (sw_r32(priv->r->mac_force_mode_ctrl(port)) & BIT(9))
+		e->advertised |= ADVERTISED_100baseT_Full;
+
+	if (sw_r32(priv->r->mac_force_mode_ctrl(port)) & BIT(10))
+		e->advertised |= ADVERTISED_1000baseT_Full;
+
+	e->eee_enabled = priv->ports[port].eee_enabled;
+	pr_debug("enabled: %d, active %x\n", e->eee_enabled, e->advertised);
+
+	if (sw_r32(RTL838X_MAC_EEE_ABLTY) & BIT(port)) {
+		e->lp_advertised = ADVERTISED_100baseT_Full;
+		e->lp_advertised |= ADVERTISED_1000baseT_Full;
+	}
+
+	e->eee_active = !!(e->advertised & e->lp_advertised);
+	pr_debug("active: %d, lp %x\n", e->eee_active, e->lp_advertised);
+
+	return 0;
+}
+
+static int rtl83xx_set_mac_eee(struct dsa_switch *ds, int port,
+			       struct ethtool_eee *e)
+{
+	struct rtl838x_switch_priv *priv = ds->priv;
+
+	pr_debug("%s: port %d", __func__, port);
+	if (e->eee_enabled) {
+		pr_debug("Globally enabling EEE\n");
+		sw_w32_mask(0x4, 0, RTL838X_SMI_GLB_CTRL);
+	}
+	if (e->eee_enabled) {
+		pr_debug("Enabling EEE for MAC %d\n", port);
+		sw_w32_mask(0, 3 << 9, priv->r->mac_force_mode_ctrl(port));
+		sw_w32_mask(0, BIT(port), RTL838X_EEE_PORT_TX_EN);
+		sw_w32_mask(0, BIT(port), RTL838X_EEE_PORT_RX_EN);
+		priv->ports[port].eee_enabled = true;
+		e->eee_enabled = true;
+	} else {
+		pr_debug("Disabling EEE for MAC %d\n", port);
+		sw_w32_mask(3 << 9, 0, priv->r->mac_force_mode_ctrl(port));
+		sw_w32_mask(BIT(port), 0, RTL838X_EEE_PORT_TX_EN);
+		sw_w32_mask(BIT(port), 0, RTL838X_EEE_PORT_RX_EN);
+		priv->ports[port].eee_enabled = false;
+		e->eee_enabled = false;
+	}
+	return 0;
+}
+
+/*
+ * Set Switch L2 Aging time, t is time in milliseconds
+ * t = 0: aging is disabled
+ */
+static int rtl83xx_set_l2aging(struct dsa_switch *ds, u32 t)
+{
+	struct rtl838x_switch_priv *priv = ds->priv;
+	int t_max = priv->family_id == RTL8380_FAMILY_ID ? 0x7fffff : 0x1FFFFF;
+
+	/* Convert time in mseconds to internal value */
+	if (t > 0x10000000) { /* Set to maximum */
+		t = t_max;
+	} else {
+		if (priv->family_id == RTL8380_FAMILY_ID)
+			t = ((t * 625) / 1000 + 127) / 128;
+		else
+			t = (t * 5 + 2) / 3;
+	}
+	sw_w32(t, priv->r->l2_ctrl_1);
+	return 0;
+}
+
+static int rtl83xx_port_bridge_join(struct dsa_switch *ds, int port,
+					struct net_device *bridge)
+{
+	struct rtl838x_switch_priv *priv = ds->priv;
+	u64 port_bitmap = BIT_ULL(priv->cpu_port);
+	int i;
+
+	pr_debug("%s %x: %d %llx", __func__, (u32)priv, port, port_bitmap);
+	mutex_lock(&priv->reg_mutex);
+	for (i = 0; i < ds->num_ports; i++) {
+		/* Add this port to the port matrix of the other ports in the
+		 * same bridge. If the port is disabled, port matrix is kept
+		 * and not being setup until the port becomes enabled.
+		 */
+		if (dsa_is_user_port(ds, i) && i != port) {
+			if (dsa_to_port(ds, i)->bridge_dev != bridge)
+				continue;
+			if (priv->ports[i].enable)
+				priv->r->mask_port_reg_be(0, BIT_ULL(port),
+						       priv->r->port_iso_ctrl(i));
+			priv->ports[i].pm |= BIT_ULL(port);
+
+			port_bitmap |= BIT_ULL(i);
+		}
+	}
+
+	/* Add all other ports to this port matrix. */
+	if (priv->ports[port].enable) {
+		priv->r->mask_port_reg_be(0, BIT_ULL(port),
+					priv->r->port_iso_ctrl(priv->cpu_port));
+		priv->r->mask_port_reg_be(0, port_bitmap,
+					priv->r->port_iso_ctrl(port));
+	}
+	priv->ports[port].pm |= port_bitmap;
+	mutex_unlock(&priv->reg_mutex);
+
+	return 0;
+}
+
+static void rtl83xx_port_bridge_leave(struct dsa_switch *ds, int port,
+					struct net_device *bridge)
+{
+	struct rtl838x_switch_priv *priv = ds->priv;
+	u64 port_bitmap = BIT_ULL(priv->cpu_port);
+	int i;
+
+	pr_debug("%s %x: %d", __func__, (u32)priv, port);
+	mutex_lock(&priv->reg_mutex);
+	for (i = 0; i < ds->num_ports; i++) {
+		/* Remove this port from the port matrix of the other ports
+		 * in the same bridge. If the port is disabled, port matrix
+		 * is kept and not being setup until the port becomes enabled.
+		 * And the other port's port matrix cannot be broken when the
+		 * other port is still a VLAN-aware port.
+		 */
+		if (dsa_is_user_port(ds, i) && i != port) {
+			if (dsa_to_port(ds, i)->bridge_dev != bridge)
+				continue;
+			if (priv->ports[i].enable)
+				priv->r->mask_port_reg_be(BIT_ULL(port), 0,
+						       priv->r->port_iso_ctrl(i));
+			priv->ports[i].pm &= ~BIT_ULL(port);
+
+			port_bitmap &= ~BIT_ULL(i);
+		}
+	}
+
+	/* Add all other ports to this port matrix. */
+	if (priv->ports[port].enable)
+		priv->r->mask_port_reg_be(0, port_bitmap, priv->r->port_iso_ctrl(port));
+	priv->ports[port].pm &= ~port_bitmap;
+
+	mutex_unlock(&priv->reg_mutex);
+}
+
+static void rtl83xx_port_stp_state_set(struct dsa_switch *ds, int port,
+				       u8 state)
+{
+	u32 cmd, msti = 0;
+	u32 port_state[4];
+	int index, bit, i;
+	int pos = port;
+	struct rtl838x_switch_priv *priv = ds->priv;
+	int n = priv->family_id == RTL8380_FAMILY_ID ? 2 : 4;
+
+	pr_debug("%s: port %d state %2x\n", __func__, port, state);
+
+	/* CPU PORT can only be configured on RTL838x */
+	if (port >= priv->cpu_port || port > 51)
+		return;
+
+	mutex_lock(&priv->reg_mutex);
+
+	/* For the RTL839x, the bits are left-aligned in the 128 bit field */
+	if (priv->family_id == RTL8390_FAMILY_ID)
+		pos += 12;
+
+	index = n - (pos >> 4) - 1;
+	bit = (pos << 1) % 32;
+
+	if (priv->family_id == RTL8380_FAMILY_ID) {
+		cmd = BIT(15) /* Execute cmd */
+			| BIT(14) /* Read */
+			| 2 << 12 /* Table type 0b10 */
+			| (msti & 0xfff);
+	} else {
+		cmd = BIT(16) /* Execute cmd */
+			| 0 << 15 /* Read */
+			| 5 << 12 /* Table type 0b101 */
+			| (msti & 0xfff);
+	}
+	priv->r->exec_tbl0_cmd(cmd);
+
+	for (i = 0; i < n; i++)
+		port_state[i] = sw_r32(priv->r->tbl_access_data_0(i));
+
+	pr_debug("Current state, port %d: %d\n", port, (port_state[index] >> bit) & 3);
+	port_state[index] &= ~(3 << bit);
+
+	switch (state) {
+	case BR_STATE_DISABLED: /* 0 */
+		port_state[index] |= (0 << bit);
+		break;
+	case BR_STATE_BLOCKING:  /* 4 */
+	case BR_STATE_LISTENING: /* 1 */
+		port_state[index] |= (1 << bit);
+		break;
+	case BR_STATE_LEARNING: /* 2 */
+		port_state[index] |= (2 << bit);
+		break;
+	case BR_STATE_FORWARDING: /* 3*/
+		port_state[index] |= (3 << bit);
+	default:
+		break;
+	}
+
+	if (priv->family_id == RTL8380_FAMILY_ID) {
+		cmd = BIT(15) /* Execute cmd */
+			| 0 << 14 /* Write */
+			| 2 << 12 /* Table type 0b10 */
+			| (msti & 0xfff);
+	} else {
+		cmd = 1 << 16 /* Execute cmd */
+			| BIT(15) /* Write */
+			| 5 << 12 /* Table type 0b101 */
+			| (msti & 0xfff);
+	}
+	for (i = 0; i < n; i++)
+		sw_w32(port_state[i], priv->r->tbl_access_data_0(i));
+	priv->r->exec_tbl0_cmd(cmd);
+
+	mutex_unlock(&priv->reg_mutex);
+}
+
+static void rtl83xx_fast_age(struct dsa_switch *ds, int port)
+{
+	struct rtl838x_switch_priv *priv = ds->priv;
+	int s = priv->family_id == RTL8390_FAMILY_ID ? 2 : 0;
+
+	pr_debug("FAST AGE port %d\n", port);
+	mutex_lock(&priv->reg_mutex);
+	/* RTL838X_L2_TBL_FLUSH_CTRL register bits, 839x has 1 bit larger
+	 * port fields:
+	 * 0-4: Replacing port
+	 * 5-9: Flushed/replaced port
+	 * 10-21: FVID
+	 * 22: Entry types: 1: dynamic, 0: also static
+	 * 23: Match flush port
+	 * 24: Match FVID
+	 * 25: Flush (0) or replace (1) L2 entries
+	 * 26: Status of action (1: Start, 0: Done)
+	 */
+	sw_w32(1 << (26 + s) | 1 << (23 + s) | port << (5 + (s / 2)), priv->r->l2_tbl_flush_ctrl);
+
+	do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & (1 << (26 + s)));
+
+	mutex_unlock(&priv->reg_mutex);
+}
+
+static int rtl83xx_vlan_filtering(struct dsa_switch *ds, int port,
+				  bool vlan_filtering)
+{
+	struct rtl838x_switch_priv *priv = ds->priv;
+
+	pr_debug("%s: port %d\n", __func__, port);
+	mutex_lock(&priv->reg_mutex);
+
+	if (vlan_filtering) {
+		/* Enable ingress and egress filtering */
+		if (port != priv->cpu_port)
+			sw_w32_mask(0b10 << ((port % 16) << 1), 0b01 << ((port % 16) << 1),
+				    priv->r->vlan_port_igr_filter(port));
+		sw_w32_mask(0, 1 << (port % 32), priv->r->vlan_port_egr_filter(port));
+	} else {
+		/* Disable ingress and egress filtering */
+		if (port != priv->cpu_port)
+			sw_w32_mask(0b11 << ((port % 16) << 1), 0,
+				    priv->r->vlan_port_igr_filter(port));
+		sw_w32_mask(1 << (port % 32), 0, priv->r->vlan_port_egr_filter(port));
+	}
+
+	/* Do we need to do something to the CPU-Port, too? */
+	mutex_unlock(&priv->reg_mutex);
+
+	return 0;
+}
+
+static int rtl83xx_vlan_prepare(struct dsa_switch *ds, int port,
+				const struct switchdev_obj_port_vlan *vlan)
+{
+	struct rtl838x_vlan_info info;
+	struct rtl838x_switch_priv *priv = ds->priv;
+
+	pr_debug("%s: port %d\n", __func__, port);
+
+	mutex_lock(&priv->reg_mutex);
+
+	if (priv->family_id == RTL8380_FAMILY_ID)
+		rtl838x_vlan_profile_dump(0);
+	else
+		rtl839x_vlan_profile_dump(0);
+
+	priv->r->vlan_tables_read(0, &info);
+
+	pr_debug("Tagged ports %llx, untag %llx, prof %x, MC# %d, UC# %d, FID %x\n",
+		info.tagged_ports, info.untagged_ports, info.profile_id,
+		info.hash_mc_fid, info.hash_uc_fid, info.fid);
+
+	mutex_unlock(&priv->reg_mutex);
+	return 0;
+}
+
+static void rtl83xx_vlan_add(struct dsa_switch *ds, int port,
+			    const struct switchdev_obj_port_vlan *vlan)
+{
+	struct rtl838x_vlan_info info = {};
+	struct rtl838x_switch_priv *priv = ds->priv;
+	int v;
+
+	pr_debug("%s port %d, vid_end %d, vid_end %d, flags %x\n", __func__,
+		port, vlan->vid_begin, vlan->vid_end, vlan->flags);
+
+	if (vlan->vid_begin > 4095 || vlan->vid_end > 4095) {
+		dev_err(priv->dev, "VLAN out of range: %d - %d",
+			vlan->vid_begin, vlan->vid_end);
+		return;
+	}
+
+	mutex_lock(&priv->reg_mutex);
+
+	if (vlan->flags & BRIDGE_VLAN_INFO_PVID) {
+		/* Set both inner and outer PVID of the port */
+		sw_w32((vlan->vid_end << 16) | vlan->vid_end << 2, priv->r->vlan_port_pb(port));
+		priv->ports[port].pvid = vlan->vid_end;
+	}
+
+	for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
+		/* Get port memberships of this vlan */
+		priv->r->vlan_tables_read(v, &info);
+
+		/* new VLAN? */
+		if (!info.tagged_ports) {
+			info.fid = 0;
+			info.hash_mc_fid = false;
+			info.hash_uc_fid = false;
+			info.profile_id = 0;
+		}
+
+		/* sanitize untagged_ports - must be a subset */
+		if (info.untagged_ports & ~info.tagged_ports)
+			info.untagged_ports = 0;
+
+		info.tagged_ports |= BIT_ULL(port);
+		if (vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED)
+			info.untagged_ports |= BIT_ULL(port);
+
+		priv->r->vlan_set_untagged(v, info.untagged_ports);
+		pr_debug("Untagged ports, VLAN %d: %llx\n", v, info.untagged_ports);
+
+		priv->r->vlan_set_tagged(v, &info);
+		pr_debug("Tagged ports, VLAN %d: %llx\n", v, info.tagged_ports);
+	}
+
+	mutex_unlock(&priv->reg_mutex);
+}
+
+static int rtl83xx_vlan_del(struct dsa_switch *ds, int port,
+			    const struct switchdev_obj_port_vlan *vlan)
+{
+	struct rtl838x_vlan_info info;
+	struct rtl838x_switch_priv *priv = ds->priv;
+	int v;
+	u16 pvid;
+
+	pr_debug("%s: port %d, vid_end %d, vid_end %d, flags %x\n", __func__,
+		port, vlan->vid_begin, vlan->vid_end, vlan->flags);
+
+	if (vlan->vid_begin > 4095 || vlan->vid_end > 4095) {
+		dev_err(priv->dev, "VLAN out of range: %d - %d",
+			vlan->vid_begin, vlan->vid_end);
+		return -ENOTSUPP;
+	}
+
+	mutex_lock(&priv->reg_mutex);
+	pvid = priv->ports[port].pvid;
+
+	for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
+		/* Reset to default if removing the current PVID */
+		if (v == pvid)
+			sw_w32(0, priv->r->vlan_port_pb(port));
+
+		/* Get port memberships of this vlan */
+		priv->r->vlan_tables_read(v, &info);
+
+		/* remove port from both tables */
+		info.untagged_ports &= (~BIT_ULL(port));
+		/* always leave vid 1 */
+		if (v != 1)
+			info.tagged_ports &= (~BIT_ULL(port));
+
+		priv->r->vlan_set_untagged(v, info.untagged_ports);
+		pr_debug("Untagged ports, VLAN %d: %llx\n", v, info.untagged_ports);
+
+		priv->r->vlan_set_tagged(v, &info);
+		pr_debug("Tagged ports, VLAN %d: %llx\n", v, info.tagged_ports);
+	}
+	mutex_unlock(&priv->reg_mutex);
+
+	return 0;
+}
+
+static int rtl83xx_port_fdb_add(struct dsa_switch *ds, int port,
+				const unsigned char *addr, u16 vid)
+{
+	struct rtl838x_switch_priv *priv = ds->priv;
+	u64 mac = ether_addr_to_u64(addr);
+	u32 key = rtl83xx_hash_key(priv, mac, vid);
+	struct rtl838x_l2_entry e;
+	u32 r[3];
+	u64 entry;
+	int idx = -1, err = 0, i;
+
+	mutex_lock(&priv->reg_mutex);
+	for (i = 0; i < 4; i++) {
+		entry = priv->r->read_l2_entry_using_hash(key, i, &e);
+		if (!e.valid) {
+			idx = (key << 2) | i;
+			break;
+		}
+		if ((entry & 0x0fffffffffffffffULL) == ((mac << 12) | vid)) {
+			idx = (key << 2) | i;
+			break;
+		}
+	}
+	if (idx >= 0) {
+		r[0] = 3 << 17 | port << 12; // Aging and  port
+		r[0] |= vid;
+		r[1] = mac >> 16;
+		r[2] = (mac & 0xffff) << 12; /* rvid = 0 */
+		rtl83xx_write_hash(idx, r);
+		goto out;
+	}
+
+	/* Hash buckets full, try CAM */
+	for (i = 0; i < 64; i++) {
+		entry = priv->r->read_cam(i, &e);
+		if (!e.valid) {
+			if (idx < 0) /* First empty entry? */
+				idx = i;
+			break;
+		} else if ((entry & 0x0fffffffffffffffULL) == ((mac << 12) | vid)) {
+			pr_debug("Found entry in CAM\n");
+			idx = i;
+			break;
+		}
+	}
+	if (idx >= 0) {
+		r[0] = 3 << 17 | port << 12; // Aging
+		r[0] |= vid;
+		r[1] = mac >> 16;
+		r[2] = (mac & 0xffff) << 12; /* rvid = 0 */
+		rtl83xx_write_cam(idx, r);
+		goto out;
+	}
+	err = -ENOTSUPP;
+out:
+	mutex_unlock(&priv->reg_mutex);
+	return err;
+}
+
+static int rtl83xx_port_fdb_del(struct dsa_switch *ds, int port,
+			   const unsigned char *addr, u16 vid)
+{
+	struct rtl838x_switch_priv *priv = ds->priv;
+	u64 mac = ether_addr_to_u64(addr);
+	u32 key = rtl83xx_hash_key(priv, mac, vid);
+	struct rtl838x_l2_entry e;
+	u32 r[3];
+	u64 entry;
+	int idx = -1, err = 0, i;
+
+	pr_debug("In %s, mac %llx, vid: %d, key: %x\n", __func__, mac, vid, key);
+	mutex_lock(&priv->reg_mutex);
+	for (i = 0; i < 4; i++) {
+		entry = priv->r->read_l2_entry_using_hash(key, i, &e);
+		if (!e.valid)
+			continue;
+		if ((entry & 0x0fffffffffffffffULL) == ((mac << 12) | vid)) {
+			idx = (key << 2) | i;
+			break;
+		}
+	}
+
+	if (idx >= 0) {
+		r[0] = r[1] = r[2] = 0;
+		rtl83xx_write_hash(idx, r);
+		goto out;
+	}
+
+	/* Check CAM for spillover from hash buckets */
+	for (i = 0; i < 64; i++) {
+		entry = priv->r->read_cam(i, &e);
+		if ((entry & 0x0fffffffffffffffULL) == ((mac << 12) | vid)) {
+			idx = i;
+			break;
+		}
+	}
+	if (idx >= 0) {
+		r[0] = r[1] = r[2] = 0;
+		rtl83xx_write_cam(idx, r);
+		goto out;
+	}
+	err = -ENOENT;
+out:
+	mutex_unlock(&priv->reg_mutex);
+	return err;
+}
+
+static int rtl83xx_port_fdb_dump(struct dsa_switch *ds, int port,
+				 dsa_fdb_dump_cb_t *cb, void *data)
+{
+	struct rtl838x_l2_entry e;
+	struct rtl838x_switch_priv *priv = ds->priv;
+	int i;
+	u32 fid;
+	u32 pkey;
+	u64 mac;
+
+	mutex_lock(&priv->reg_mutex);
+
+	for (i = 0; i < priv->fib_entries; i++) {
+		priv->r->read_l2_entry_using_hash(i >> 2, i & 0x3, &e);
+
+		if (!e.valid)
+			continue;
+
+		if (e.port == port) {
+			fid = (i & 0x3ff) | (e.rvid & ~0x3ff);
+			mac = ether_addr_to_u64(&e.mac[0]);
+			pkey = rtl838x_hash(priv, mac << 12 | fid);
+			fid = (pkey & 0x3ff) | (fid & ~0x3ff);
+			pr_debug("-> mac %016llx, fid: %d\n", mac, fid);
+			cb(e.mac, e.vid, e.is_static, data);
+		}
+	}
+
+	for (i = 0; i < 64; i++) {
+		priv->r->read_cam(i, &e);
+
+		if (!e.valid)
+			continue;
+
+		if (e.port == port)
+			cb(e.mac, e.vid, e.is_static, data);
+	}
+
+	mutex_unlock(&priv->reg_mutex);
+	return 0;
+}
+
+static int rtl83xx_port_mirror_add(struct dsa_switch *ds, int port,
+				   struct dsa_mall_mirror_tc_entry *mirror,
+				   bool ingress)
+{
+	/* We support 4 mirror groups, one destination port per group */
+	int group;
+	struct rtl838x_switch_priv *priv = ds->priv;
+
+	pr_debug("In %s\n", __func__);
+
+	for (group = 0; group < 4; group++) {
+		if (priv->mirror_group_ports[group] == mirror->to_local_port)
+			break;
+	}
+	if (group >= 4) {
+		for (group = 0; group < 4; group++) {
+			if (priv->mirror_group_ports[group] < 0)
+				break;
+		}
+	}
+
+	if (group >= 4)
+		return -ENOSPC;
+
+	pr_debug("Using group %d\n", group);
+	mutex_lock(&priv->reg_mutex);
+
+	if (priv->family_id == RTL8380_FAMILY_ID) {
+		/* Enable mirroring to port across VLANs (bit 11) */
+		sw_w32(1 << 11 | (mirror->to_local_port << 4) | 1, RTL838X_MIR_CTRL(group));
+	} else {
+		/* Enable mirroring to destination port */
+		sw_w32((mirror->to_local_port << 4) | 1, RTL839X_MIR_CTRL(group));
+	}
+
+	if (ingress && (priv->r->get_port_reg_be(priv->r->mir_spm(group)) & (1ULL << port))) {
+		mutex_unlock(&priv->reg_mutex);
+		return -EEXIST;
+	}
+	if ((!ingress) && (priv->r->get_port_reg_be(priv->r->mir_dpm(group)) & (1ULL << port))) {
+		mutex_unlock(&priv->reg_mutex);
+		return -EEXIST;
+	}
+
+	if (ingress)
+		priv->r->mask_port_reg_be(0, 1ULL << port, priv->r->mir_spm(group));
+	else
+		priv->r->mask_port_reg_be(0, 1ULL << port, priv->r->mir_dpm(group));
+
+	priv->mirror_group_ports[group] = mirror->to_local_port;
+	mutex_unlock(&priv->reg_mutex);
+	return 0;
+}
+
+static void rtl83xx_port_mirror_del(struct dsa_switch *ds, int port,
+				    struct dsa_mall_mirror_tc_entry *mirror)
+{
+	int group = 0;
+	struct rtl838x_switch_priv *priv = ds->priv;
+
+	pr_debug("In %s\n", __func__);
+	for (group = 0; group < 4; group++) {
+		if (priv->mirror_group_ports[group] == mirror->to_local_port)
+			break;
+	}
+	if (group >= 4)
+		return;
+
+	mutex_lock(&priv->reg_mutex);
+	if (mirror->ingress) {
+		/* Ingress, clear source port matrix */
+		priv->r->mask_port_reg_be(1ULL << port, 0, priv->r->mir_spm(group));
+	} else {
+		/* Egress, clear destination port matrix */
+		priv->r->mask_port_reg_be(1ULL << port, 0, priv->r->mir_dpm(group));
+	}
+
+	if (!(sw_r32(priv->r->mir_spm(group)) || sw_r32(priv->r->mir_dpm(group)))) {
+		priv->mirror_group_ports[group] = -1;
+		sw_w32(0, priv->r->mir_ctrl(group));
+	}
+
+	mutex_unlock(&priv->reg_mutex);
+}
+
+const struct dsa_switch_ops rtl83xx_switch_ops = {
+	.get_tag_protocol	= rtl83xx_get_tag_protocol,
+	.setup			= rtl83xx_setup,
+
+	.phy_read		= rtl83xx_dsa_phy_read,
+	.phy_write		= rtl83xx_dsa_phy_write,
+
+	.phylink_validate	= rtl83xx_phylink_validate,
+	.phylink_mac_link_state	= rtl83xx_phylink_mac_link_state,
+	.phylink_mac_config	= rtl83xx_phylink_mac_config,
+	.phylink_mac_link_down	= rtl83xx_phylink_mac_link_down,
+	.phylink_mac_link_up	= rtl83xx_phylink_mac_link_up,
+
+	.get_strings		= rtl83xx_get_strings,
+	.get_ethtool_stats	= rtl83xx_get_ethtool_stats,
+	.get_sset_count		= rtl83xx_get_sset_count,
+
+	.port_enable		= rtl83xx_port_enable,
+	.port_disable		= rtl83xx_port_disable,
+
+	.get_mac_eee		= rtl83xx_get_mac_eee,
+	.set_mac_eee		= rtl83xx_set_mac_eee,
+
+	.set_ageing_time	= rtl83xx_set_l2aging,
+	.port_bridge_join	= rtl83xx_port_bridge_join,
+	.port_bridge_leave	= rtl83xx_port_bridge_leave,
+	.port_stp_state_set	= rtl83xx_port_stp_state_set,
+	.port_fast_age		= rtl83xx_fast_age,
+
+	.port_vlan_filtering	= rtl83xx_vlan_filtering,
+	.port_vlan_prepare	= rtl83xx_vlan_prepare,
+	.port_vlan_add		= rtl83xx_vlan_add,
+	.port_vlan_del		= rtl83xx_vlan_del,
+
+	.port_fdb_add		= rtl83xx_port_fdb_add,
+	.port_fdb_del		= rtl83xx_port_fdb_del,
+	.port_fdb_dump		= rtl83xx_port_fdb_dump,
+
+	.port_mirror_add	= rtl83xx_port_mirror_add,
+	.port_mirror_del	= rtl83xx_port_mirror_del,
+};
+
diff --git a/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl838x.c b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl838x.c
new file mode 100644
index 0000000000..c7b5873e99
--- /dev/null
+++ b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl838x.c
@@ -0,0 +1,476 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <asm/mach-rtl838x/mach-rtl83xx.h>
+#include "rtl83xx.h"
+
+extern struct mutex smi_lock;
+
+
+static inline void rtl838x_mask_port_reg(u64 clear, u64 set, int reg)
+{
+	sw_w32_mask((u32)clear, (u32)set, reg);
+}
+
+static inline void rtl838x_set_port_reg(u64 set, int reg)
+{
+	sw_w32(set, reg);
+}
+
+static inline u64 rtl838x_get_port_reg(int reg)
+{
+	return ((u64) sw_r32(reg));
+}
+
+static inline int rtl838x_stat_port_std_mib(int p)
+{
+	return RTL838X_STAT_PORT_STD_MIB + (p << 8);
+}
+
+static inline int rtl838x_port_iso_ctrl(int p)
+{
+	return RTL838X_PORT_ISO_CTRL(p);
+}
+
+static inline void rtl838x_exec_tbl0_cmd(u32 cmd)
+{
+	sw_w32(cmd, RTL838X_TBL_ACCESS_CTRL_0);
+	do { } while (sw_r32(RTL838X_TBL_ACCESS_CTRL_0) & BIT(15));
+}
+
+static inline void rtl838x_exec_tbl1_cmd(u32 cmd)
+{
+	sw_w32(cmd, RTL838X_TBL_ACCESS_CTRL_1);
+	do { } while (sw_r32(RTL838X_TBL_ACCESS_CTRL_1) & BIT(15));
+}
+
+static inline int rtl838x_tbl_access_data_0(int i)
+{
+	return RTL838X_TBL_ACCESS_DATA_0(i);
+}
+
+static void rtl838x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info)
+{
+	u32 cmd, v;
+
+	cmd = BIT(15) /* Execute cmd */
+		| BIT(14) /* Read */
+		| 0 << 12 /* Table type 0b00 */
+		| (vlan & 0xfff);
+	rtl838x_exec_tbl0_cmd(cmd);
+	info->tagged_ports = sw_r32(RTL838X_TBL_ACCESS_DATA_0(0));
+	v = sw_r32(RTL838X_TBL_ACCESS_DATA_0(1));
+	info->profile_id = v & 0x7;
+	info->hash_mc_fid = !!(v & 0x8);
+	info->hash_uc_fid = !!(v & 0x10);
+	info->fid = (v >> 5) & 0x3f;
+
+
+	cmd = BIT(15) /* Execute cmd */
+		| BIT(14) /* Read */
+		| 0 << 12 /* Table type 0b00 */
+		| (vlan & 0xfff);
+	rtl838x_exec_tbl1_cmd(cmd);
+	info->untagged_ports = sw_r32(RTL838X_TBL_ACCESS_DATA_1(0));
+}
+
+static void rtl838x_vlan_set_tagged(u32 vlan, struct rtl838x_vlan_info *info)
+{
+	u32 cmd = BIT(15) /* Execute cmd */
+		| 0 << 14 /* Write */
+		| 0 << 12 /* Table type 0b00 */
+		| (vlan & 0xfff);
+	u32 v;
+
+	sw_w32(info->tagged_ports, RTL838X_TBL_ACCESS_DATA_0(0));
+
+	v = info->profile_id;
+	v |= info->hash_mc_fid ? 0x8 : 0;
+	v |= info->hash_uc_fid ? 0x10 : 0;
+	v |= ((u32)info->fid) << 5;
+
+	sw_w32(v, RTL838X_TBL_ACCESS_DATA_0(1));
+	rtl838x_exec_tbl0_cmd(cmd);
+}
+
+static void rtl838x_vlan_set_untagged(u32 vlan, u64 portmask)
+{
+	u32 cmd = BIT(15) /* Execute cmd */
+		| 0 << 14 /* Write */
+		| 0 << 12 /* Table type 0b00 */
+		| (vlan & 0xfff);
+	sw_w32(portmask & 0x1fffffff, RTL838X_TBL_ACCESS_DATA_1(0));
+	rtl838x_exec_tbl1_cmd(cmd);
+}
+
+static inline int rtl838x_mac_force_mode_ctrl(int p)
+{
+	return RTL838X_MAC_FORCE_MODE_CTRL + (p << 2);
+}
+
+static inline int rtl838x_mac_port_ctrl(int p)
+{
+	return RTL838X_MAC_PORT_CTRL(p);
+}
+
+static inline int rtl838x_l2_port_new_salrn(int p)
+{
+	return RTL838X_L2_PORT_NEW_SALRN(p);
+}
+
+static inline int rtl838x_l2_port_new_sa_fwd(int p)
+{
+	return RTL838X_L2_PORT_NEW_SA_FWD(p);
+}
+
+static inline int rtl838x_mir_ctrl(int group)
+{
+	return RTL838X_MIR_CTRL(group);
+}
+
+static inline int rtl838x_mir_dpm(int group)
+{
+	return RTL838X_MIR_DPM_CTRL(group);
+}
+
+static inline int rtl838x_mir_spm(int group)
+{
+	return RTL838X_MIR_SPM_CTRL(group);
+}
+
+static inline int rtl838x_mac_link_spd_sts(int p)
+{
+	return RTL838X_MAC_LINK_SPD_STS(p);
+}
+
+static u64 rtl838x_read_l2_entry_using_hash(u32 hash, u32 position, struct rtl838x_l2_entry *e)
+{
+	u64 entry;
+	u32 r[3];
+
+	/* Search in SRAM, with hash and at position in hash bucket (0-3) */
+	u32 idx = (0 << 14) | (hash << 2) | position;
+
+	u32 cmd = BIT(16) /* Execute cmd */
+		| BIT(15) /* Read */
+		| 0 << 13 /* Table type 0b00 */
+		| (idx & 0x1fff);
+
+	sw_w32(cmd, RTL838X_TBL_ACCESS_L2_CTRL);
+	do { }  while (sw_r32(RTL838X_TBL_ACCESS_L2_CTRL) & BIT(16));
+	r[0] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(0));
+	r[1] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(1));
+	r[2] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(2));
+
+	e->mac[0] = (r[1] >> 20);
+	e->mac[1] = (r[1] >> 12);
+	e->mac[2] = (r[1] >> 4);
+	e->mac[3] = (r[1] & 0xf) << 4 | (r[2] >> 28);
+	e->mac[4] = (r[2] >> 20);
+	e->mac[5] = (r[2] >> 12);
+	e->is_static = !!((r[0] >> 19) & 1);
+	e->vid = r[0] & 0xfff;
+	e->rvid = r[2] & 0xfff;
+	e->port = (r[0] >> 12) & 0x1f;
+
+	e->valid = true;
+	if (!(r[0] >> 17)) /* Check for invalid entry */
+		e->valid = false;
+
+	if (e->valid)
+		pr_debug("Found in Hash: R1 %x R2 %x R3 %x\n", r[0], r[1], r[2]);
+
+	entry = (((u64) r[1]) << 32) | (r[2] & 0xfffff000) | (r[0] & 0xfff);
+	return entry;
+}
+
+static u64 rtl838x_read_cam(int idx, struct rtl838x_l2_entry *e)
+{
+	u64 entry;
+	u32 r[3];
+
+	u32 cmd = BIT(16) /* Execute cmd */
+		| BIT(15) /* Read */
+		| BIT(13) /* Table type 0b01 */
+		| (idx & 0x3f);
+	sw_w32(cmd, RTL838X_TBL_ACCESS_L2_CTRL);
+	do { }  while (sw_r32(RTL838X_TBL_ACCESS_L2_CTRL) & BIT(16));
+	r[0] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(0));
+	r[1] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(1));
+	r[2] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(2));
+
+	e->mac[0] = (r[1] >> 20);
+	e->mac[1] = (r[1] >> 12);
+	e->mac[2] = (r[1] >> 4);
+	e->mac[3] = (r[1] & 0xf) << 4 | (r[2] >> 28);
+	e->mac[4] = (r[2] >> 20);
+	e->mac[5] = (r[2] >> 12);
+	e->is_static = !!((r[0] >> 19) & 1);
+	e->vid = r[0] & 0xfff;
+	e->rvid = r[2] & 0xfff;
+	e->port = (r[0] >> 12) & 0x1f;
+
+	e->valid = true;
+	if (!(r[0] >> 17)) /* Check for invalid entry */
+		e->valid = false;
+
+	if (e->valid)
+		pr_debug("Found in CAM: R1 %x R2 %x R3 %x\n", r[0], r[1], r[2]);
+
+	entry = (((u64) r[1]) << 32) | (r[2] & 0xfffff000) | (r[0] & 0xfff);
+	return entry;
+}
+
+static inline int rtl838x_vlan_profile(int profile)
+{
+	return RTL838X_VLAN_PROFILE(profile);
+}
+
+static inline int rtl838x_vlan_port_egr_filter(int port)
+{
+	return RTL838X_VLAN_PORT_EGR_FLTR;
+}
+
+static inline int rtl838x_vlan_port_igr_filter(int port)
+{
+	return RTL838X_VLAN_PORT_IGR_FLTR(port);
+}
+
+static inline int rtl838x_vlan_port_pb(int port)
+{
+	return RTL838X_VLAN_PORT_PB_VLAN(port);
+}
+
+static inline int rtl838x_vlan_port_tag_sts_ctrl(int port)
+{
+	return RTL838X_VLAN_PORT_TAG_STS_CTRL(port);
+}
+
+const struct rtl838x_reg rtl838x_reg = {
+	.mask_port_reg_be = rtl838x_mask_port_reg,
+	.set_port_reg_be = rtl838x_set_port_reg,
+	.get_port_reg_be = rtl838x_get_port_reg,
+	.mask_port_reg_le = rtl838x_mask_port_reg,
+	.set_port_reg_le = rtl838x_set_port_reg,
+	.get_port_reg_le = rtl838x_get_port_reg,
+	.stat_port_rst = RTL838X_STAT_PORT_RST,
+	.stat_rst = RTL838X_STAT_RST,
+	.stat_port_std_mib = rtl838x_stat_port_std_mib,
+	.port_iso_ctrl = rtl838x_port_iso_ctrl,
+	.l2_ctrl_0 = RTL838X_L2_CTRL_0,
+	.l2_ctrl_1 = RTL838X_L2_CTRL_1,
+	.l2_port_aging_out = RTL838X_L2_PORT_AGING_OUT,
+	.smi_poll_ctrl = RTL838X_SMI_POLL_CTRL,
+	.l2_tbl_flush_ctrl = RTL838X_L2_TBL_FLUSH_CTRL,
+	.exec_tbl0_cmd = rtl838x_exec_tbl0_cmd,
+	.exec_tbl1_cmd = rtl838x_exec_tbl1_cmd,
+	.tbl_access_data_0 = rtl838x_tbl_access_data_0,
+	.isr_glb_src = RTL838X_ISR_GLB_SRC,
+	.isr_port_link_sts_chg = RTL838X_ISR_PORT_LINK_STS_CHG,
+	.imr_port_link_sts_chg = RTL838X_IMR_PORT_LINK_STS_CHG,
+	.imr_glb = RTL838X_IMR_GLB,
+	.vlan_tables_read = rtl838x_vlan_tables_read,
+	.vlan_set_tagged = rtl838x_vlan_set_tagged,
+	.vlan_set_untagged = rtl838x_vlan_set_untagged,
+	.mac_force_mode_ctrl = rtl838x_mac_force_mode_ctrl,
+	.mac_port_ctrl = rtl838x_mac_port_ctrl,
+	.l2_port_new_salrn = rtl838x_l2_port_new_salrn,
+	.l2_port_new_sa_fwd = rtl838x_l2_port_new_sa_fwd,
+	.mir_ctrl = rtl838x_mir_ctrl,
+	.mir_dpm = rtl838x_mir_dpm,
+	.mir_spm = rtl838x_mir_spm,
+	.mac_link_sts = RTL838X_MAC_LINK_STS,
+	.mac_link_dup_sts = RTL838X_MAC_LINK_DUP_STS,
+	.mac_link_spd_sts = rtl838x_mac_link_spd_sts,
+	.mac_rx_pause_sts = RTL838X_MAC_RX_PAUSE_STS,
+	.mac_tx_pause_sts = RTL838X_MAC_TX_PAUSE_STS,
+	.read_l2_entry_using_hash = rtl838x_read_l2_entry_using_hash,
+	.read_cam = rtl838x_read_cam,
+	.vlan_profile = rtl838x_vlan_profile,
+	.vlan_port_egr_filter = rtl838x_vlan_port_egr_filter,
+	.vlan_port_igr_filter = rtl838x_vlan_port_igr_filter,
+	.vlan_port_pb = rtl838x_vlan_port_pb,
+	.vlan_port_tag_sts_ctrl = rtl838x_vlan_port_tag_sts_ctrl,
+};
+
+irqreturn_t rtl838x_switch_irq(int irq, void *dev_id)
+{
+	struct dsa_switch *ds = dev_id;
+	u32 status = sw_r32(RTL838X_ISR_GLB_SRC);
+	u32 ports = sw_r32(RTL838X_ISR_PORT_LINK_STS_CHG);
+	u32 link;
+	int i;
+
+	/* Clear status */
+	sw_w32(ports, RTL838X_ISR_PORT_LINK_STS_CHG);
+	pr_debug("RTL8380 Link change: status: %x, ports %x\n", status, ports);
+
+	for (i = 0; i < 28; i++) {
+		if (ports & BIT(i)) {
+			link = sw_r32(RTL838X_MAC_LINK_STS);
+			if (link & BIT(i))
+				dsa_port_phylink_mac_change(ds, i, true);
+			else
+				dsa_port_phylink_mac_change(ds, i, false);
+		}
+	}
+	return IRQ_HANDLED;
+}
+
+int rtl838x_smi_wait_op(int timeout)
+{
+	do {
+		timeout--;
+		udelay(10);
+	} while ((sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1) & 0x1) && (timeout >= 0));
+	if (timeout <= 0)
+		return -1;
+	return 0;
+}
+
+/*
+ * Reads a register in a page from the PHY
+ */
+int rtl838x_read_phy(u32 port, u32 page, u32 reg, u32 *val)
+{
+	u32 v;
+	u32 park_page;
+
+	if (port > 31) {
+		*val = 0xffff;
+		return 0;
+	}
+
+	if (page > 4095 || reg > 31)
+		return -ENOTSUPP;
+
+	mutex_lock(&smi_lock);
+
+	if (rtl838x_smi_wait_op(10000))
+		goto timeout;
+
+	sw_w32_mask(0xffff0000, port << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2);
+
+	park_page = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1) & ((0x1f << 15) | 0x2);
+	v = reg << 20 | page << 3;
+	sw_w32(v | park_page, RTL838X_SMI_ACCESS_PHY_CTRL_1);
+	sw_w32_mask(0, 1, RTL838X_SMI_ACCESS_PHY_CTRL_1);
+
+	if (rtl838x_smi_wait_op(10000))
+		goto timeout;
+
+	*val = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_2) & 0xffff;
+
+	mutex_unlock(&smi_lock);
+	return 0;
+
+timeout:
+	mutex_unlock(&smi_lock);
+	return -ETIMEDOUT;
+}
+
+/*
+ * Write to a register in a page of the PHY
+ */
+int rtl838x_write_phy(u32 port, u32 page, u32 reg, u32 val)
+{
+	u32 v;
+	u32 park_page;
+
+	val &= 0xffff;
+	if (port > 31 || page > 4095 || reg > 31)
+		return -ENOTSUPP;
+
+	mutex_lock(&smi_lock);
+	if (rtl838x_smi_wait_op(10000))
+		goto timeout;
+
+	sw_w32(BIT(port), RTL838X_SMI_ACCESS_PHY_CTRL_0);
+	mdelay(10);
+
+	sw_w32_mask(0xffff0000, val << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2);
+
+	park_page = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1) & ((0x1f << 15) | 0x2);
+	v = reg << 20 | page << 3 | 0x4;
+	sw_w32(v | park_page, RTL838X_SMI_ACCESS_PHY_CTRL_1);
+	sw_w32_mask(0, 1, RTL838X_SMI_ACCESS_PHY_CTRL_1);
+
+	if (rtl838x_smi_wait_op(10000))
+		goto timeout;
+
+	mutex_unlock(&smi_lock);
+	return 0;
+
+timeout:
+	mutex_unlock(&smi_lock);
+	return -ETIMEDOUT;
+}
+
+void rtl8380_get_version(struct rtl838x_switch_priv *priv)
+{
+	u32 rw_save, info_save;
+	u32 info;
+
+	rw_save = sw_r32(RTL838X_INT_RW_CTRL);
+	sw_w32(rw_save | 0x3, RTL838X_INT_RW_CTRL);
+
+	info_save = sw_r32(RTL838X_CHIP_INFO);
+	sw_w32(info_save | 0xA0000000, RTL838X_CHIP_INFO);
+
+	info = sw_r32(RTL838X_CHIP_INFO);
+	sw_w32(info_save, RTL838X_CHIP_INFO);
+	sw_w32(rw_save, RTL838X_INT_RW_CTRL);
+
+	if ((info & 0xFFFF) == 0x6275) {
+		if (((info >> 16) & 0x1F) == 0x1)
+			priv->version = RTL8380_VERSION_A;
+		else if (((info >> 16) & 0x1F) == 0x2)
+			priv->version = RTL8380_VERSION_B;
+		else
+			priv->version = RTL8380_VERSION_B;
+	} else {
+		priv->version = '-';
+	}
+}
+
+/*
+ * Applies the same hash algorithm as the one used currently by the ASIC
+ */
+u32 rtl838x_hash(struct rtl838x_switch_priv *priv, u64 seed)
+{
+	u32 h1, h2, h3, h;
+
+	if (sw_r32(priv->r->l2_ctrl_0) & 1) {
+		h1 = (seed >> 11) & 0x7ff;
+		h1 = ((h1 & 0x1f) << 6) | ((h1 >> 5) & 0x3f);
+
+		h2 = (seed >> 33) & 0x7ff;
+		h2 = ((h2 & 0x3f) << 5) | ((h2 >> 6) & 0x1f);
+
+		h3 = (seed >> 44) & 0x7ff;
+		h3 = ((h3 & 0x7f) << 4) | ((h3 >> 7) & 0xf);
+
+		h = h1 ^ h2 ^ h3 ^ ((seed >> 55) & 0x1ff);
+		h ^= ((seed >> 22) & 0x7ff) ^ (seed & 0x7ff);
+	} else {
+		h = ((seed >> 55) & 0x1ff) ^ ((seed >> 44) & 0x7ff)
+			^ ((seed >> 33) & 0x7ff) ^ ((seed >> 22) & 0x7ff)
+			^ ((seed >> 11) & 0x7ff) ^ (seed & 0x7ff);
+	}
+
+	return h;
+}
+
+void rtl838x_vlan_profile_dump(int index)
+{
+	u32 profile;
+
+	if (index < 0 || index > 7)
+		return;
+
+	profile = sw_r32(RTL838X_VLAN_PROFILE(index));
+
+	pr_debug("VLAN %d: L2 learning: %d, L2 Unknown MultiCast Field %x, \
+		IPv4 Unknown MultiCast Field %x, IPv6 Unknown MultiCast Field: %x",
+		index, profile & 1, (profile >> 1) & 0x1ff, (profile >> 10) & 0x1ff,
+		(profile >> 19) & 0x1ff);
+}
diff --git a/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl838x.h b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl838x.h
new file mode 100644
index 0000000000..1ebb4dff72
--- /dev/null
+++ b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl838x.h
@@ -0,0 +1,293 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _RTL838X_H
+#define _RTL838X_H
+
+#include <net/dsa.h>
+
+/*
+ * Register definition
+ */
+#define RTL838X_CPU_PORT			28
+#define RTL839X_CPU_PORT			52
+
+#define RTL838X_MAC_PORT_CTRL(port)		(0xd560 + (((port) << 7)))
+#define RTL839X_MAC_PORT_CTRL(port)		(0x8004 + (((port) << 7)))
+#define RTL838X_RST_GLB_CTRL_0			(0x003c)
+#define RTL838X_MAC_FORCE_MODE_CTRL		(0xa104)
+#define RTL839X_MAC_FORCE_MODE_CTRL		(0x02bc)
+
+#define RTL838X_DMY_REG31			(0x3b28)
+#define RTL838X_SDS_MODE_SEL			(0x0028)
+#define RTL838X_SDS_CFG_REG			(0x0034)
+#define RTL838X_INT_MODE_CTRL			(0x005c)
+#define RTL838X_CHIP_INFO			(0x00d8)
+#define RTL839X_CHIP_INFO			(0x0ff4)
+#define RTL838X_SDS4_REG28			(0xef80)
+#define RTL838X_SDS4_DUMMY0			(0xef8c)
+#define RTL838X_SDS5_EXT_REG6			(0xf18c)
+#define RTL838X_PORT_ISO_CTRL(port)		(0x4100 + ((port) << 2))
+#define RTL839X_PORT_ISO_CTRL(port)		(0x1400 + ((port) << 3))
+#define RTL8380_SDS4_FIB_REG0			(0xF800)
+#define RTL838X_STAT_PORT_STD_MIB		(0x1200)
+#define RTL839X_STAT_PORT_STD_MIB		(0xC000)
+#define RTL838X_STAT_RST			(0x3100)
+#define RTL839X_STAT_RST			(0xF504)
+#define RTL838X_STAT_PORT_RST			(0x3104)
+#define RTL839X_STAT_PORT_RST			(0xF508)
+#define RTL838X_STAT_CTRL			(0x3108)
+#define RTL839X_STAT_CTRL			(0x04cc)
+
+/* Registers of the internal Serdes of the 8390 */
+#define RTL8390_SDS0_1_XSG0			(0xA000)
+#define RTL8390_SDS0_1_XSG1			(0xA100)
+#define RTL839X_SDS12_13_XSG0			(0xB800)
+#define RTL839X_SDS12_13_XSG1			(0xB900)
+#define RTL839X_SDS12_13_PWR0			(0xb880)
+#define RTL839X_SDS12_13_PWR1			(0xb980)
+
+/* Registers of the internal Serdes of the 8380 */
+#define MAPLE_SDS4_REG0r			RTL838X_SDS4_REG28
+#define MAPLE_SDS5_REG0r			(RTL838X_SDS4_REG28 + 0x100)
+#define MAPLE_SDS4_REG3r			RTL838X_SDS4_DUMMY0
+#define MAPLE_SDS5_REG3r			(RTL838X_SDS4_REG28 + 0x100)
+#define MAPLE_SDS4_FIB_REG0r			(RTL838X_SDS4_REG28 + 0x880)
+#define MAPLE_SDS5_FIB_REG0r			(RTL838X_SDS4_REG28 + 0x980)
+
+/* VLAN registers */
+#define RTL838X_VLAN_PROFILE(idx)		(0x3A88 + ((idx) << 2))
+#define RTL838X_VLAN_PORT_EGR_FLTR		(0x3A84)
+#define RTL838X_VLAN_PORT_PB_VLAN(port)		(0x3C00 + ((port) << 2))
+#define RTL838X_VLAN_PORT_IGR_FLTR(port)	(0x3A7C + (((port >> 4) << 2)))
+#define RTL838X_VLAN_PORT_IGR_FLTR_0		(0x3A7C)
+#define RTL838X_VLAN_PORT_IGR_FLTR_1		(0x3A7C + 4)
+#define RTL838X_VLAN_PORT_TAG_STS_CTRL(port)	(0xA530 + (((port) << 2)))
+#define RTL839X_VLAN_PROFILE(idx)		(0x25C0 + (((idx) << 3)))
+#define RTL839X_VLAN_CTRL			(0x26D4)
+#define RTL839X_VLAN_PORT_PB_VLAN(port)		(0x26D8 + (((port) << 2)))
+#define RTL839X_VLAN_PORT_IGR_FLTR(port)	(0x27B4 + (((port >> 4) << 2)))
+#define RTL839X_VLAN_PORT_EGR_FLTR(port)	(0x27C4 + (((port >> 5) << 2)))
+#define RTL839X_VLAN_PORT_TAG_STS_CTRL(port)	(0x6828 + (((port) << 2)))
+
+/* Table 0/1 access registers */
+#define RTL838X_TBL_ACCESS_CTRL_0		(0x6914)
+#define RTL838X_TBL_ACCESS_DATA_0(idx)		(0x6918 + ((idx) << 2))
+#define RTL838X_TBL_ACCESS_CTRL_1		(0xA4C8)
+#define RTL838X_TBL_ACCESS_DATA_1(idx)		(0xA4CC + ((idx) << 2))
+#define RTL839X_TBL_ACCESS_CTRL_0		(0x1190)
+#define RTL839X_TBL_ACCESS_DATA_0(idx)		(0x1194 + ((idx) << 2))
+#define RTL839X_TBL_ACCESS_CTRL_1		(0x6b80)
+#define RTL839X_TBL_ACCESS_DATA_1(idx)		(0x6b84 + ((idx) << 2))
+
+/* MAC handling */
+#define RTL838X_MAC_LINK_STS			(0xa188)
+#define RTL839X_MAC_LINK_STS			(0x0390)
+#define RTL838X_MAC_LINK_SPD_STS(port)		(0xa190 + (((port >> 4) << 2)))
+#define RTL839X_MAC_LINK_SPD_STS(port)		(0x03a0 + (((port >> 4) << 2)))
+#define RTL838X_MAC_LINK_DUP_STS		(0xa19c)
+#define RTL839X_MAC_LINK_DUP_STS		(0x03b0)
+#define RTL838X_MAC_TX_PAUSE_STS		(0xa1a0)
+#define RTL839X_MAC_TX_PAUSE_STS		(0x03b8)
+#define RTL838X_MAC_RX_PAUSE_STS		(0xa1a4)
+#define RTL839X_MAC_RX_PAUSE_STS		(0x03c0)
+#define RTL838X_EEE_TX_TIMER_GIGA_CTRL		(0xaa04)
+#define RTL838X_EEE_TX_TIMER_GELITE_CTRL	(0xaa08)
+
+#define RTL838X_DMA_IF_CTRL			(0x9f58)
+
+/* MAC link state bits */
+#define FORCE_EN				(1 << 0)
+#define FORCE_LINK_EN				(1 << 1)
+#define NWAY_EN					(1 << 2)
+#define DUPLX_MODE				(1 << 3)
+#define TX_PAUSE_EN				(1 << 6)
+#define RX_PAUSE_EN				(1 << 7)
+
+/* EEE */
+#define RTL838X_MAC_EEE_ABLTY			(0xa1a8)
+#define RTL838X_EEE_PORT_TX_EN			(0x014c)
+#define RTL838X_EEE_PORT_RX_EN			(0x0150)
+#define RTL838X_EEE_CLK_STOP_CTRL		(0x0148)
+
+/* L2 functionality */
+#define RTL838X_L2_CTRL_0			(0x3200)
+#define RTL839X_L2_CTRL_0			(0x3800)
+#define RTL838X_L2_CTRL_1			(0x3204)
+#define RTL839X_L2_CTRL_1			(0x3804)
+#define RTL838X_L2_PORT_AGING_OUT		(0x3358)
+#define RTL839X_L2_PORT_AGING_OUT		(0x3b74)
+#define RTL838X_TBL_ACCESS_L2_CTRL		(0x6900)
+#define RTL839X_TBL_ACCESS_L2_CTRL		(0x1180)
+#define RTL838X_TBL_ACCESS_L2_DATA(idx)		(0x6908 + ((idx) << 2))
+#define RTL839X_TBL_ACCESS_L2_DATA(idx)		(0x1184 + ((idx) << 2))
+#define RTL838X_L2_TBL_FLUSH_CTRL		(0x3370)
+#define RTL839X_L2_TBL_FLUSH_CTRL		(0x3ba0)
+#define RTL838X_L2_PORT_NEW_SALRN(p)		(0x328c + (((p >> 4) << 2)))
+#define RTL839X_L2_PORT_NEW_SALRN(p)		(0x38F0 + (((p >> 4) << 2)))
+#define RTL838X_L2_PORT_NEW_SA_FWD(p)		(0x3294 + (((p >> 4) << 2)))
+#define RTL839X_L2_PORT_NEW_SA_FWD(p)		(0x3900 + (((p >> 4) << 2)))
+#define RTL838X_L2_PORT_SALRN(p)		(0x328c + (((p >> 4) << 2)))
+#define RTL839X_L2_PORT_SALRN(p)		(0x38F0 + (((p >> 4) << 2)))
+
+/* Port Mirroring */
+#define RTL838X_MIR_CTRL(grp)			(0x5D00 + (((grp) << 2)))
+#define RTL838X_MIR_DPM_CTRL(grp)		(0x5D20 + (((grp) << 2)))
+#define RTL838X_MIR_SPM_CTRL(grp)		(0x5D10 + (((grp) << 2)))
+#define RTL839X_MIR_CTRL(grp)			(0x2500 + (((grp) << 2)))
+#define RTL839X_MIR_DPM_CTRL(grp)		(0x2530 + (((grp) << 2)))
+#define RTL839X_MIR_SPM_CTRL(grp)		(0x2510 + (((grp) << 2)))
+
+/* Storm control */
+#define RTL838X_STORM_CTRL			(0x4700)
+#define RTL839X_STORM_CTRL			(0x1800)
+#define RTL838X_STORM_CTRL_LB_CTRL(p)		(0x4884 + (((p) << 2)))
+#define RTL838X_STORM_CTRL_BURST_PPS_0		(0x4874)
+#define RTL838X_STORM_CTRL_BURST_PPS_1		(0x4878)
+#define RTL838X_STORM_CTRL_BURST_0		(0x487c)
+#define RTL838X_STORM_CTRL_BURST_1		(0x4880)
+#define RTL838X_SCHED_CTRL			(0xB980)
+#define RTL838X_SCHED_LB_TICK_TKN_CTRL_0	(0xAD58)
+#define RTL838X_SCHED_LB_TICK_TKN_CTRL_1	(0xAD5C)
+#define RTL839X_SCHED_LB_TICK_TKN_CTRL_0	(0x1804)
+#define RTL839X_SCHED_LB_TICK_TKN_CTRL_1	(0x1808)
+#define RTL838X_SCHED_LB_THR			(0xB984)
+#define RTL838X_STORM_CTRL_PORT_BC_EXCEED	(0x470C)
+#define RTL838X_STORM_CTRL_PORT_MC_EXCEED	(0x4710)
+#define RTL838X_STORM_CTRL_PORT_UC_EXCEED	(0x4714)
+#define RTL839X_STORM_CTRL_PORT_BC_EXCEED(p)	(0x180c + (((p >> 5) << 2)))
+#define RTL839X_STORM_CTRL_PORT_MC_EXCEED(p)	(0x1814 + (((p >> 5) << 2)))
+#define RTL839X_STORM_CTRL_PORT_UC_EXCEED(p)	(0x181c + (((p >> 5) << 2)))
+#define RTL838X_STORM_CTRL_PORT_UC(p)		(0x4718 + (((p) << 2)))
+#define RTL838X_STORM_CTRL_PORT_MC(p)		(0x478c + (((p) << 2)))
+#define RTL838X_STORM_CTRL_PORT_BC(p)		(0x4800 + (((p) << 2)))
+
+/* Attack prevention */
+#define RTL838X_ATK_PRVNT_PORT_EN		(0x5B00)
+#define RTL838X_ATK_PRVNT_CTRL			(0x5B04)
+#define RTL838X_ATK_PRVNT_ACT			(0x5B08)
+#define RTL838X_ATK_PRVNT_STS			(0x5B1C)
+
+enum phy_type {
+	PHY_NONE = 0,
+	PHY_RTL838X_SDS = 1,
+	PHY_RTL8218B_INT = 2,
+	PHY_RTL8218B_EXT = 3,
+	PHY_RTL8214FC = 4,
+	PHY_RTL839X_SDS = 5,
+};
+
+struct rtl838x_port {
+	bool enable;
+	u64 pm;
+	u16 pvid;
+	bool eee_enabled;
+	enum phy_type phy;
+	const struct dsa_port *dp;
+};
+
+struct rtl838x_vlan_info {
+	u64 untagged_ports;
+	u64 tagged_ports;
+	u8 profile_id;
+	bool hash_mc_fid;
+	bool hash_uc_fid;
+	u8 fid;
+};
+
+enum l2_entry_type {
+	L2_INVALID = 0,
+	L2_UNICAST = 1,
+	L2_MULTICAST = 2,
+	IP4_MULTICAST = 3,
+	IP6_MULTICAST = 4,
+};
+
+struct rtl838x_l2_entry {
+	u8 mac[6];
+	u16 vid;
+	u16 rvid;
+	u8 port;
+	bool valid;
+	enum l2_entry_type type;
+	bool is_static;
+	bool is_ip_mc;
+	bool is_ipv6_mc;
+	bool block_da;
+	bool block_sa;
+	bool suspended;
+	bool next_hop;
+	int age;
+	u16 mc_portmask_index;
+};
+
+struct rtl838x_switch_priv;
+
+struct rtl838x_reg {
+	void (*mask_port_reg_be)(u64 clear, u64 set, int reg);
+	void (*set_port_reg_be)(u64 set, int reg);
+	u64 (*get_port_reg_be)(int reg);
+	void (*mask_port_reg_le)(u64 clear, u64 set, int reg);
+	void (*set_port_reg_le)(u64 set, int reg);
+	u64 (*get_port_reg_le)(int reg);
+	int stat_port_rst;
+	int stat_rst;
+	int (*stat_port_std_mib)(int p);
+	int (*port_iso_ctrl)(int p);
+	int l2_ctrl_0;
+	int l2_ctrl_1;
+	int l2_port_aging_out;
+	int smi_poll_ctrl;
+	int l2_tbl_flush_ctrl;
+	void (*exec_tbl0_cmd)(u32 cmd);
+	void (*exec_tbl1_cmd)(u32 cmd);
+	int (*tbl_access_data_0)(int i);
+	int isr_glb_src;
+	int isr_port_link_sts_chg;
+	int imr_port_link_sts_chg;
+	int imr_glb;
+	void (*vlan_tables_read)(u32 vlan, struct rtl838x_vlan_info *info);
+	void (*vlan_set_tagged)(u32 vlan, struct rtl838x_vlan_info *info);
+	void (*vlan_set_untagged)(u32 vlan, u64 portmask);
+	int  (*mac_force_mode_ctrl)(int port);
+	int  (*mac_port_ctrl)(int port);
+	int  (*l2_port_new_salrn)(int port);
+	int  (*l2_port_new_sa_fwd)(int port);
+	int  (*mir_ctrl)(int group);
+	int  (*mir_dpm)(int group);
+	int  (*mir_spm)(int group);
+	int mac_link_sts;
+	int mac_link_dup_sts;
+	int  (*mac_link_spd_sts)(int port);
+	int mac_rx_pause_sts;
+	int mac_tx_pause_sts;
+	u64 (*read_l2_entry_using_hash)(u32 hash, u32 position, struct rtl838x_l2_entry *e);
+	u64 (*read_cam)(int idx, struct rtl838x_l2_entry *e);
+	int (*vlan_profile)(int profile);
+	int (*vlan_port_egr_filter)(int port);
+	int (*vlan_port_igr_filter)(int port);
+	int (*vlan_port_pb)(int port);
+	int (*vlan_port_tag_sts_ctrl)(int port);
+};
+
+struct rtl838x_switch_priv {
+	/* Switch operation */
+	struct dsa_switch *ds;
+	struct device *dev;
+	u16 id;
+	u16 family_id;
+	char version;
+	struct rtl838x_port ports[54]; /* TODO: correct size! */
+	struct mutex reg_mutex;
+	int link_state_irq;
+	int mirror_group_ports[4];
+	struct mii_bus *mii_bus;
+	const struct rtl838x_reg *r;
+	u8 cpu_port;
+	u8 port_mask;
+	u32 fib_entries;
+	struct dentry *dbgfs_dir;
+};
+
+void rtl838x_dbgfs_init(struct rtl838x_switch_priv *priv);
+
+#endif /* _RTL838X_H */
diff --git a/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl839x.c b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl839x.c
new file mode 100644
index 0000000000..8dd123f609
--- /dev/null
+++ b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl839x.c
@@ -0,0 +1,514 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <asm/mach-rtl838x/mach-rtl83xx.h>
+#include "rtl83xx.h"
+
+extern struct mutex smi_lock;
+
+
+static inline void rtl839x_mask_port_reg_be(u64 clear, u64 set, int reg)
+{
+	sw_w32_mask((u32)(clear >> 32), (u32)(set >> 32), reg);
+	sw_w32_mask((u32)(clear & 0xffffffff), (u32)(set & 0xffffffff), reg + 4);
+}
+
+static inline u64 rtl839x_get_port_reg_be(int reg)
+{
+	u64 v = sw_r32(reg);
+
+	v <<= 32;
+	v |= sw_r32(reg + 4);
+	return v;
+}
+
+static inline void rtl839x_set_port_reg_be(u64 set, int reg)
+{
+	sw_w32(set >> 32, reg);
+	sw_w32(set & 0xffffffff, reg + 4);
+}
+
+static inline void rtl839x_mask_port_reg_le(u64 clear, u64 set, int reg)
+{
+	sw_w32_mask((u32)clear, (u32)set, reg);
+	sw_w32_mask((u32)(clear >> 32), (u32)(set >> 32), reg + 4);
+}
+
+static inline void rtl839x_set_port_reg_le(u64 set, int reg)
+{
+	sw_w32(set, reg);
+	sw_w32(set >> 32, reg + 4);
+}
+
+static inline u64 rtl839x_get_port_reg_le(int reg)
+{
+	u64 v = sw_r32(reg + 4);
+
+	v <<= 32;
+	v |= sw_r32(reg);
+	return v;
+}
+
+static inline int rtl839x_stat_port_std_mib(int p)
+{
+	return RTL839X_STAT_PORT_STD_MIB + (p << 8);
+}
+
+static inline int rtl839x_port_iso_ctrl(int p)
+{
+	return RTL839X_PORT_ISO_CTRL(p);
+}
+
+static inline void rtl839x_exec_tbl0_cmd(u32 cmd)
+{
+	sw_w32(cmd, RTL839X_TBL_ACCESS_CTRL_0);
+	do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_0) & BIT(16));
+}
+
+static inline void rtl839x_exec_tbl1_cmd(u32 cmd)
+{
+	sw_w32(cmd, RTL839X_TBL_ACCESS_CTRL_1);
+	do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_1) & BIT(16));
+}
+
+static inline int rtl839x_tbl_access_data_0(int i)
+{
+	return RTL839X_TBL_ACCESS_DATA_0(i);
+}
+
+static void rtl839x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info)
+{
+	u32 cmd;
+	u64 v;
+	u32 u, w;
+
+	cmd = BIT(16) /* Execute cmd */
+		| 0 << 15 /* Read */
+		| 0 << 12 /* Table type 0b000 */
+		| (vlan & 0xfff);
+	rtl839x_exec_tbl0_cmd(cmd);
+
+	v = sw_r32(RTL838X_TBL_ACCESS_DATA_0(0));
+	v <<= 32;
+	u = sw_r32(RTL838X_TBL_ACCESS_DATA_0(1));
+	v |= u;
+	info->tagged_ports = v >> 11;
+
+	w = sw_r32(RTL838X_TBL_ACCESS_DATA_0(2));
+
+	info->profile_id = w >> 30 | ((u & 1) << 2);
+	info->hash_mc_fid = !!(u & 2);
+	info->hash_uc_fid = !!(u & 4);
+	info->fid = (u >> 3) & 0xff;
+
+	cmd = BIT(16) /* Execute cmd */
+		| 0 << 15 /* Read */
+		| 0 << 12 /* Table type 0b000 */
+		| (vlan & 0xfff);
+	rtl839x_exec_tbl1_cmd(cmd);
+	v = sw_r32(RTL838X_TBL_ACCESS_DATA_1(0));
+	v <<= 32;
+	v |= sw_r32(RTL838X_TBL_ACCESS_DATA_1(1));
+	info->untagged_ports = v >> 11;
+}
+
+static void rtl839x_vlan_set_tagged(u32 vlan, struct rtl838x_vlan_info *info)
+{
+	u32 cmd = BIT(16) /* Execute cmd */
+		| BIT(15) /* Write */
+		| 0 << 12 /* Table type 0b00 */
+		| (vlan & 0xfff);
+	u32 w;
+	u64 v = info->tagged_ports << 11;
+
+	v |= info->profile_id >> 2;
+	v |= info->hash_mc_fid ? 2 : 0;
+	v |= info->hash_uc_fid ? 4 : 0;
+	v |= ((u32)info->fid) << 3;
+	rtl839x_set_port_reg_be(v, RTL838X_TBL_ACCESS_DATA_0(0));
+
+	w = info->profile_id;
+	sw_w32(w << 30, RTL838X_TBL_ACCESS_DATA_0(2));
+	rtl839x_exec_tbl0_cmd(cmd);
+}
+
+static void rtl839x_vlan_set_untagged(u32 vlan, u64 portmask)
+{
+	u32 cmd = BIT(16) /* Execute cmd */
+		| BIT(15) /* Write */
+		| 0 << 12 /* Table type 0b00 */
+		| (vlan & 0xfff);
+	rtl839x_set_port_reg_be(portmask << 11, RTL838X_TBL_ACCESS_DATA_1(0));
+	rtl839x_exec_tbl1_cmd(cmd);
+}
+
+static inline int rtl839x_mac_force_mode_ctrl(int p)
+{
+	return RTL839X_MAC_FORCE_MODE_CTRL + (p << 2);
+}
+
+static inline int rtl839x_mac_port_ctrl(int p)
+{
+	return RTL839X_MAC_PORT_CTRL(p);
+}
+
+static inline int rtl839x_l2_port_new_salrn(int p)
+{
+	return RTL839X_L2_PORT_NEW_SALRN(p);
+}
+
+static inline int rtl839x_l2_port_new_sa_fwd(int p)
+{
+	return RTL839X_L2_PORT_NEW_SA_FWD(p);
+}
+
+static inline int rtl839x_mir_ctrl(int group)
+{
+	return RTL839X_MIR_CTRL(group);
+}
+
+static inline int rtl839x_mir_dpm(int group)
+{
+	return RTL839X_MIR_DPM_CTRL(group);
+}
+
+static inline int rtl839x_mir_spm(int group)
+{
+	return RTL839X_MIR_SPM_CTRL(group);
+}
+
+static inline int rtl839x_mac_link_spd_sts(int p)
+{
+	return RTL839X_MAC_LINK_SPD_STS(p);
+}
+
+static u64 rtl839x_read_l2_entry_using_hash(u32 hash, u32 position, struct rtl838x_l2_entry *e)
+{
+	u64 entry;
+	u32 r[3];
+
+	/* Search in SRAM, with hash and at position in hash bucket (0-3) */
+	u32 idx = (0 << 14) | (hash << 2) | position;
+
+	u32 cmd = BIT(17) /* Execute cmd */
+		| 0 << 16 /* Read */
+		| 0 << 14 /* Table type 0b00 */
+		| (idx & 0x3fff);
+
+	sw_w32(cmd, RTL839X_TBL_ACCESS_L2_CTRL);
+	do { }  while (sw_r32(RTL839X_TBL_ACCESS_L2_CTRL) & BIT(17));
+	r[0] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(0));
+	r[1] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(1));
+	r[2] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(2));
+
+	/* Table contains different entry types, we need to identify the right one:
+	 * Check for MC entries, first
+	 */
+	e->is_ip_mc = !!(r[2] & BIT(31));
+	e->is_ipv6_mc = !!(r[2] & BIT(30));
+	e->type = L2_INVALID;
+	if (!e->is_ip_mc) {
+		e->mac[0] = (r[0] >> 12);
+		e->mac[1] = (r[0] >> 4);
+		e->mac[2] = ((r[1] >> 28) | (r[0] << 4));
+		e->mac[3] = (r[1] >> 20);
+		e->mac[4] = (r[1] >> 12);
+		e->mac[5] = (r[1] >> 4);
+
+		/* Is it a unicast entry? check multicast bit */
+		if (!(e->mac[0] & 1)) {
+			e->is_static = !!((r[2] >> 18) & 1);
+			e->vid = (r[2] >> 4) & 0xfff;
+			e->rvid = (r[0] >> 20) & 0xfff;
+			e->port = (r[2] >> 24) & 0x3f;
+			e->block_da = !!(r[2] & BIT(19));
+			e->block_sa = !!(r[2] & BIT(20));
+			e->suspended = !!(r[2] & BIT(17));
+			e->next_hop = !!(r[2] & BIT(16));
+			if (e->next_hop)
+				pr_debug("Found next hop entry, need to read data\n");
+			e->age = (r[2] >> 21) & 3;
+			e->valid = true;
+			if (!(r[2] & 0xc0fd0000)) /* Check for valid entry */
+				e->valid = false;
+			else
+				e->type = L2_UNICAST;
+		} else {
+			e->valid = true;
+			e->type = L2_MULTICAST;
+			e->mc_portmask_index = (r[2]>>6) & 0xfff;
+		}
+	}
+	if (e->is_ip_mc) {
+		e->valid = true;
+		e->type = IP4_MULTICAST;
+	}
+	if (e->is_ipv6_mc) {
+		e->valid = true;
+		e->type = IP6_MULTICAST;
+	}
+
+	entry = (((u64) r[0]) << 12) | ((r[1] & 0xfffffff0) << 12) | ((r[2] >> 4) & 0xfff);
+	return entry;
+}
+
+static u64 rtl839x_read_cam(int idx, struct rtl838x_l2_entry *e)
+{
+	u64 entry;
+	u32 r[3];
+
+	u32 cmd = BIT(17) /* Execute cmd */
+		| 0 << 16 /* Read */
+		| BIT(14) /* Table type 0b01 */
+		| (idx & 0x3f);
+	sw_w32(cmd, RTL839X_TBL_ACCESS_L2_CTRL);
+	do { }  while (sw_r32(RTL839X_TBL_ACCESS_L2_CTRL) & BIT(17));
+	r[0] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(0));
+	r[1] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(1));
+	r[2] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(2));
+
+	e->mac[0] = (r[0] >> 12);
+	e->mac[1] = (r[0] >> 4);
+	e->mac[2] = ((r[1] >> 28) | (r[0] << 4));
+	e->mac[3] = (r[1] >> 20);
+	e->mac[4] = (r[1] >> 12);
+	e->mac[5] = (r[1] >> 4);
+	e->is_static = !!((r[2] >> 18) & 1);
+	e->vid = (r[2] >> 4) & 0xfff;
+	e->rvid = (r[0] >> 20) & 0xfff;
+	e->port = (r[2] >> 24) & 0x3f;
+
+	e->valid = true;
+	if (!(r[2] & 0x10fd0000)) /* Check for invalid entry */
+		e->valid = false;
+
+	if (e->valid)
+		pr_debug("Found in CAM: R1 %x R2 %x R3 %x\n", r[0], r[1], r[2]);
+
+	entry = (((u64) r[0]) << 12) | ((r[1] & 0xfffffff0) << 12) | ((r[2] >> 4) & 0xfff);
+	return entry;
+}
+
+static inline int rtl839x_vlan_profile(int profile)
+{
+	return RTL839X_VLAN_PROFILE(profile);
+}
+
+static inline int rtl839x_vlan_port_egr_filter(int port)
+{
+	return RTL839X_VLAN_PORT_EGR_FLTR(port);
+}
+
+static inline int rtl839x_vlan_port_igr_filter(int port)
+{
+	return RTL839X_VLAN_PORT_IGR_FLTR(port);
+}
+
+static inline int rtl839x_vlan_port_pb(int port)
+{
+	return RTL839X_VLAN_PORT_PB_VLAN(port);
+}
+
+static inline int rtl839x_vlan_port_tag_sts_ctrl(int port)
+{
+	return RTL839X_VLAN_PORT_TAG_STS_CTRL(port);
+}
+
+const struct rtl838x_reg rtl839x_reg = {
+	.mask_port_reg_be = rtl839x_mask_port_reg_be,
+	.set_port_reg_be = rtl839x_set_port_reg_be,
+	.get_port_reg_be = rtl839x_get_port_reg_be,
+	.mask_port_reg_le = rtl839x_mask_port_reg_le,
+	.set_port_reg_le = rtl839x_set_port_reg_le,
+	.get_port_reg_le = rtl839x_get_port_reg_le,
+	.stat_port_rst = RTL839X_STAT_PORT_RST,
+	.stat_rst = RTL839X_STAT_RST,
+	.stat_port_std_mib = rtl839x_stat_port_std_mib,
+	.port_iso_ctrl = rtl839x_port_iso_ctrl,
+	.l2_ctrl_0 = RTL839X_L2_CTRL_0,
+	.l2_ctrl_1 = RTL839X_L2_CTRL_1,
+	.l2_port_aging_out = RTL839X_L2_PORT_AGING_OUT,
+	.smi_poll_ctrl = RTL839X_SMI_PORT_POLLING_CTRL,
+	.l2_tbl_flush_ctrl = RTL839X_L2_TBL_FLUSH_CTRL,
+	.exec_tbl0_cmd = rtl839x_exec_tbl0_cmd,
+	.exec_tbl1_cmd = rtl839x_exec_tbl1_cmd,
+	.tbl_access_data_0 = rtl839x_tbl_access_data_0,
+	.isr_glb_src = RTL839X_ISR_GLB_SRC,
+	.isr_port_link_sts_chg = RTL839X_ISR_PORT_LINK_STS_CHG,
+	.imr_port_link_sts_chg = RTL839X_IMR_PORT_LINK_STS_CHG,
+	.imr_glb = RTL839X_IMR_GLB,
+	.vlan_tables_read = rtl839x_vlan_tables_read,
+	.vlan_set_tagged = rtl839x_vlan_set_tagged,
+	.vlan_set_untagged = rtl839x_vlan_set_untagged,
+	.mac_force_mode_ctrl = rtl839x_mac_force_mode_ctrl,
+	.mac_port_ctrl = rtl839x_mac_port_ctrl,
+	.l2_port_new_salrn = rtl839x_l2_port_new_salrn,
+	.l2_port_new_sa_fwd = rtl839x_l2_port_new_sa_fwd,
+	.mir_ctrl = rtl839x_mir_ctrl,
+	.mir_dpm = rtl839x_mir_dpm,
+	.mir_spm = rtl839x_mir_spm,
+	.mac_link_sts = RTL839X_MAC_LINK_STS,
+	.mac_link_dup_sts = RTL839X_MAC_LINK_DUP_STS,
+	.mac_link_spd_sts = rtl839x_mac_link_spd_sts,
+	.mac_rx_pause_sts = RTL839X_MAC_RX_PAUSE_STS,
+	.mac_tx_pause_sts = RTL839X_MAC_TX_PAUSE_STS,
+	.read_l2_entry_using_hash = rtl839x_read_l2_entry_using_hash,
+	.read_cam = rtl839x_read_cam,
+	.vlan_profile = rtl839x_vlan_profile,
+	.vlan_port_egr_filter = rtl839x_vlan_port_egr_filter,
+	.vlan_port_igr_filter = rtl839x_vlan_port_igr_filter,
+	.vlan_port_pb = rtl839x_vlan_port_pb,
+	.vlan_port_tag_sts_ctrl = rtl839x_vlan_port_tag_sts_ctrl,
+};
+
+irqreturn_t rtl839x_switch_irq(int irq, void *dev_id)
+{
+	struct dsa_switch *ds = dev_id;
+	u32 status = sw_r32(RTL839X_ISR_GLB_SRC);
+	u64 ports = rtl839x_get_port_reg_le(RTL839X_ISR_PORT_LINK_STS_CHG);
+	u64 link;
+	int i;
+
+	/* Clear status */
+	rtl839x_set_port_reg_le(ports, RTL839X_ISR_PORT_LINK_STS_CHG);
+	pr_debug("RTL8390 Link change: status: %x, ports %llx\n", status, ports);
+
+	for (i = 0; i < 52; i++) {
+		if (ports & (1ULL << i)) {
+			link = rtl839x_get_port_reg_le(RTL839X_MAC_LINK_STS);
+			if (link & (1ULL << i))
+				dsa_port_phylink_mac_change(ds, i, true);
+			else
+				dsa_port_phylink_mac_change(ds, i, false);
+		}
+	}
+	return IRQ_HANDLED;
+}
+
+// TODO: unused
+int rtl8390_sds_power(int mac, int val)
+{
+	u32 offset = (mac == 48) ? 0x0 : 0x100;
+	u32 mode = val ? 0 : 1;
+
+	pr_debug("In %s: mac %d, set %d\n", __func__, mac, val);
+
+	if ((mac != 48) && (mac != 49)) {
+		pr_err("%s: not an SFP port: %d\n", __func__, mac);
+		return -1;
+	}
+
+	// Set bit 1003. 1000 starts at 7c
+	sw_w32_mask(BIT(11), mode << 11, RTL839X_SDS12_13_PWR0 + offset);
+
+	return 0;
+}
+
+int rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val)
+{
+	u32 v;
+
+	if (port > 63 || page > 4095 || reg > 31)
+		return -ENOTSUPP;
+
+	mutex_lock(&smi_lock);
+
+	sw_w32_mask(0xffff0000, port << 16, RTL839X_PHYREG_DATA_CTRL);
+	v = reg << 5 | page << 10 | ((page == 0x1fff) ? 0x1f : 0) << 23;
+	sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
+
+	sw_w32(0x1ff, RTL839X_PHYREG_CTRL);
+
+	v |= 1;
+	sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
+
+	do {
+	} while (sw_r32(RTL839X_PHYREG_ACCESS_CTRL) & 0x1);
+
+	*val = sw_r32(RTL839X_PHYREG_DATA_CTRL) & 0xffff;
+
+	mutex_unlock(&smi_lock);
+	return 0;
+}
+
+int rtl839x_write_phy(u32 port, u32 page, u32 reg, u32 val)
+{
+	u32 v;
+	int err = 0;
+
+	val &= 0xffff;
+	if (port > 63 || page > 4095 || reg > 31)
+		return -ENOTSUPP;
+
+	mutex_lock(&smi_lock);
+	/* Clear both port registers */
+	sw_w32(0, RTL839X_PHYREG_PORT_CTRL(0));
+	sw_w32(0, RTL839X_PHYREG_PORT_CTRL(0) + 4);
+	sw_w32_mask(0, BIT(port), RTL839X_PHYREG_PORT_CTRL(port));
+
+	sw_w32_mask(0xffff0000, val << 16, RTL839X_PHYREG_DATA_CTRL);
+
+	v = reg << 5 | page << 10 | ((page == 0x1fff) ? 0x1f : 0) << 23;
+	sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
+
+	sw_w32(0x1ff, RTL839X_PHYREG_CTRL);
+
+	v |= BIT(3) | 1; /* Write operation and execute */
+	sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
+
+	do {
+	} while (sw_r32(RTL839X_PHYREG_ACCESS_CTRL) & 0x1);
+
+	if (sw_r32(RTL839X_PHYREG_ACCESS_CTRL) & 0x2)
+		err = -EIO;
+
+	mutex_unlock(&smi_lock);
+	return err;
+}
+
+void rtl8390_get_version(struct rtl838x_switch_priv *priv)
+{
+	u32 info;
+
+	sw_w32_mask(0xf << 28, 0xa << 28, RTL839X_CHIP_INFO);
+	info = sw_r32(RTL839X_CHIP_INFO);
+	pr_debug("Chip-Info: %x\n", info);
+	priv->version = RTL8390_VERSION_A;
+}
+
+u32 rtl839x_hash(struct rtl838x_switch_priv *priv, u64 seed)
+{
+	u32 h1, h2, h;
+
+	if (sw_r32(priv->r->l2_ctrl_0) & 1) {
+		h1 = (u32) (((seed >> 60) & 0x3f) ^ ((seed >> 54) & 0x3f)
+				^ ((seed >> 36) & 0x3f) ^ ((seed >> 30) & 0x3f)
+				^ ((seed >> 12) & 0x3f) ^ ((seed >> 6) & 0x3f));
+		h2 = (u32) (((seed >> 48) & 0x3f) ^ ((seed >> 42) & 0x3f)
+				^ ((seed >> 24) & 0x3f) ^ ((seed >> 18) & 0x3f)
+				^ (seed & 0x3f));
+		h = (h1 << 6) | h2;
+	} else {
+		h = (seed >> 60)
+			^ ((((seed >> 48) & 0x3f) << 6) | ((seed >> 54) & 0x3f))
+			^ ((seed >> 36) & 0xfff) ^ ((seed >> 24) & 0xfff)
+			^ ((seed >> 12) & 0xfff) ^ (seed & 0xfff);
+	}
+
+	return h;
+}
+
+void rtl839x_vlan_profile_dump(int index)
+{
+	u32 profile, profile1;
+
+	if (index < 0 || index > 7)
+		return;
+
+	profile1 = sw_r32(RTL839X_VLAN_PROFILE(index) + 4);
+	profile = sw_r32(RTL839X_VLAN_PROFILE(index));
+
+	pr_debug("VLAN %d: L2 learning: %d, L2 Unknown MultiCast Field %x, \
+		IPv4 Unknown MultiCast Field %x, IPv6 Unknown MultiCast Field: %x",
+		index, profile & 1, (profile >> 1) & 0xfff, (profile >> 13) & 0xfff,
+		(profile1) & 0xfff);
+}
diff --git a/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl83xx.h b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl83xx.h
new file mode 100644
index 0000000000..3953512525
--- /dev/null
+++ b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl83xx.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _NET_DSA_RTL83XX_H
+#define _NET_DSA_RTL83XX_H
+
+#include <net/dsa.h>
+#include "rtl838x.h"
+
+
+#define RTL8380_VERSION_A 'A'
+#define RTL8390_VERSION_A 'A'
+#define RTL8380_VERSION_B 'B'
+
+struct fdb_update_work {
+	struct work_struct work;
+	struct net_device *ndev;
+	u64 macs[];
+};
+
+#define MIB_DESC(_size, _offset, _name) {.size = _size, .offset = _offset, .name = _name}
+struct rtl83xx_mib_desc {
+	unsigned int size;
+	unsigned int offset;
+	const char *name;
+};
+
+void __init rtl83xx_storm_control_init(struct rtl838x_switch_priv *priv);
+
+/* RTL838x-specific */
+u32 rtl838x_hash(struct rtl838x_switch_priv *priv, u64 seed);
+irqreturn_t rtl838x_switch_irq(int irq, void *dev_id);
+void rtl8380_get_version(struct rtl838x_switch_priv *priv);
+void rtl838x_vlan_profile_dump(int index);
+int rtl83xx_dsa_phy_read(struct dsa_switch *ds, int phy_addr, int phy_reg);
+
+/* RTL839x-specific */
+u32 rtl839x_hash(struct rtl838x_switch_priv *priv, u64 seed);
+irqreturn_t rtl839x_switch_irq(int irq, void *dev_id);
+void rtl8390_get_version(struct rtl838x_switch_priv *priv);
+void rtl839x_vlan_profile_dump(int index);
+int rtl83xx_dsa_phy_write(struct dsa_switch *ds, int phy_addr, int phy_reg, u16 val);
+
+#endif /* _NET_DSA_RTL83XX_H */
+
diff --git a/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/storm.c b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/storm.c
new file mode 100644
index 0000000000..de0af033f3
--- /dev/null
+++ b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/storm.c
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <asm/mach-rtl838x/mach-rtl83xx.h>
+#include "rtl83xx.h"
+
+
+static void rtl83xx_storm_enable(struct rtl838x_switch_priv *priv, int port, bool enable)
+{
+	// Enable Storm control for that port for UC, MC, and BC
+	if (enable)
+		sw_w32(0x7, RTL838X_STORM_CTRL_LB_CTRL(port));
+	else
+		sw_w32(0x0, RTL838X_STORM_CTRL_LB_CTRL(port));
+}
+
+void __init rtl83xx_storm_control_init(struct rtl838x_switch_priv *priv)
+{
+	int i;
+
+	pr_debug("Enabling Storm control\n");
+	// TICK_PERIOD_PPS
+	if (priv->id == 0x8380)
+		sw_w32_mask(0x3ff << 20, 434 << 20, RTL838X_SCHED_LB_TICK_TKN_CTRL_0);
+
+	// Set burst rate
+	sw_w32(0x00008000, RTL838X_STORM_CTRL_BURST_0); // UC
+	sw_w32(0x80008000, RTL838X_STORM_CTRL_BURST_1); // MC and BC
+
+	// Set burst Packets per Second to 32
+	sw_w32(0x00000020, RTL838X_STORM_CTRL_BURST_PPS_0); // UC
+	sw_w32(0x00200020, RTL838X_STORM_CTRL_BURST_PPS_1); // MC and BC
+
+	// Include IFG in storm control
+	sw_w32_mask(0, BIT(6), RTL838X_STORM_CTRL);
+	// Rate control is based on bytes/s (0 = packets)
+	sw_w32_mask(0, BIT(5), RTL838X_STORM_CTRL);
+	// Bandwidth control includes preamble and IFG (10 Bytes)
+	sw_w32_mask(0, 1, RTL838X_SCHED_CTRL);
+
+	// On SoCs except RTL8382M, set burst size of port egress
+	if (priv->id != 0x8382)
+		sw_w32_mask(0xffff, 0x800, RTL838X_SCHED_LB_THR);
+
+	/* Enable storm control on all ports with a PHY and limit rates,
+	 * for UC and MC for both known and unknown addresses */
+	for (i = 0; i < priv->cpu_port; i++) {
+		if (priv->ports[i].phy) {
+			sw_w32(BIT(18) | 0x8000, RTL838X_STORM_CTRL_PORT_UC(i));
+			sw_w32(BIT(18) | 0x8000, RTL838X_STORM_CTRL_PORT_MC(i));
+			sw_w32(0x000, RTL838X_STORM_CTRL_PORT_BC(i));
+			rtl83xx_storm_enable(priv, i, true);
+		}
+	}
+
+	// Attack prevention, enable all attack prevention measures
+	//sw_w32(0x1ffff, RTL838X_ATK_PRVNT_CTRL);
+	/* Attack prevention, drop (bit = 0) problematic packets on all ports.
+	 * Setting bit = 1 means: trap to CPU
+	 */
+	//sw_w32(0, RTL838X_ATK_PRVNT_ACT);
+	// Enable attack prevention on all ports
+	//sw_w32(0x0fffffff, RTL838X_ATK_PRVNT_PORT_EN);
+}
+
diff --git a/target/linux/realtek/files-5.4/drivers/net/ethernet/rtl838x_eth.c b/target/linux/realtek/files-5.4/drivers/net/ethernet/rtl838x_eth.c
new file mode 100644
index 0000000000..d53d5dec12
--- /dev/null
+++ b/target/linux/realtek/files-5.4/drivers/net/ethernet/rtl838x_eth.c
@@ -0,0 +1,1543 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * linux/drivers/net/ethernet/rtl838x_eth.c
+ * Copyright (C) 2020 B. Koblitz
+ */
+
+#include <linux/dma-mapping.h>
+#include <linux/etherdevice.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/of_net.h>
+#include <linux/of_mdio.h>
+#include <linux/module.h>
+#include <linux/phylink.h>
+#include <net/dsa.h>
+#include <net/switchdev.h>
+#include <asm/cacheflush.h>
+
+#include <asm/mach-rtl838x/mach-rtl83xx.h>
+#include "rtl838x_eth.h"
+
+extern struct rtl83xx_soc_info soc_info;
+
+/*
+ * Maximum number of RX rings is 8, assigned by switch based on
+ * packet/port priortity (not implemented)
+ * Maximum number of TX rings is 2 (only ring 0 used)
+ * RX ringlength needs to be at least 200, otherwise CPU and Switch
+ * may gridlock.
+ */
+#define RXRINGS		8
+#define RXRINGLEN	300
+#define TXRINGS		2
+#define TXRINGLEN	160
+#define NOTIFY_EVENTS	10
+#define NOTIFY_BLOCKS	10
+#define TX_EN		0x8
+#define RX_EN		0x4
+#define TX_DO		0x2
+#define WRAP		0x2
+
+#define RING_BUFFER	1600
+
+#define RTL838X_STORM_CTRL_PORT_BC_EXCEED	(0x470C)
+#define RTL838X_STORM_CTRL_PORT_MC_EXCEED	(0x4710)
+#define RTL838X_STORM_CTRL_PORT_UC_EXCEED	(0x4714)
+#define RTL838X_ATK_PRVNT_STS			(0x5B1C)
+
+struct p_hdr {
+	uint8_t		*buf;
+	uint16_t	reserved;
+	uint16_t	size;   /* buffer size */
+	uint16_t	offset;
+	uint16_t	len;    /* pkt len */
+	uint16_t	reserved2;
+	uint16_t	cpu_tag[5];
+} __packed __aligned(1);
+
+struct n_event {
+	uint32_t	type:2;
+	uint32_t	fidVid:12;
+	uint64_t	mac:48;
+	uint32_t	slp:6;
+	uint32_t	valid:1;
+	uint32_t	reserved:27;
+} __packed __aligned(1);
+
+struct ring_b {
+	uint32_t	rx_r[RXRINGS][RXRINGLEN];
+	uint32_t	tx_r[TXRINGS][TXRINGLEN];
+	struct	p_hdr	rx_header[RXRINGS][RXRINGLEN];
+	struct	p_hdr	tx_header[TXRINGS][TXRINGLEN];
+	uint32_t	c_rx[RXRINGS];
+	uint32_t	c_tx[TXRINGS];
+	uint8_t		rx_space[RXRINGS*RXRINGLEN*RING_BUFFER];
+	uint8_t		tx_space[TXRINGLEN*RING_BUFFER];
+};
+
+struct notify_block {
+	struct n_event	events[NOTIFY_EVENTS];
+};
+
+struct notify_b {
+	struct notify_block	blocks[NOTIFY_BLOCKS];
+	u32			reserved1[8];
+	u32			ring[NOTIFY_BLOCKS];
+	u32			reserved2[8];
+};
+
+inline void rtl838x_create_tx_header(struct p_hdr *h, int dest_port)
+{
+	if (dest_port > 0) {
+		h->cpu_tag[0] = 0x0400;
+		h->cpu_tag[1] = 0x0200;
+		h->cpu_tag[2] = 0x0000;
+		h->cpu_tag[3] = (1 << dest_port) >> 16;
+		h->cpu_tag[4] = (1 << dest_port) & 0xffff;
+	} else {
+		h->cpu_tag[0] = 0;
+		h->cpu_tag[1] = 0;
+		h->cpu_tag[2] = 0;
+		h->cpu_tag[3] = 0;
+		h->cpu_tag[4] = 0;
+	}
+}
+
+inline void rtl839x_create_tx_header(struct p_hdr *h, int dest_port)
+{
+	if (dest_port > 0) {
+		h->cpu_tag[0] = 0x0100;
+		h->cpu_tag[1] = ((1 << (dest_port - 32)) >> 16) | (1 << 21);
+		h->cpu_tag[2] = (1 << (dest_port - 32)) & 0xffff;
+		h->cpu_tag[3] = (1 << dest_port) >> 16;
+		h->cpu_tag[4] = (1 << dest_port) & 0xffff;
+	} else {
+		h->cpu_tag[0] = 0;
+		h->cpu_tag[1] = 0;
+		h->cpu_tag[2] = 0;
+		h->cpu_tag[3] = 0;
+		h->cpu_tag[4] = 0;
+	}
+}
+
+struct rtl838x_eth_priv {
+	struct net_device *netdev;
+	struct platform_device *pdev;
+	void		*membase;
+	spinlock_t	lock;
+	struct mii_bus	*mii_bus;
+	struct napi_struct napi;
+	struct phylink *phylink;
+	struct phylink_config phylink_config;
+	u16 id;
+	u16 family_id;
+	const struct rtl838x_reg *r;
+	u8 cpu_port;
+	u8 port_mask;
+	u32 lastEvent;
+};
+
+static const struct rtl838x_reg rtl838x_reg = {
+	.mac_port_ctrl = rtl838x_mac_port_ctrl,
+	.dma_if_intr_sts = RTL838X_DMA_IF_INTR_STS,
+	.dma_if_intr_msk = RTL838X_DMA_IF_INTR_MSK,
+	.dma_if_ctrl = RTL838X_DMA_IF_CTRL,
+	.mac_force_mode_ctrl = rtl838x_mac_force_mode_ctrl,
+	.dma_rx_base = rtl838x_dma_rx_base,
+	.dma_tx_base = rtl838x_dma_tx_base,
+	.dma_if_rx_ring_size = rtl838x_dma_if_rx_ring_size,
+	.dma_if_rx_ring_cntr = rtl838x_dma_if_rx_ring_cntr,
+	.dma_if_rx_cur = rtl838x_dma_if_rx_cur,
+	.rst_glb_ctrl = RTL838X_RST_GLB_CTRL_0,
+	.get_mac_link_sts = rtl838x_get_mac_link_sts,
+	.get_mac_link_dup_sts = rtl838x_get_mac_link_dup_sts,
+	.get_mac_link_spd_sts = rtl838x_get_mac_link_spd_sts,
+	.get_mac_rx_pause_sts = rtl838x_get_mac_rx_pause_sts,
+	.get_mac_tx_pause_sts = rtl838x_get_mac_tx_pause_sts,
+	.mac = RTL838X_MAC,
+	.l2_tbl_flush_ctrl = RTL838X_L2_TBL_FLUSH_CTRL,
+};
+
+static const struct rtl838x_reg rtl839x_reg = {
+	.mac_port_ctrl = rtl839x_mac_port_ctrl,
+	.dma_if_intr_sts = RTL839X_DMA_IF_INTR_STS,
+	.dma_if_intr_msk = RTL839X_DMA_IF_INTR_MSK,
+	.dma_if_ctrl = RTL839X_DMA_IF_CTRL,
+	.mac_force_mode_ctrl = rtl839x_mac_force_mode_ctrl,
+	.dma_rx_base = rtl839x_dma_rx_base,
+	.dma_tx_base = rtl839x_dma_tx_base,
+	.dma_if_rx_ring_size = rtl839x_dma_if_rx_ring_size,
+	.dma_if_rx_ring_cntr = rtl839x_dma_if_rx_ring_cntr,
+	.dma_if_rx_cur = rtl839x_dma_if_rx_cur,
+	.rst_glb_ctrl = RTL839X_RST_GLB_CTRL,
+	.get_mac_link_sts = rtl839x_get_mac_link_sts,
+	.get_mac_link_dup_sts = rtl839x_get_mac_link_dup_sts,
+	.get_mac_link_spd_sts = rtl839x_get_mac_link_spd_sts,
+	.get_mac_rx_pause_sts = rtl839x_get_mac_rx_pause_sts,
+	.get_mac_tx_pause_sts = rtl839x_get_mac_tx_pause_sts,
+	.mac = RTL839X_MAC,
+	.l2_tbl_flush_ctrl = RTL839X_L2_TBL_FLUSH_CTRL,
+};
+
+extern int rtl838x_phy_init(struct rtl838x_eth_priv *priv);
+extern int rtl838x_read_sds_phy(int phy_addr, int phy_reg);
+extern int rtl839x_read_sds_phy(int phy_addr, int phy_reg);
+extern int rtl839x_write_sds_phy(int phy_addr, int phy_reg, u16 v);
+
+/*
+ * Discard the RX ring-buffers, called as part of the net-ISR
+ * when the buffer runs over
+ * Caller needs to hold priv->lock
+ */
+static void rtl838x_rb_cleanup(struct rtl838x_eth_priv *priv)
+{
+	int r;
+	u32	*last;
+	struct p_hdr *h;
+	struct ring_b *ring = priv->membase;
+
+	for (r = 0; r < RXRINGS; r++) {
+		last = (u32 *)KSEG1ADDR(sw_r32(priv->r->dma_if_rx_cur(r)));
+		do {
+			if ((ring->rx_r[r][ring->c_rx[r]] & 0x1))
+				break;
+			h = &ring->rx_header[r][ring->c_rx[r]];
+			h->buf = (u8 *)KSEG1ADDR(ring->rx_space
+					+ r * ring->c_rx[r] * RING_BUFFER);
+			h->size = RING_BUFFER;
+			h->len = 0;
+			/* make sure the header is visible to the ASIC */
+			mb();
+
+			ring->rx_r[r][ring->c_rx[r]] = KSEG1ADDR(h) | 0x1
+				| (ring->c_rx[r] == (RXRINGLEN - 1) ? WRAP : 0x1);
+			ring->c_rx[r] = (ring->c_rx[r] + 1) % RXRINGLEN;
+		} while (&ring->rx_r[r][ring->c_rx[r]] != last);
+	}
+}
+
+struct fdb_update_work {
+	struct work_struct work;
+	struct net_device *ndev;
+	u64 macs[NOTIFY_EVENTS + 1];
+};
+
+void rtl838x_fdb_sync(struct work_struct *work)
+{
+       const struct fdb_update_work *uw =
+               container_of(work, struct fdb_update_work, work);
+       struct switchdev_notifier_fdb_info info;
+       u8 addr[ETH_ALEN];
+       int i = 0;
+       int action;
+
+       while (uw->macs[i]) {
+               action = (uw->macs[i] & (1ULL << 63)) ? SWITCHDEV_FDB_ADD_TO_BRIDGE
+                               : SWITCHDEV_FDB_DEL_TO_BRIDGE;
+               u64_to_ether_addr(uw->macs[i] & 0xffffffffffffULL, addr);
+               info.addr = &addr[0];
+               info.vid = 0;
+               info.offloaded = 1;
+               pr_debug("FDB entry %d: %llx, action %d\n", i, uw->macs[0], action);
+               call_switchdev_notifiers(action, uw->ndev, &info.info, NULL);
+               i++;
+       }
+       kfree(work);
+}
+
+static void rtl839x_l2_notification_handler(struct rtl838x_eth_priv *priv)
+{
+	struct notify_b *nb = priv->membase + sizeof(struct ring_b);
+	u32 e = priv->lastEvent;
+	struct n_event *event;
+	int i;
+	u64 mac;
+	struct fdb_update_work *w;
+
+	while (!(nb->ring[e] & 1)) {
+		w = kzalloc(sizeof(*w), GFP_ATOMIC);
+		if (!w) {
+			pr_err("Out of memory: %s", __func__);
+			return;
+		}
+		INIT_WORK(&w->work, rtl838x_fdb_sync);
+
+		for (i = 0; i < NOTIFY_EVENTS; i++) {
+			event = &nb->blocks[e].events[i];
+			if (!event->valid)
+				continue;
+			mac = event->mac;
+			if (event->type)
+				mac |= 1ULL << 63;
+			w->ndev = priv->netdev;
+			w->macs[i] = mac;
+		}
+
+		/* Hand the ring entry back to the switch */
+		nb->ring[e] = nb->ring[e] | 1;
+		e = (e + 1) % NOTIFY_BLOCKS;
+
+		w->macs[i] = 0ULL;
+		schedule_work(&w->work);
+	}
+	priv->lastEvent = e;
+}
+
+static irqreturn_t rtl838x_net_irq(int irq, void *dev_id)
+{
+	struct net_device *dev = dev_id;
+	struct rtl838x_eth_priv *priv = netdev_priv(dev);
+	u32 status = sw_r32(priv->r->dma_if_intr_sts);
+	bool triggered = false;
+	u32 atk = sw_r32(RTL838X_ATK_PRVNT_STS);
+	u32 storm_uc = sw_r32(RTL838X_STORM_CTRL_PORT_UC_EXCEED);
+	u32 storm_mc = sw_r32(RTL838X_STORM_CTRL_PORT_MC_EXCEED);
+	u32 storm_bc = sw_r32(RTL838X_STORM_CTRL_PORT_BC_EXCEED);
+
+	if (storm_uc || storm_mc || storm_bc) {
+
+		pr_warn("Storm control UC: %08x, MC: %08x, BC: %08x\n",
+			storm_uc, storm_mc, storm_bc);
+
+		sw_w32(storm_uc, RTL838X_STORM_CTRL_PORT_UC_EXCEED);
+		sw_w32(storm_mc, RTL838X_STORM_CTRL_PORT_MC_EXCEED);
+		sw_w32(storm_bc, RTL838X_STORM_CTRL_PORT_BC_EXCEED);
+
+		triggered = true;
+	}
+
+	if (atk) {
+		pr_debug("Attack prevention triggered: %08x\n", atk);
+		sw_w32(atk, RTL838X_ATK_PRVNT_STS);
+	}
+
+	spin_lock(&priv->lock);
+	/*  Ignore TX interrupt */
+	if ((status & 0xf0000)) {
+		/* Clear ISR */
+		sw_w32(0x000f0000, priv->r->dma_if_intr_sts);
+	}
+
+	/* RX interrupt */
+	if (status & 0x0ff00) {
+		/* Disable RX interrupt */
+		if (triggered)
+			pr_info("RX\n");
+		sw_w32_mask(0xff00, 0, priv->r->dma_if_intr_msk);
+		sw_w32(0x0000ff00, priv->r->dma_if_intr_sts);
+		napi_schedule(&priv->napi);
+	}
+
+	/* RX buffer overrun */
+	if (status & 0x000ff) {
+		pr_info("RX buffer overrun: status %x, mask: %x\n",
+			 status, sw_r32(priv->r->dma_if_intr_msk));
+		sw_w32(0x000000ff, priv->r->dma_if_intr_sts);
+		rtl838x_rb_cleanup(priv);
+	}
+
+	if (priv->family_id == RTL8390_FAMILY_ID && status & 0x00100000) {
+		sw_w32(0x00100000, priv->r->dma_if_intr_sts);
+		rtl839x_l2_notification_handler(priv);
+	}
+
+	if (priv->family_id == RTL8390_FAMILY_ID && status & 0x00200000) {
+		sw_w32(0x00200000, priv->r->dma_if_intr_sts);
+		rtl839x_l2_notification_handler(priv);
+	}
+
+	if (priv->family_id == RTL8390_FAMILY_ID && status & 0x00400000) {
+		sw_w32(0x00400000, priv->r->dma_if_intr_sts);
+		rtl839x_l2_notification_handler(priv);
+	}
+
+	spin_unlock(&priv->lock);
+	return IRQ_HANDLED;
+}
+
+static void rtl838x_hw_reset(struct rtl838x_eth_priv *priv)
+{
+	u32 int_saved, nbuf;
+
+	pr_info("RESETTING %x, CPU_PORT %d\n", priv->family_id, priv->cpu_port);
+	/* Stop TX/RX */
+	sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(priv->cpu_port));
+	mdelay(500);
+
+	if (priv->family_id == RTL8390_FAMILY_ID) {
+		/* Preserve L2 notification and NBUF settings */
+		int_saved = sw_r32(priv->r->dma_if_intr_msk);
+		nbuf = sw_r32(RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL);
+
+		/* Disable link change interrupt on RTL839x */
+		sw_w32(0, RTL839X_IMR_PORT_LINK_STS_CHG);
+		sw_w32(0, RTL839X_IMR_PORT_LINK_STS_CHG + 4);
+
+		sw_w32(0x00000000, priv->r->dma_if_intr_msk);
+		sw_w32(0xffffffff, priv->r->dma_if_intr_sts);
+	}
+
+	/* Reset NIC and Queue */
+	sw_w32(0x08, priv->r->rst_glb_ctrl);
+	if (priv->family_id == RTL8390_FAMILY_ID)
+		sw_w32(0xffffffff, RTL839X_DMA_IF_RX_RING_CNTR);
+	do { /* Reset NIC */
+		udelay(20);
+	} while (sw_r32(priv->r->rst_glb_ctrl) & 0x08);
+	do { /* Reset Queues */
+		udelay(20);
+	} while (sw_r32(priv->r->rst_glb_ctrl) & 0x04);
+	mdelay(100);
+
+	/* Re-enable link change interrupt */
+	if (priv->family_id == RTL8390_FAMILY_ID) {
+		sw_w32(0xffffffff, RTL839X_ISR_PORT_LINK_STS_CHG);
+		sw_w32(0xffffffff, RTL839X_ISR_PORT_LINK_STS_CHG + 4);
+		sw_w32(0xffffffff, RTL839X_IMR_PORT_LINK_STS_CHG);
+		sw_w32(0xffffffff, RTL839X_IMR_PORT_LINK_STS_CHG + 4);
+
+		/* Restore notification settings: on RTL838x these bits are null */
+		sw_w32_mask(7 << 20, int_saved & (7 << 20), priv->r->dma_if_intr_msk);
+		sw_w32(nbuf, RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL);
+	}
+
+	/* Restart TX/RX to CPU port */
+	sw_w32_mask(0x0, 0x3, priv->r->mac_port_ctrl(priv->cpu_port));
+
+	if (priv->family_id == RTL8380_FAMILY_ID) {
+		/* Set Speed, duplex, flow control
+		 * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL
+		 * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN
+		 * | MEDIA_SEL
+		 */
+		sw_w32(0x6192F, priv->r->mac_force_mode_ctrl(priv->cpu_port));
+		/* allow CRC errors on CPU-port */
+		sw_w32_mask(0, 0x8, priv->r->mac_port_ctrl(priv->cpu_port));
+	} else {
+		/* CPU port joins Lookup Miss Flooding Portmask */
+		sw_w32(0x28000, RTL839X_TBL_ACCESS_L2_CTRL);
+		sw_w32_mask(0, 0x80000000, RTL839X_TBL_ACCESS_L2_DATA(0));
+		sw_w32(0x38000, RTL839X_TBL_ACCESS_L2_CTRL);
+
+		/* Force CPU port link up */
+		sw_w32_mask(0, 3, priv->r->mac_force_mode_ctrl(priv->cpu_port));
+	}
+
+	/* Disable and clear interrupts */
+	sw_w32(0x00000000, priv->r->dma_if_intr_msk);
+	sw_w32(0xffffffff, priv->r->dma_if_intr_sts);
+}
+
+static void rtl838x_hw_ring_setup(struct rtl838x_eth_priv *priv)
+{
+	int i;
+	struct ring_b *ring = priv->membase;
+
+	for (i = 0; i < RXRINGS; i++)
+		sw_w32(KSEG1ADDR(&ring->rx_r[i]), priv->r->dma_rx_base(i));
+
+	for (i = 0; i < TXRINGS; i++)
+		sw_w32(KSEG1ADDR(&ring->tx_r[i]), priv->r->dma_tx_base(i));
+}
+
+static void rtl838x_hw_en_rxtx(struct rtl838x_eth_priv *priv)
+{
+	/* Disable Head of Line features for all RX rings */
+	sw_w32(0xffffffff, priv->r->dma_if_rx_ring_size(0));
+
+	/* Truncate RX buffer to 0x640 (1600) bytes, pad TX */
+	sw_w32(0x06400020, priv->r->dma_if_ctrl);
+
+	/* Enable RX done, RX overflow and TX done interrupts */
+	sw_w32(0xfffff, priv->r->dma_if_intr_msk);
+
+	/* Enable traffic, engine expects empty FCS field */
+	sw_w32_mask(0, RX_EN | TX_EN, priv->r->dma_if_ctrl);
+}
+
+static void rtl839x_hw_en_rxtx(struct rtl838x_eth_priv *priv)
+{
+	/* Setup CPU-Port: RX Buffer */
+	sw_w32(0x0000c808, priv->r->dma_if_ctrl);
+
+	/* Enable Notify, RX done, RX overflow and TX done interrupts */
+	sw_w32(0x007fffff, priv->r->dma_if_intr_msk); // Notify IRQ!
+
+	/* Enable traffic */
+	sw_w32_mask(0, RX_EN | TX_EN, priv->r->dma_if_ctrl);
+}
+
+static void rtl838x_setup_ring_buffer(struct ring_b *ring)
+{
+	int i, j;
+
+	struct p_hdr *h;
+
+	for (i = 0; i < RXRINGS; i++) {
+		for (j = 0; j < RXRINGLEN; j++) {
+			h = &ring->rx_header[i][j];
+			h->buf = (u8 *)KSEG1ADDR(ring->rx_space + i * j * RING_BUFFER);
+			h->reserved = 0;
+			h->size = RING_BUFFER;
+			h->offset = 0;
+			h->len = 0;
+			memset(&h->cpu_tag, 0, sizeof(uint16_t[5]));
+			/* All rings owned by switch, last one wraps */
+			ring->rx_r[i][j] = KSEG1ADDR(h) | 1 | (j == (RXRINGLEN - 1) ? WRAP : 0);
+		}
+		ring->c_rx[i] = 0;
+	}
+
+	for (i = 0; i < TXRINGS; i++) {
+		for (j = 0; j < TXRINGLEN; j++) {
+			h = &ring->tx_header[i][j];
+			h->buf = (u8 *)KSEG1ADDR(ring->tx_space + i * j * RING_BUFFER);
+			h->reserved = 0;
+			h->size = RING_BUFFER;
+			h->offset = 0;
+			h->len = 0;
+			memset(&h->cpu_tag, 0, sizeof(uint16_t[5]));
+			ring->tx_r[i][j] = KSEG1ADDR(&ring->tx_header[i][j]);
+		}
+		/* Last header is wrapping around */
+		ring->tx_r[i][j-1] |= WRAP;
+		ring->c_tx[i] = 0;
+	}
+}
+
+static void rtl839x_setup_notify_ring_buffer(struct rtl838x_eth_priv *priv)
+{
+	int i;
+	struct notify_b *b = priv->membase + sizeof(struct ring_b);
+
+	for (i = 0; i < NOTIFY_BLOCKS; i++)
+		b->ring[i] = KSEG1ADDR(&b->blocks[i]) | 1 | (i == (NOTIFY_BLOCKS - 1) ? WRAP : 0);
+
+	sw_w32((u32) b->ring, RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL);
+	sw_w32_mask(0x3ff << 2, 100 << 2, RTL839X_L2_NOTIFICATION_CTRL);
+
+	/* Setup notification events */
+	sw_w32_mask(0, 1 << 14, RTL839X_L2_CTRL_0); // RTL8390_L2_CTRL_0_FLUSH_NOTIFY_EN
+	sw_w32_mask(0, 1 << 12, RTL839X_L2_NOTIFICATION_CTRL); // SUSPEND_NOTIFICATION_EN
+
+	/* Enable Notification */
+	sw_w32_mask(0, 1 << 0, RTL839X_L2_NOTIFICATION_CTRL);
+	priv->lastEvent = 0;
+}
+
+static int rtl838x_eth_open(struct net_device *ndev)
+{
+	unsigned long flags;
+	struct rtl838x_eth_priv *priv = netdev_priv(ndev);
+	struct ring_b *ring = priv->membase;
+	int err;
+
+	pr_info("%s called: RX rings %d, TX rings %d\n", __func__, RXRINGS, TXRINGS);
+
+	spin_lock_irqsave(&priv->lock, flags);
+	rtl838x_hw_reset(priv);
+	rtl838x_setup_ring_buffer(ring);
+	if (priv->family_id == RTL8390_FAMILY_ID) {
+		rtl839x_setup_notify_ring_buffer(priv);
+		/* Make sure the ring structure is visible to the ASIC */
+		mb();
+		flush_cache_all();
+	}
+
+	rtl838x_hw_ring_setup(priv);
+	err = request_irq(ndev->irq, rtl838x_net_irq, IRQF_SHARED,
+			ndev->name, ndev);
+	if (err) {
+		netdev_err(ndev, "%s: could not acquire interrupt: %d\n",
+			   __func__, err);
+		return err;
+	}
+	phylink_start(priv->phylink);
+
+	napi_enable(&priv->napi);
+	netif_start_queue(ndev);
+
+	if (priv->family_id == RTL8380_FAMILY_ID) {
+		rtl838x_hw_en_rxtx(priv);
+		/* Trap IGMP traffic to CPU-Port */
+		sw_w32(0x3, RTL838X_SPCL_TRAP_IGMP_CTRL);
+		/* Flush learned FDB entries on link down of a port */
+		sw_w32_mask(0, 1 << 7, RTL838X_L2_CTRL_0);
+	} else {
+		rtl839x_hw_en_rxtx(priv);
+		sw_w32(0x3, RTL839X_SPCL_TRAP_IGMP_CTRL);
+		sw_w32_mask(0, 1 << 7, RTL839X_L2_CTRL_0);
+	}
+
+	spin_unlock_irqrestore(&priv->lock, flags);
+
+	return 0;
+}
+
+static void rtl838x_hw_stop(struct rtl838x_eth_priv *priv)
+{
+	u32 force_mac = priv->family_id == RTL8380_FAMILY_ID ? 0x6192D : 0x75;
+	u32 clear_irq = priv->family_id == RTL8380_FAMILY_ID ? 0x000fffff : 0x007fffff;
+	int i;
+
+	/* Block all ports */
+	if (priv->family_id == RTL8380_FAMILY_ID) {
+		sw_w32(0x03000000, RTL838X_TBL_ACCESS_DATA_0(0));
+		sw_w32(0x00000000, RTL838X_TBL_ACCESS_DATA_0(1));
+		sw_w32(1 << 15 | 2 << 12, RTL838X_TBL_ACCESS_CTRL_0);
+	}
+
+	/* Flush L2 address cache */
+	if (priv->family_id == RTL8380_FAMILY_ID) {
+		for (i = 0; i <= priv->cpu_port; i++) {
+			sw_w32(1 << 26 | 1 << 23 | i << 5, priv->r->l2_tbl_flush_ctrl);
+			do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & (1 << 26));
+		}
+	} else {
+		for (i = 0; i <= priv->cpu_port; i++) {
+			sw_w32(1 << 28 | 1 << 25 | i << 5, priv->r->l2_tbl_flush_ctrl);
+			do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & (1 << 28));
+		}
+	}
+
+	/* CPU-Port: Link down */
+	sw_w32(force_mac, priv->r->mac_force_mode_ctrl(priv->cpu_port));
+	mdelay(100);
+
+	/* Disable traffic */
+	sw_w32_mask(RX_EN | TX_EN, 0, priv->r->dma_if_ctrl);
+	mdelay(200); // Test, whether this is needed
+
+	/* Disable all TX/RX interrupts */
+	sw_w32(0x00000000, priv->r->dma_if_intr_msk);
+	sw_w32(clear_irq, priv->r->dma_if_intr_sts);
+
+	/* Disable TX/RX DMA */
+	sw_w32(0x00000000, priv->r->dma_if_ctrl);
+	mdelay(200);
+}
+
+static int rtl838x_eth_stop(struct net_device *ndev)
+{
+	unsigned long flags;
+	struct rtl838x_eth_priv *priv = netdev_priv(ndev);
+
+	pr_info("in %s\n", __func__);
+
+	spin_lock_irqsave(&priv->lock, flags);
+	phylink_stop(priv->phylink);
+	rtl838x_hw_stop(priv);
+	free_irq(ndev->irq, ndev);
+	napi_disable(&priv->napi);
+	netif_stop_queue(ndev);
+	spin_unlock_irqrestore(&priv->lock, flags);
+
+	return 0;
+}
+
+static void rtl839x_eth_set_multicast_list(struct net_device *ndev)
+{
+	if (!(ndev->flags & (IFF_PROMISC | IFF_ALLMULTI))) {
+		sw_w32(0x0, RTL839X_RMA_CTRL_0);
+		sw_w32(0x0, RTL839X_RMA_CTRL_1);
+		sw_w32(0x0, RTL839X_RMA_CTRL_2);
+		sw_w32(0x0, RTL839X_RMA_CTRL_3);
+	}
+	if (ndev->flags & IFF_ALLMULTI) {
+		sw_w32(0x7fffffff, RTL839X_RMA_CTRL_0);
+		sw_w32(0x7fffffff, RTL839X_RMA_CTRL_1);
+		sw_w32(0x7fffffff, RTL839X_RMA_CTRL_2);
+	}
+	if (ndev->flags & IFF_PROMISC) {
+		sw_w32(0x7fffffff, RTL839X_RMA_CTRL_0);
+		sw_w32(0x7fffffff, RTL839X_RMA_CTRL_1);
+		sw_w32(0x7fffffff, RTL839X_RMA_CTRL_2);
+		sw_w32(0x3ff, RTL839X_RMA_CTRL_3);
+	}
+}
+
+static void rtl838x_eth_set_multicast_list(struct net_device *ndev)
+{
+	struct rtl838x_eth_priv *priv = netdev_priv(ndev);
+
+	if (priv->family_id == RTL8390_FAMILY_ID)
+		return rtl839x_eth_set_multicast_list(ndev);
+
+	if (!(ndev->flags & (IFF_PROMISC | IFF_ALLMULTI))) {
+		sw_w32(0x0, RTL838X_RMA_CTRL_0);
+		sw_w32(0x0, RTL838X_RMA_CTRL_1);
+	}
+	if (ndev->flags & IFF_ALLMULTI)
+		sw_w32(0x1fffff, RTL838X_RMA_CTRL_0);
+	if (ndev->flags & IFF_PROMISC) {
+		sw_w32(0x1fffff, RTL838X_RMA_CTRL_0);
+		sw_w32(0x7fff, RTL838X_RMA_CTRL_1);
+	}
+}
+
+static void rtl838x_eth_tx_timeout(struct net_device *ndev)
+{
+	unsigned long flags;
+	struct rtl838x_eth_priv *priv = netdev_priv(ndev);
+
+	pr_info("in %s\n", __func__);
+	spin_lock_irqsave(&priv->lock, flags);
+	rtl838x_hw_stop(priv);
+	rtl838x_hw_ring_setup(priv);
+	rtl838x_hw_en_rxtx(priv);
+	netif_trans_update(ndev);
+	netif_start_queue(ndev);
+	spin_unlock_irqrestore(&priv->lock, flags);
+}
+
+static int rtl838x_eth_tx(struct sk_buff *skb, struct net_device *dev)
+{
+	int len, i;
+	struct rtl838x_eth_priv *priv = netdev_priv(dev);
+	struct ring_b *ring = priv->membase;
+	uint32_t val;
+	int ret;
+	unsigned long flags;
+	struct p_hdr *h;
+	int dest_port = -1;
+
+	spin_lock_irqsave(&priv->lock, flags);
+	len = skb->len;
+
+	/* Check for DSA tagging at the end of the buffer */
+	if (netdev_uses_dsa(dev) && skb->data[len-4] == 0x80 && skb->data[len-3] > 0
+			&& skb->data[len-3] < 28 &&  skb->data[len-2] == 0x10
+			&&  skb->data[len-1] == 0x00) {
+		/* Reuse tag space for CRC */
+		dest_port = skb->data[len-3];
+		len -= 4;
+	}
+	if (len < ETH_ZLEN)
+		len = ETH_ZLEN;
+
+	/* ASIC expects that packet includes CRC, so we extend by 4 bytes */
+	len += 4;
+
+	if (skb_padto(skb, len)) {
+		ret = NETDEV_TX_OK;
+		goto txdone;
+	}
+
+	/* We can send this packet if CPU owns the descriptor */
+	if (!(ring->tx_r[0][ring->c_tx[0]] & 0x1)) {
+		/* Set descriptor for tx */
+		h = &ring->tx_header[0][ring->c_tx[0]];
+
+		h->buf = (u8 *)KSEG1ADDR(ring->tx_space);
+		h->size = len;
+		h->len = len;
+
+		/* Create cpu_tag */
+		if (priv->family_id == RTL8380_FAMILY_ID)
+			rtl838x_create_tx_header(h, dest_port);
+		else
+			rtl839x_create_tx_header(h, dest_port);
+
+		/* Copy packet data to tx buffer */
+		memcpy((void *)KSEG1ADDR(h->buf), skb->data, len);
+		/* Make sure packet data is visible to ASIC */
+		mb(); /* wmb() probably works, too */
+
+		/* Hand over to switch */
+		ring->tx_r[0][ring->c_tx[0]] = ring->tx_r[0][ring->c_tx[0]] | 0x1;
+
+		/* BUG: before tx fetch, need to make sure right data is accessed
+		 * This might not be necessary on newer RTL839x, though.
+		 */
+		for (i = 0; i < 10; i++) {
+			val = sw_r32(priv->r->dma_if_ctrl);
+			if ((val & 0xc) == 0xc)
+				break;
+		}
+
+		/* Tell switch to send data */
+		sw_w32_mask(0, TX_DO, priv->r->dma_if_ctrl);
+
+		dev->stats.tx_packets++;
+		dev->stats.tx_bytes += len;
+		dev_kfree_skb(skb);
+		ring->c_tx[0] = (ring->c_tx[0] + 1) % TXRINGLEN;
+		ret = NETDEV_TX_OK;
+	} else {
+		dev_warn(&priv->pdev->dev, "Data is owned by switch\n");
+		ret = NETDEV_TX_BUSY;
+	}
+txdone:
+	spin_unlock_irqrestore(&priv->lock, flags);
+	return ret;
+}
+
+static int rtl838x_hw_receive(struct net_device *dev, int r, int budget)
+{
+	struct rtl838x_eth_priv *priv = netdev_priv(dev);
+	struct ring_b *ring = priv->membase;
+	struct sk_buff *skb;
+	unsigned long flags;
+	int i, len, work_done = 0;
+	u8 *data, *skb_data;
+	unsigned int val;
+	u32	*last;
+	struct p_hdr *h;
+	bool dsa = netdev_uses_dsa(dev);
+
+	spin_lock_irqsave(&priv->lock, flags);
+	last = (u32 *)KSEG1ADDR(sw_r32(priv->r->dma_if_rx_cur(r)));
+
+	if (&ring->rx_r[r][ring->c_rx[r]] == last) {
+		spin_unlock_irqrestore(&priv->lock, flags);
+		return 0;
+	}
+	do {
+		if ((ring->rx_r[r][ring->c_rx[r]] & 0x1)) {
+			netdev_warn(dev, "WARNING Ring contention: ring %x, last %x, current %x, cPTR %x, ISR %x\n", r, (uint32_t)last,
+				    (u32) &ring->rx_r[r][ring->c_rx[r]],
+				    ring->rx_r[r][ring->c_rx[r]],
+				sw_r32(priv->r->dma_if_intr_sts));
+			break;
+		}
+
+		h = &ring->rx_header[r][ring->c_rx[r]];
+		data = (u8 *)KSEG1ADDR(h->buf);
+		len = h->len;
+
+		if (!len)
+			break;
+		work_done++;
+
+		len -= 4; /* strip the CRC */
+		/* Add 4 bytes for cpu_tag */
+		if (dsa)
+			len += 4;
+
+		skb = alloc_skb(len + 4, GFP_KERNEL);
+		skb_reserve(skb, NET_IP_ALIGN);
+
+		if (likely(skb)) {
+			/* BUG: Prevent bug on RTL838x SoCs*/
+			if (priv->family_id == RTL8380_FAMILY_ID) {
+				sw_w32(0xffffffff, priv->r->dma_if_rx_ring_size(0));
+				for (i = 0; i < RXRINGS; i++) {
+					/* Update each ring cnt */
+					val = sw_r32(priv->r->dma_if_rx_ring_cntr(i));
+					sw_w32(val, priv->r->dma_if_rx_ring_cntr(i));
+				}
+			}
+
+			skb_data = skb_put(skb, len);
+			/* Make sure data is visible */
+			mb();
+			memcpy(skb->data, (u8 *)KSEG1ADDR(data), len);
+			/* Overwrite CRC with cpu_tag */
+			if (dsa) {
+				skb->data[len-4] = 0x80;
+				skb->data[len-3] = h->cpu_tag[0] & priv->port_mask;
+				skb->data[len-2] = 0x10;
+				skb->data[len-1] = 0x00;
+			}
+
+			skb->protocol = eth_type_trans(skb, dev);
+			dev->stats.rx_packets++;
+			dev->stats.rx_bytes += len;
+
+			netif_receive_skb(skb);
+		} else {
+			if (net_ratelimit())
+				dev_warn(&dev->dev, "low on memory - packet dropped\n");
+			dev->stats.rx_dropped++;
+		}
+
+		h->buf = (u8 *)KSEG1ADDR(ring->rx_space
+				+ r * ring->c_rx[r] * RING_BUFFER);
+		h->size = RING_BUFFER;
+		h->len = 0;
+		memset(&h->cpu_tag, 0, sizeof(uint16_t[5]));
+
+		ring->rx_r[r][ring->c_rx[r]]
+			= KSEG1ADDR(h) | 0x1 | (ring->c_rx[r] == (RXRINGLEN-1) ? WRAP : 0x1);
+		ring->c_rx[r] = (ring->c_rx[r] + 1) % RXRINGLEN;
+	} while (&ring->rx_r[r][ring->c_rx[r]] != last && work_done < budget);
+
+	spin_unlock_irqrestore(&priv->lock, flags);
+	return work_done;
+}
+
+static int rtl838x_poll_rx(struct napi_struct *napi, int budget)
+{
+	struct rtl838x_eth_priv *priv = container_of(napi, struct rtl838x_eth_priv, napi);
+	int work_done = 0, r = 0;
+
+	while (work_done < budget && r < RXRINGS) {
+		work_done += rtl838x_hw_receive(priv->netdev, r, budget - work_done);
+		r++;
+	}
+
+	if (work_done < budget) {
+		napi_complete_done(napi, work_done);
+		/* Enable RX interrupt */
+		sw_w32_mask(0, 0xfffff, priv->r->dma_if_intr_msk);
+	}
+	return work_done;
+}
+
+
+static void rtl838x_validate(struct phylink_config *config,
+			 unsigned long *supported,
+			 struct phylink_link_state *state)
+{
+	__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
+
+	pr_info("In %s\n", __func__);
+
+	if (!phy_interface_mode_is_rgmii(state->interface) &&
+	    state->interface != PHY_INTERFACE_MODE_1000BASEX &&
+	    state->interface != PHY_INTERFACE_MODE_MII &&
+	    state->interface != PHY_INTERFACE_MODE_REVMII &&
+	    state->interface != PHY_INTERFACE_MODE_GMII &&
+	    state->interface != PHY_INTERFACE_MODE_QSGMII &&
+	    state->interface != PHY_INTERFACE_MODE_INTERNAL &&
+	    state->interface != PHY_INTERFACE_MODE_SGMII) {
+		bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
+		pr_err("Unsupported interface: %d\n", state->interface);
+		return;
+	}
+
+	/* Allow all the expected bits */
+	phylink_set(mask, Autoneg);
+	phylink_set_port_modes(mask);
+	phylink_set(mask, Pause);
+	phylink_set(mask, Asym_Pause);
+
+	/* With the exclusion of MII and Reverse MII, we support Gigabit,
+	 * including Half duplex
+	 */
+	if (state->interface != PHY_INTERFACE_MODE_MII &&
+	    state->interface != PHY_INTERFACE_MODE_REVMII) {
+		phylink_set(mask, 1000baseT_Full);
+		phylink_set(mask, 1000baseT_Half);
+	}
+
+	phylink_set(mask, 10baseT_Half);
+	phylink_set(mask, 10baseT_Full);
+	phylink_set(mask, 100baseT_Half);
+	phylink_set(mask, 100baseT_Full);
+
+	bitmap_and(supported, supported, mask,
+		   __ETHTOOL_LINK_MODE_MASK_NBITS);
+	bitmap_and(state->advertising, state->advertising, mask,
+		   __ETHTOOL_LINK_MODE_MASK_NBITS);
+}
+
+
+static void rtl838x_mac_config(struct phylink_config *config,
+			       unsigned int mode,
+			       const struct phylink_link_state *state)
+{
+	/* This is only being called for the master device,
+	 * i.e. the CPU-Port. We don't need to do anything.
+	 */
+
+	pr_info("In %s, mode %x\n", __func__, mode);
+}
+
+static void rtl838x_mac_an_restart(struct phylink_config *config)
+{
+	struct net_device *dev = container_of(config->dev, struct net_device, dev);
+	struct rtl838x_eth_priv *priv = netdev_priv(dev);
+
+	/* This works only on RTL838x chips */
+	if (priv->family_id != RTL8380_FAMILY_ID)
+		return;
+
+	pr_info("In %s\n", __func__);
+	/* Restart by disabling and re-enabling link */
+	sw_w32(0x6192D, priv->r->mac_force_mode_ctrl(priv->cpu_port));
+	mdelay(20);
+	sw_w32(0x6192F, priv->r->mac_force_mode_ctrl(priv->cpu_port));
+}
+
+static int rtl838x_mac_pcs_get_state(struct phylink_config *config,
+				  struct phylink_link_state *state)
+{
+	u32 speed;
+	struct net_device *dev = container_of(config->dev, struct net_device, dev);
+	struct rtl838x_eth_priv *priv = netdev_priv(dev);
+	int port = priv->cpu_port;
+
+	pr_info("In %s\n", __func__);
+
+	state->link = priv->r->get_mac_link_sts(port) ? 1 : 0;
+	state->duplex = priv->r->get_mac_link_dup_sts(port) ? 1 : 0;
+
+	speed = priv->r->get_mac_link_spd_sts(port);
+	switch (speed) {
+	case 0:
+		state->speed = SPEED_10;
+		break;
+	case 1:
+		state->speed = SPEED_100;
+		break;
+		state->speed = SPEED_1000;
+		break;
+	default:
+		state->speed = SPEED_UNKNOWN;
+		break;
+	}
+
+	state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
+	if (priv->r->get_mac_rx_pause_sts(port))
+		state->pause |= MLO_PAUSE_RX;
+	if (priv->r->get_mac_tx_pause_sts(port))
+		state->pause |= MLO_PAUSE_TX;
+
+	return 1;
+}
+
+static void rtl838x_mac_link_down(struct phylink_config *config,
+				  unsigned int mode,
+				  phy_interface_t interface)
+{
+	struct net_device *dev = container_of(config->dev, struct net_device, dev);
+	struct rtl838x_eth_priv *priv = netdev_priv(dev);
+
+	pr_info("In %s\n", __func__);
+	/* Stop TX/RX to port */
+	sw_w32_mask(0x03, 0, priv->r->mac_port_ctrl(priv->cpu_port));
+}
+
+static void rtl838x_mac_link_up(struct phylink_config *config, unsigned int mode,
+			    phy_interface_t interface,
+			    struct phy_device *phy)
+{
+	struct net_device *dev = container_of(config->dev, struct net_device, dev);
+	struct rtl838x_eth_priv *priv = netdev_priv(dev);
+
+	pr_info("In %s\n", __func__);
+	/* Restart TX/RX to port */
+	sw_w32_mask(0, 0x03, priv->r->mac_port_ctrl(priv->cpu_port));
+}
+
+static void rtl838x_set_mac_hw(struct net_device *dev, u8 *mac)
+{
+	struct rtl838x_eth_priv *priv = netdev_priv(dev);
+	unsigned long flags;
+
+	spin_lock_irqsave(&priv->lock, flags);
+	pr_info("In %s\n", __func__);
+	sw_w32((mac[0] << 8) | mac[1], priv->r->mac);
+	sw_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5], priv->r->mac + 4);
+
+	if (priv->family_id == RTL8380_FAMILY_ID) {
+		/* 2 more registers, ALE/MAC block */
+		sw_w32((mac[0] << 8) | mac[1], RTL838X_MAC_ALE);
+		sw_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
+		       (RTL838X_MAC_ALE + 4));
+
+		sw_w32((mac[0] << 8) | mac[1], RTL838X_MAC2);
+		sw_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
+		       RTL838X_MAC2 + 4);
+	}
+	spin_unlock_irqrestore(&priv->lock, flags);
+}
+
+static int rtl838x_set_mac_address(struct net_device *dev, void *p)
+{
+	struct rtl838x_eth_priv *priv = netdev_priv(dev);
+	const struct sockaddr *addr = p;
+	u8 *mac = (u8 *) (addr->sa_data);
+
+	if (!is_valid_ether_addr(addr->sa_data))
+		return -EADDRNOTAVAIL;
+
+	memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
+	rtl838x_set_mac_hw(dev, mac);
+
+	pr_info("Using MAC %08x%08x\n", sw_r32(priv->r->mac), sw_r32(priv->r->mac + 4));
+	return 0;
+}
+
+static int rtl8390_init_mac(struct rtl838x_eth_priv *priv)
+{
+	// We will need to set-up EEE and the egress-rate limitation
+	return 0;
+}
+
+static int rtl8380_init_mac(struct rtl838x_eth_priv *priv)
+{
+	int i;
+
+	if (priv->family_id == 0x8390)
+		return rtl8390_init_mac(priv);
+
+	pr_info("%s\n", __func__);
+	/* fix timer for EEE */
+	sw_w32(0x5001411, RTL838X_EEE_TX_TIMER_GIGA_CTRL);
+	sw_w32(0x5001417, RTL838X_EEE_TX_TIMER_GELITE_CTRL);
+
+	/* Init VLAN */
+	if (priv->id == 0x8382) {
+		for (i = 0; i <= 28; i++)
+			sw_w32(0, 0xd57c + i * 0x80);
+	}
+	if (priv->id == 0x8380) {
+		for (i = 8; i <= 28; i++)
+			sw_w32(0, 0xd57c + i * 0x80);
+	}
+	return 0;
+}
+
+static int rtl838x_get_link_ksettings(struct net_device *ndev,
+				      struct ethtool_link_ksettings *cmd)
+{
+	struct rtl838x_eth_priv *priv = netdev_priv(ndev);
+
+	pr_info("%s called\n", __func__);
+	return phylink_ethtool_ksettings_get(priv->phylink, cmd);
+}
+
+static int rtl838x_set_link_ksettings(struct net_device *ndev,
+				      const struct ethtool_link_ksettings *cmd)
+{
+	struct rtl838x_eth_priv *priv = netdev_priv(ndev);
+
+	pr_info("%s called\n", __func__);
+	return phylink_ethtool_ksettings_set(priv->phylink, cmd);
+}
+
+int rtl839x_read_sds_phy(int phy_addr, int phy_reg)
+{
+	int offset = 0;
+	int reg;
+	u32 val;
+
+	if (phy_addr == 49)
+		offset = 0x100;
+
+	/* For the RTL8393 internal SerDes, we simulate a PHY ID in registers 2/3
+	 * which would otherwise read as 0
+	 */
+	if (soc_info.id == 0x8393) {
+		if (phy_reg == 2)
+			return 0x1c;
+		if (phy_reg == 3)
+			return 0x8393;
+	}
+
+	reg = (phy_reg << 1) & 0xfc;
+	val = sw_r32(RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg);
+
+	if (phy_reg & 1)
+		val = (val >> 16) & 0xffff;
+	else
+		val &= 0xffff;
+	return val;
+}
+
+int rtl838x_read_sds_phy(int phy_addr, int phy_reg)
+{
+	int offset = 0;
+	u32 val;
+
+	if (phy_addr == 26)
+		offset = 0x100;
+	val = sw_r32(MAPLE_SDS4_FIB_REG0r + offset + (phy_reg << 2)) & 0xffff;
+
+	return val;
+}
+
+int rtl839x_write_sds_phy(int phy_addr, int phy_reg, u16 v)
+{
+	int offset = 0;
+	int reg;
+	u32 val;
+
+	if (phy_addr == 49)
+		offset = 0x100;
+
+	reg = (phy_reg << 1) & 0xfc;
+	val = v;
+	if (phy_reg & 1) {
+		val = val << 16;
+		sw_w32_mask(0xffff0000, val,
+			    RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg);
+	} else {
+		sw_w32_mask(0xffff, val,
+			    RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg);
+	}
+
+	return 0;
+}
+
+static int rtl838x_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
+{
+	u32 val;
+	int err;
+	struct rtl838x_eth_priv *priv = bus->priv;
+
+	if (mii_id >= 24 && mii_id <= 27 && priv->id == 0x8380)
+		return rtl838x_read_sds_phy(mii_id, regnum);
+	err = rtl838x_read_phy(mii_id, 0, regnum, &val);
+	if (err)
+		return err;
+	return val;
+}
+
+static int rtl839x_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
+{
+	u32 val;
+	int err;
+	struct rtl838x_eth_priv *priv = bus->priv;
+
+	if (mii_id >= 48 && mii_id <= 49 && priv->id == 0x8393)
+		return rtl839x_read_sds_phy(mii_id, regnum);
+
+	err = rtl839x_read_phy(mii_id, 0, regnum, &val);
+	if (err)
+		return err;
+	return val;
+}
+
+static int rtl838x_mdio_write(struct mii_bus *bus, int mii_id,
+			      int regnum, u16 value)
+{
+	u32 offset = 0;
+	struct rtl838x_eth_priv *priv = bus->priv;
+
+	if (mii_id >= 24 && mii_id <= 27 && priv->id == 0x8380) {
+		if (mii_id == 26)
+			offset = 0x100;
+		sw_w32(value, MAPLE_SDS4_FIB_REG0r + offset + (regnum << 2));
+		return 0;
+	}
+	return rtl838x_write_phy(mii_id, 0, regnum, value);
+}
+
+static int rtl839x_mdio_write(struct mii_bus *bus, int mii_id,
+			      int regnum, u16 value)
+{
+	struct rtl838x_eth_priv *priv = bus->priv;
+
+	if (mii_id >= 48 && mii_id <= 49 && priv->id == 0x8393)
+		return rtl839x_write_sds_phy(mii_id, regnum, value);
+
+	return rtl839x_write_phy(mii_id, 0, regnum, value);
+}
+
+static int rtl838x_mdio_reset(struct mii_bus *bus)
+{
+	pr_info("%s called\n", __func__);
+	/* Disable MAC polling the PHY so that we can start configuration */
+	sw_w32(0x00000000, RTL838X_SMI_POLL_CTRL);
+
+	/* Enable PHY control via SoC */
+	sw_w32_mask(0, 1 << 15, RTL838X_SMI_GLB_CTRL);
+
+	// Probably should reset all PHYs here...
+	return 0;
+}
+
+static int rtl839x_mdio_reset(struct mii_bus *bus)
+{
+	return 0;
+
+	pr_info("%s called\n", __func__);
+	/* BUG: The following does not work, but should! */
+	/* Disable MAC polling the PHY so that we can start configuration */
+	sw_w32(0x00000000, RTL839X_SMI_PORT_POLLING_CTRL);
+	sw_w32(0x00000000, RTL839X_SMI_PORT_POLLING_CTRL + 4);
+	/* Disable PHY polling via SoC */
+	sw_w32_mask(1 << 7, 0, RTL839X_SMI_GLB_CTRL);
+
+	// Probably should reset all PHYs here...
+	return 0;
+}
+
+
+static int rtl838x_mdio_init(struct rtl838x_eth_priv *priv)
+{
+	struct device_node *mii_np;
+	int ret;
+
+	pr_info("%s called\n", __func__);
+	mii_np = of_get_child_by_name(priv->pdev->dev.of_node, "mdio-bus");
+
+	if (!mii_np) {
+		dev_err(&priv->pdev->dev, "no %s child node found", "mdio-bus");
+		return -ENODEV;
+	}
+
+	if (!of_device_is_available(mii_np)) {
+		ret = -ENODEV;
+		goto err_put_node;
+	}
+
+	priv->mii_bus = devm_mdiobus_alloc(&priv->pdev->dev);
+	if (!priv->mii_bus) {
+		ret = -ENOMEM;
+		goto err_put_node;
+	}
+
+	if (priv->family_id == RTL8380_FAMILY_ID) {
+		priv->mii_bus->name = "rtl838x-eth-mdio";
+		priv->mii_bus->read = rtl838x_mdio_read;
+		priv->mii_bus->write = rtl838x_mdio_write;
+		priv->mii_bus->reset = rtl838x_mdio_reset;
+	} else {
+		priv->mii_bus->name = "rtl839x-eth-mdio";
+		priv->mii_bus->read = rtl839x_mdio_read;
+		priv->mii_bus->write = rtl839x_mdio_write;
+		priv->mii_bus->reset = rtl839x_mdio_reset;
+	}
+	priv->mii_bus->priv = priv;
+	priv->mii_bus->parent = &priv->pdev->dev;
+
+	snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np);
+	ret = of_mdiobus_register(priv->mii_bus, mii_np);
+
+err_put_node:
+	of_node_put(mii_np);
+	return ret;
+}
+
+static int rtl838x_mdio_remove(struct rtl838x_eth_priv *priv)
+{
+	pr_info("%s called\n", __func__);
+	if (!priv->mii_bus)
+		return 0;
+
+	mdiobus_unregister(priv->mii_bus);
+	mdiobus_free(priv->mii_bus);
+
+	return 0;
+}
+
+static const struct net_device_ops rtl838x_eth_netdev_ops = {
+	.ndo_open = rtl838x_eth_open,
+	.ndo_stop = rtl838x_eth_stop,
+	.ndo_start_xmit = rtl838x_eth_tx,
+	.ndo_set_mac_address = rtl838x_set_mac_address,
+	.ndo_validate_addr = eth_validate_addr,
+	.ndo_set_rx_mode = rtl838x_eth_set_multicast_list,
+	.ndo_tx_timeout = rtl838x_eth_tx_timeout,
+};
+
+static const struct phylink_mac_ops rtl838x_phylink_ops = {
+	.validate = rtl838x_validate,
+	.mac_link_state = rtl838x_mac_pcs_get_state,
+	.mac_an_restart = rtl838x_mac_an_restart,
+	.mac_config = rtl838x_mac_config,
+	.mac_link_down = rtl838x_mac_link_down,
+	.mac_link_up = rtl838x_mac_link_up,
+};
+
+static const struct ethtool_ops rtl838x_ethtool_ops = {
+	.get_link_ksettings     = rtl838x_get_link_ksettings,
+	.set_link_ksettings     = rtl838x_set_link_ksettings,
+};
+
+static int __init rtl838x_eth_probe(struct platform_device *pdev)
+{
+	struct net_device *dev;
+	struct device_node *dn = pdev->dev.of_node;
+	struct rtl838x_eth_priv *priv;
+	struct resource *res, *mem;
+	const void *mac;
+	phy_interface_t phy_mode;
+	struct phylink *phylink;
+	int err = 0;
+
+	pr_info("Probing RTL838X eth device pdev: %x, dev: %x\n",
+		(u32)pdev, (u32)(&(pdev->dev)));
+
+	if (!dn) {
+		dev_err(&pdev->dev, "No DT found\n");
+		return -EINVAL;
+	}
+
+	dev = alloc_etherdev(sizeof(struct rtl838x_eth_priv));
+	if (!dev) {
+		err = -ENOMEM;
+		goto err_free;
+	}
+	SET_NETDEV_DEV(dev, &pdev->dev);
+	priv = netdev_priv(dev);
+
+	/* obtain buffer memory space */
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (res) {
+		mem = devm_request_mem_region(&pdev->dev, res->start,
+			resource_size(res), res->name);
+		if (!mem) {
+			dev_err(&pdev->dev, "cannot request memory space\n");
+			err = -ENXIO;
+			goto err_free;
+		}
+
+		dev->mem_start = mem->start;
+		dev->mem_end   = mem->end;
+	} else {
+		dev_err(&pdev->dev, "cannot request IO resource\n");
+		err = -ENXIO;
+		goto err_free;
+	}
+
+	/* Allocate buffer memory */
+	priv->membase = dmam_alloc_coherent(&pdev->dev,
+				sizeof(struct ring_b) + sizeof(struct notify_b),
+				(void *)&dev->mem_start, GFP_KERNEL);
+	if (!priv->membase) {
+		dev_err(&pdev->dev, "cannot allocate DMA buffer\n");
+		err = -ENOMEM;
+		goto err_free;
+	}
+
+	spin_lock_init(&priv->lock);
+
+	/* obtain device IRQ number */
+	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+	if (!res) {
+		dev_err(&pdev->dev, "cannot obtain IRQ, using default 24\n");
+		dev->irq = 24;
+	} else {
+		dev->irq = res->start;
+	}
+	dev->ethtool_ops = &rtl838x_ethtool_ops;
+
+	priv->id = soc_info.id;
+	priv->family_id = soc_info.family;
+	if (priv->id) {
+		pr_info("Found SoC ID: %4x: %s, family %x\n",
+			priv->id, soc_info.name, priv->family_id);
+	} else {
+		pr_err("Unknown chip id (%04x)\n", priv->id);
+		return -ENODEV;
+	}
+
+	if (priv->family_id == 0x8390) {
+		priv->cpu_port = RTL839X_CPU_PORT;
+		priv->r = &rtl839x_reg;
+		priv->port_mask = 0x3f;
+	} else {
+		priv->cpu_port = RTL838X_CPU_PORT;
+		priv->r = &rtl838x_reg;
+		priv->port_mask = 0x1f;
+	}
+
+	rtl8380_init_mac(priv);
+
+	/* try to get mac address in the following order:
+	 * 1) from device tree data
+	 * 2) from internal registers set by bootloader
+	 */
+	mac = of_get_mac_address(pdev->dev.of_node);
+	if (!IS_ERR(mac)) {
+		memcpy(dev->dev_addr, mac, ETH_ALEN);
+		rtl838x_set_mac_hw(dev, (u8 *)mac);
+	} else {
+		dev->dev_addr[0] = (sw_r32(priv->r->mac) >> 8) & 0xff;
+		dev->dev_addr[1] = sw_r32(priv->r->mac) & 0xff;
+		dev->dev_addr[2] = (sw_r32(priv->r->mac + 4) >> 24) & 0xff;
+		dev->dev_addr[3] = (sw_r32(priv->r->mac + 4) >> 16) & 0xff;
+		dev->dev_addr[4] = (sw_r32(priv->r->mac + 4) >> 8) & 0xff;
+		dev->dev_addr[5] = sw_r32(priv->r->mac + 4) & 0xff;
+	}
+	/* if the address is invalid, use a random value */
+	if (!is_valid_ether_addr(dev->dev_addr)) {
+		struct sockaddr sa = { AF_UNSPEC };
+
+		netdev_warn(dev, "Invalid MAC address, using random\n");
+		eth_hw_addr_random(dev);
+		memcpy(sa.sa_data, dev->dev_addr, ETH_ALEN);
+		if (rtl838x_set_mac_address(dev, &sa))
+			netdev_warn(dev, "Failed to set MAC address.\n");
+	}
+	pr_info("Using MAC %08x%08x\n", sw_r32(priv->r->mac),
+					sw_r32(priv->r->mac + 4));
+	strcpy(dev->name, "eth%d");
+	dev->netdev_ops = &rtl838x_eth_netdev_ops;
+	priv->pdev = pdev;
+	priv->netdev = dev;
+
+	err = rtl838x_mdio_init(priv);
+	if (err)
+		goto err_free;
+
+	err = register_netdev(dev);
+	if (err)
+		goto err_free;
+
+	netif_napi_add(dev, &priv->napi, rtl838x_poll_rx, 64);
+	platform_set_drvdata(pdev, dev);
+
+	phy_mode = of_get_phy_mode(dn);
+	if (phy_mode < 0) {
+		dev_err(&pdev->dev, "incorrect phy-mode\n");
+		err = -EINVAL;
+		goto err_free;
+	}
+	priv->phylink_config.dev = &dev->dev;
+	priv->phylink_config.type = PHYLINK_NETDEV;
+
+	phylink = phylink_create(&priv->phylink_config, pdev->dev.fwnode,
+				 phy_mode, &rtl838x_phylink_ops);
+	if (IS_ERR(phylink)) {
+		err = PTR_ERR(phylink);
+		goto err_free;
+	}
+	priv->phylink = phylink;
+
+	return 0;
+
+err_free:
+	pr_err("Error setting up netdev, freeing it again.\n");
+	free_netdev(dev);
+	return err;
+}
+
+static int rtl838x_eth_remove(struct platform_device *pdev)
+{
+	struct net_device *dev = platform_get_drvdata(pdev);
+	struct rtl838x_eth_priv *priv = netdev_priv(dev);
+
+	if (dev) {
+		pr_info("Removing platform driver for rtl838x-eth\n");
+		rtl838x_mdio_remove(priv);
+		rtl838x_hw_stop(priv);
+		netif_stop_queue(dev);
+		netif_napi_del(&priv->napi);
+		unregister_netdev(dev);
+		free_netdev(dev);
+	}
+	return 0;
+}
+
+static const struct of_device_id rtl838x_eth_of_ids[] = {
+	{ .compatible = "realtek,rtl838x-eth"},
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, rtl838x_eth_of_ids);
+
+static struct platform_driver rtl838x_eth_driver = {
+	.probe = rtl838x_eth_probe,
+	.remove = rtl838x_eth_remove,
+	.driver = {
+		.name = "rtl838x-eth",
+		.pm = NULL,
+		.of_match_table = rtl838x_eth_of_ids,
+	},
+};
+
+module_platform_driver(rtl838x_eth_driver);
+
+MODULE_AUTHOR("B. Koblitz");
+MODULE_DESCRIPTION("RTL838X SoC Ethernet Driver");
+MODULE_LICENSE("GPL");
diff --git a/target/linux/realtek/files-5.4/drivers/net/ethernet/rtl838x_eth.h b/target/linux/realtek/files-5.4/drivers/net/ethernet/rtl838x_eth.h
new file mode 100644
index 0000000000..4366e6b64f
--- /dev/null
+++ b/target/linux/realtek/files-5.4/drivers/net/ethernet/rtl838x_eth.h
@@ -0,0 +1,279 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _RTL838X_ETH_H
+#define _RTL838X_ETH_H
+
+/*
+ * Register definition
+ */
+
+#define RTL838X_CPU_PORT			28
+#define RTL839X_CPU_PORT			52
+
+#define RTL838X_MAC_PORT_CTRL			(0xd560)
+#define RTL839X_MAC_PORT_CTRL			(0x8004)
+#define RTL838X_DMA_IF_INTR_STS			(0x9f54)
+#define RTL839X_DMA_IF_INTR_STS			(0x7868)
+#define RTL838X_DMA_IF_INTR_MSK			(0x9f50)
+#define RTL839X_DMA_IF_INTR_MSK			(0x7864)
+#define RTL838X_DMA_IF_CTRL			(0x9f58)
+#define RTL839X_DMA_IF_CTRL			(0x786c)
+#define RTL838X_RST_GLB_CTRL_0			(0x003c)
+#define RTL838X_MAC_FORCE_MODE_CTRL		(0xa104)
+#define RTL839X_MAC_FORCE_MODE_CTRL		(0x02bc)
+
+/* MAC address settings */
+#define RTL838X_MAC				(0xa9ec)
+#define RTL839X_MAC				(0x02b4)
+#define RTL838X_MAC_ALE				(0x6b04)
+#define RTL838X_MAC2				(0xa320)
+
+#define RTL838X_DMA_RX_BASE			(0x9f00)
+#define RTL839X_DMA_RX_BASE			(0x780c)
+#define RTL838X_DMA_TX_BASE			(0x9f40)
+#define RTL839X_DMA_TX_BASE			(0x784c)
+#define RTL838X_DMA_IF_RX_RING_SIZE		(0xB7E4)
+#define RTL839X_DMA_IF_RX_RING_SIZE		(0x6038)
+#define RTL838X_DMA_IF_RX_RING_CNTR		(0xB7E8)
+#define RTL839X_DMA_IF_RX_RING_CNTR		(0x603c)
+#define RTL838X_DMA_IF_RX_CUR			(0x9F20)
+#define RTL839X_DMA_IF_RX_CUR			(0x782c)
+
+#define RTL838X_DMY_REG31			(0x3b28)
+#define RTL838X_SDS_MODE_SEL			(0x0028)
+#define RTL838X_SDS_CFG_REG			(0x0034)
+#define RTL838X_INT_MODE_CTRL			(0x005c)
+#define RTL838X_CHIP_INFO			(0x00d8)
+#define RTL838X_SDS4_REG28			(0xef80)
+#define RTL838X_SDS4_DUMMY0			(0xef8c)
+#define RTL838X_SDS5_EXT_REG6			(0xf18c)
+#define RTL838X_PORT_ISO_CTRL(port)		(0x4100 + ((port) << 2))
+#define RTL838X_STAT_PORT_STD_MIB(port)		(0x1200 + (((port) << 8)))
+#define RTL838X_STAT_RST			(0x3100)
+#define RTL838X_STAT_CTRL			(0x3108)
+
+/* Registers of the internal Serdes of the 8380 */
+#define MAPLE_SDS4_REG0r			RTL838X_SDS4_REG28
+#define MAPLE_SDS5_REG0r			(RTL838X_SDS4_REG28 + 0x100)
+#define MAPLE_SDS4_REG3r			RTL838X_SDS4_DUMMY0
+#define MAPLE_SDS5_REG3r			(RTL838X_SDS4_REG28 + 0x100)
+#define MAPLE_SDS4_FIB_REG0r			(RTL838X_SDS4_REG28 + 0x880)
+#define MAPLE_SDS5_FIB_REG0r			(RTL838X_SDS4_REG28 + 0x980)
+
+/* VLAN registers */
+#define RTL838X_VLAN_PROFILE(idx)		(0x3A88 + ((idx) << 2))
+#define RTL838X_VLAN_PORT_EGR_FLTR		(0x3A84)
+#define RTL838X_VLAN_PORT_PB_VLAN(port)		(0x3C00 + ((port) << 2))
+#define RTL838X_VLAN_PORT_IGR_FLTR_0		(0x3A7C)
+#define RTL838X_VLAN_PORT_IGR_FLTR_1		(0x3A7C + 4)
+#define RTL838X_TBL_ACCESS_CTRL_0		(0x6914)
+#define RTL838X_TBL_ACCESS_DATA_0(idx)		(0x6918 + ((idx) << 2))
+#define RTL838X_TBL_ACCESS_CTRL_1		(0xA4C8)
+#define RTL838X_TBL_ACCESS_DATA_1(idx)		(0xA4CC + ((idx) << 2))
+#define RTL839X_TBL_ACCESS_L2_CTRL		(0x1180)
+#define RTL839X_TBL_ACCESS_L2_DATA(idx)		(0x1184 + ((idx) << 2))
+/* MAC handling */
+#define RTL838X_MAC_LINK_STS			(0xa188)
+#define RTL839X_MAC_LINK_STS			(0x0390)
+#define RTL838X_MAC_LINK_SPD_STS		(0xa190)
+#define RTL839X_MAC_LINK_SPD_STS		(0x03a0)
+#define RTL838X_MAC_LINK_DUP_STS		(0xa19c)
+#define RTL839X_MAC_LINK_DUP_STS		(0x03b0)
+// TODO: RTL8390_MAC_LINK_MEDIA_STS_ADDR ???
+#define RTL838X_MAC_TX_PAUSE_STS		(0xa1a0)
+#define RTL839X_MAC_TX_PAUSE_STS		(0x03b8)
+#define RTL838X_MAC_RX_PAUSE_STS		(0xa1a4)
+#define RTL839X_MAC_RX_PAUSE_STS		(0x03c0)
+#define RTL838X_EEE_TX_TIMER_GIGA_CTRL		(0xaa04)
+#define RTL838X_EEE_TX_TIMER_GELITE_CTRL	(0xaa08)
+#define RTL839X_MAC_GLB_CTRL			(0x02a8)
+#define RTL839X_SCHED_LB_TICK_TKN_CTRL		(0x60f8)
+
+#define RTL838X_L2_TBL_FLUSH_CTRL		(0x3370)
+#define RTL839X_L2_TBL_FLUSH_CTRL		(0x3ba0)
+
+/* MAC link state bits */
+#define FORCE_EN				(1 << 0)
+#define FORCE_LINK_EN				(1 << 1)
+#define NWAY_EN					(1 << 2)
+#define DUPLX_MODE				(1 << 3)
+#define TX_PAUSE_EN				(1 << 6)
+#define RX_PAUSE_EN				(1 << 7)
+
+/* RTL839X L2 Notification DMA interface */
+#define RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL	(0x785C)
+#define RTL839X_L2_NOTIFICATION_CTRL		(0x7808)
+#define RTL838X_L2_CTRL_0			(0x3200)
+#define RTL839X_L2_CTRL_0			(0x3800)
+
+/* TRAPPING to CPU-PORT */
+#define RTL838X_SPCL_TRAP_IGMP_CTRL		(0x6984)
+#define RTL839X_SPCL_TRAP_IGMP_CTRL		(0x1058)
+#define RTL838X_RMA_CTRL_0			(0x4300)
+#define RTL838X_RMA_CTRL_1			(0x4304)
+#define RTL839X_RMA_CTRL_0			(0x1200)
+#define RTL839X_RMA_CTRL_1			(0x1204)
+#define RTL839X_RMA_CTRL_2			(0x1208)
+#define RTL839X_RMA_CTRL_3			(0x120C)
+
+/* Registers of the internal Serdes of the 8390 */
+#define RTL839X_SDS12_13_XSG0			(0xB800)
+
+
+inline int rtl838x_mac_port_ctrl(int p)
+{
+	return RTL838X_MAC_PORT_CTRL + (p << 7);
+}
+
+inline int rtl839x_mac_port_ctrl(int p)
+{
+	return RTL839X_MAC_PORT_CTRL + (p << 7);
+}
+
+static inline int rtl838x_mac_force_mode_ctrl(int p)
+{
+	return RTL838X_MAC_FORCE_MODE_CTRL + (p << 2);
+}
+
+static inline int rtl839x_mac_force_mode_ctrl(int p)
+{
+	return RTL839X_MAC_FORCE_MODE_CTRL + (p << 2);
+}
+
+inline int rtl838x_dma_rx_base(int i)
+{
+	return RTL838X_DMA_RX_BASE + (i << 2);
+}
+
+inline int rtl839x_dma_rx_base(int i)
+{
+	return RTL839X_DMA_RX_BASE + (i << 2);
+}
+
+inline int rtl838x_dma_tx_base(int i)
+{
+	return RTL838X_DMA_TX_BASE + (i << 2);
+}
+
+inline int rtl839x_dma_tx_base(int i)
+{
+	return RTL839X_DMA_TX_BASE + (i << 2);
+}
+
+inline int rtl838x_dma_if_rx_ring_size(int i)
+{
+	return RTL838X_DMA_IF_RX_RING_SIZE + ((i >> 3) << 2);
+}
+
+inline int rtl839x_dma_if_rx_ring_size(int i)
+{
+	return RTL839X_DMA_IF_RX_RING_SIZE + ((i >> 3) << 2);
+}
+
+inline int rtl838x_dma_if_rx_ring_cntr(int i)
+{
+	return RTL838X_DMA_IF_RX_RING_CNTR + ((i >> 3) << 2);
+}
+
+inline int rtl839x_dma_if_rx_ring_cntr(int i)
+{
+	return RTL839X_DMA_IF_RX_RING_CNTR + ((i >> 3) << 2);
+}
+
+
+inline int rtl838x_dma_if_rx_cur(int i)
+{
+	return RTL838X_DMA_IF_RX_CUR + (i << 2);
+}
+
+inline int rtl839x_dma_if_rx_cur(int i)
+{
+	return RTL839X_DMA_IF_RX_CUR + (i << 2);
+}
+
+inline u32 rtl838x_get_mac_link_sts(int port)
+{
+	return (sw_r32(RTL838X_MAC_LINK_STS) & (1 << port));
+}
+
+inline u32 rtl839x_get_mac_link_sts(int p)
+{
+	return (sw_r32(RTL839X_MAC_LINK_STS + ((p >> 5) << 2)) & (1 << p));
+}
+
+inline u32 rtl838x_get_mac_link_dup_sts(int port)
+{
+	return (sw_r32(RTL838X_MAC_LINK_DUP_STS) & (1 << port));
+}
+
+inline u32 rtl839x_get_mac_link_dup_sts(int p)
+{
+	return (sw_r32(RTL839X_MAC_LINK_DUP_STS + ((p >> 5) << 2)) & (1 << p));
+}
+
+inline u32 rtl838x_get_mac_link_spd_sts(int port)
+{
+	int r = RTL838X_MAC_LINK_SPD_STS + ((port >> 4) << 2);
+	u32 speed = sw_r32(r);
+
+	speed >>= (port % 16) << 1;
+	return (speed & 0x3);
+}
+
+inline u32 rtl839x_get_mac_link_spd_sts(int port)
+{
+	int r = RTL839X_MAC_LINK_SPD_STS + ((port >> 4) << 2);
+	u32 speed = sw_r32(r);
+
+	speed >>= (port % 16) << 1;
+	return (speed & 0x3);
+}
+
+inline u32 rtl838x_get_mac_rx_pause_sts(int port)
+{
+	return (sw_r32(RTL838X_MAC_RX_PAUSE_STS) & (1 << port));
+}
+
+inline u32 rtl839x_get_mac_rx_pause_sts(int p)
+{
+	return (sw_r32(RTL839X_MAC_RX_PAUSE_STS + ((p >> 5) << 2)) & (1 << p));
+}
+
+inline u32 rtl838x_get_mac_tx_pause_sts(int port)
+{
+	return (sw_r32(RTL838X_MAC_TX_PAUSE_STS) & (1 << port));
+}
+
+inline u32 rtl839x_get_mac_tx_pause_sts(int p)
+{
+	return (sw_r32(RTL839X_MAC_TX_PAUSE_STS + ((p >> 5) << 2)) & (1 << p));
+}
+
+
+struct rtl838x_reg {
+	int (*mac_port_ctrl)(int port);
+	int dma_if_intr_sts;
+	int dma_if_intr_msk;
+	int dma_if_ctrl;
+	int  (*mac_force_mode_ctrl)(int port);
+	int  (*dma_rx_base)(int ring);
+	int  (*dma_tx_base)(int ring);
+	int  (*dma_if_rx_ring_size)(int ring);
+	int  (*dma_if_rx_ring_cntr)(int ring);
+	int  (*dma_if_rx_cur)(int ring);
+	int rst_glb_ctrl;
+	u32 (*get_mac_link_sts)(int port);
+	u32 (*get_mac_link_dup_sts)(int port);
+	u32 (*get_mac_link_spd_sts)(int port);
+	u32 (*get_mac_rx_pause_sts)(int port);
+	u32 (*get_mac_tx_pause_sts)(int port);
+	int mac;
+	int l2_tbl_flush_ctrl;
+};
+
+int rtl838x_write_phy(u32 port, u32 page, u32 reg, u32 val);
+int rtl838x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
+int rtl839x_write_phy(u32 port, u32 page, u32 reg, u32 val);
+int rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
+
+#endif /* _RTL838X_ETH_H */
diff --git a/target/linux/realtek/files-5.4/drivers/net/phy/rtl83xx-phy.c b/target/linux/realtek/files-5.4/drivers/net/phy/rtl83xx-phy.c
new file mode 100644
index 0000000000..eba416934f
--- /dev/null
+++ b/target/linux/realtek/files-5.4/drivers/net/phy/rtl83xx-phy.c
@@ -0,0 +1,1400 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* Realtek RTL838X Ethernet MDIO interface driver
+ *
+ * Copyright (C) 2020 B. Koblitz
+ */
+
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/phy.h>
+#include <linux/netdevice.h>
+#include <linux/firmware.h>
+#include <linux/crc32.h>
+
+#include <asm/mach-rtl838x/mach-rtl83xx.h>
+#include "rtl83xx-phy.h"
+
+
+extern struct rtl83xx_soc_info soc_info;
+extern struct mutex smi_lock;
+
+static const struct firmware rtl838x_8380_fw;
+static const struct firmware rtl838x_8214fc_fw;
+static const struct firmware rtl838x_8218b_fw;
+
+
+static int read_phy(u32 port, u32 page, u32 reg, u32 *val)
+{
+	if (soc_info.family == RTL8390_FAMILY_ID)
+		return rtl839x_read_phy(port, page, reg, val);
+	else
+		return rtl838x_read_phy(port, page, reg, val);
+}
+
+static int write_phy(u32 port, u32 page, u32 reg, u32 val)
+{
+	if (soc_info.family == RTL8390_FAMILY_ID)
+		return rtl839x_write_phy(port, page, reg, val);
+	else
+		return rtl838x_write_phy(port, page, reg, val);
+}
+
+static void int_phy_on_off(int mac, bool on)
+{
+	u32 val;
+
+	read_phy(mac, 0, 0, &val);
+	if (on)
+		write_phy(mac, 0, 0, val & ~(1 << 11));
+	else
+		write_phy(mac, 0, 0, val | (1 << 11));
+}
+
+static void rtl8214fc_on_off(int mac, bool on)
+{
+	u32 val;
+
+	/* fiber ports */
+	write_phy(mac, 4095, 30, 3);
+	read_phy(mac, 0, 16, &val);
+	if (on)
+		write_phy(mac, 0, 16, val & ~(1 << 11));
+	else
+		write_phy(mac, 0, 16, val | (1 << 11));
+
+	/* copper ports */
+	write_phy(mac, 4095, 30, 1);
+	read_phy(mac, 0, 16, &val);
+	if (on)
+		write_phy(mac, 0xa40, 16, val & ~(1 << 11));
+	else
+		write_phy(mac, 0xa40, 16, val | (1 << 11));
+}
+
+static void phy_reset(int mac)
+{
+	u32 val;
+
+	read_phy(mac, 0, 0, &val);
+	write_phy(mac, 0, 0, val | (0x1 << 15));
+}
+
+/* Read the link and speed status of the 2 internal SGMII/1000Base-X
+ * ports of the RTL838x SoCs
+ */
+static int rtl8380_read_status(struct phy_device *phydev)
+{
+	int err;
+
+	err = genphy_read_status(phydev);
+
+	if (phydev->link) {
+		phydev->speed = SPEED_1000;
+		phydev->duplex = DUPLEX_FULL;
+	}
+
+	return err;
+}
+
+/* Read the link and speed status of the 2 internal SGMII/1000Base-X
+ * ports of the RTL8393 SoC
+ */
+static int rtl8393_read_status(struct phy_device *phydev)
+{
+	int offset = 0;
+	int err;
+	int phy_addr = phydev->mdio.addr;
+	u32 v;
+
+	err = genphy_read_status(phydev);
+	if (phy_addr == 49)
+		offset = 0x100;
+
+	if (phydev->link) {
+		phydev->speed = SPEED_100;
+		/* Read SPD_RD_00 (bit 13) and SPD_RD_01 (bit 6) out of the internal
+		 * PHY registers
+		 */
+		v = sw_r32(RTL839X_SDS12_13_XSG0 + offset + 0x80);
+		if (!(v & (1 << 13)) && (v & (1 << 6)))
+			phydev->speed = SPEED_1000;
+		phydev->duplex = DUPLEX_FULL;
+	}
+
+	return err;
+}
+
+static struct fw_header *rtl838x_request_fw(struct phy_device *phydev,
+					    const struct firmware *fw,
+					    const char *name)
+{
+	struct device *dev = &phydev->mdio.dev;
+	int err;
+	struct fw_header *h;
+	uint32_t checksum, my_checksum;
+
+	err = request_firmware(&fw, name, dev);
+	if (err < 0)
+		goto out;
+
+	if (fw->size < sizeof(struct fw_header)) {
+		pr_err("Firmware size too small.\n");
+		err = -EINVAL;
+		goto out;
+	}
+
+	h = (struct fw_header *) fw->data;
+	pr_info("Firmware loaded. Size %d, magic: %08x\n", fw->size, h->magic);
+
+	if (h->magic != 0x83808380) {
+		pr_err("Wrong firmware file: MAGIC mismatch.\n");
+		goto out;
+	}
+
+	checksum = h->checksum;
+	h->checksum = 0;
+	my_checksum = ~crc32(0xFFFFFFFFU, fw->data, fw->size);
+	if (checksum != my_checksum) {
+		pr_err("Firmware checksum mismatch.\n");
+		err = -EINVAL;
+		goto out;
+	}
+	h->checksum = checksum;
+
+	return h;
+out:
+	dev_err(dev, "Unable to load firmware %s (%d)\n", name, err);
+	return NULL;
+}
+
+static int rtl8390_configure_generic(struct phy_device *phydev)
+{
+	u32 val, phy_id;
+	int mac = phydev->mdio.addr;
+
+	read_phy(mac, 0, 2, &val);
+	phy_id = val << 16;
+	read_phy(mac, 0, 3, &val);
+	phy_id |= val;
+	pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
+
+	/* Read internal PHY ID */
+	write_phy(mac, 31, 27, 0x0002);
+	read_phy(mac, 31, 28, &val);
+
+	/* Internal RTL8218B, version 2 */
+	phydev_info(phydev, "Detected unknown %x\n", val);
+	return 0;
+}
+
+static int rtl8380_configure_int_rtl8218b(struct phy_device *phydev)
+{
+	u32 val, phy_id;
+	int i, p, ipd_flag;
+	int mac = phydev->mdio.addr;
+	struct fw_header *h;
+	u32 *rtl838x_6275B_intPhy_perport;
+	u32 *rtl8218b_6276B_hwEsd_perport;
+
+
+	read_phy(mac, 0, 2, &val);
+	phy_id = val << 16;
+	read_phy(mac, 0, 3, &val);
+	phy_id |= val;
+	pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
+
+	/* Read internal PHY ID */
+	write_phy(mac, 31, 27, 0x0002);
+	read_phy(mac, 31, 28, &val);
+	if (val != 0x6275) {
+		phydev_err(phydev, "Expected internal RTL8218B, found PHY-ID %x\n", val);
+		return -1;
+	}
+
+	/* Internal RTL8218B, version 2 */
+	phydev_info(phydev, "Detected internal RTL8218B\n");
+
+	h = rtl838x_request_fw(phydev, &rtl838x_8380_fw, FIRMWARE_838X_8380_1);
+	if (!h)
+		return -1;
+
+	if (h->phy != 0x83800000) {
+		phydev_err(phydev, "Wrong firmware file: PHY mismatch.\n");
+		return -1;
+	}
+
+	rtl838x_6275B_intPhy_perport = (void *)h + sizeof(struct fw_header)
+			+ h->parts[8].start;
+
+	rtl8218b_6276B_hwEsd_perport = (void *)h + sizeof(struct fw_header)
+			+ h->parts[9].start;
+
+	if (sw_r32(RTL838X_DMY_REG31) == 0x1)
+		ipd_flag = 1;
+
+	read_phy(mac, 0, 0, &val);
+	if (val & (1 << 11))
+		int_phy_on_off(mac, true);
+	else
+		phy_reset(mac);
+	msleep(100);
+
+	/* Ready PHY for patch */
+	for (p = 0; p < 8; p++) {
+		write_phy(mac + p, 0xfff, 0x1f, 0x0b82);
+		write_phy(mac + p, 0xfff, 0x10, 0x0010);
+	}
+	msleep(500);
+	for (p = 0; p < 8; p++) {
+		for (i = 0; i < 100 ; i++) {
+			read_phy(mac + p, 0x0b80, 0x10, &val);
+			if (val & 0x40)
+				break;
+		}
+		if (i >= 100) {
+			phydev_err(phydev,
+				   "ERROR: Port %d not ready for patch.\n",
+				   mac + p);
+			return -1;
+		}
+	}
+	for (p = 0; p < 8; p++) {
+		i = 0;
+		while (rtl838x_6275B_intPhy_perport[i * 2]) {
+			write_phy(mac + p, 0xfff,
+				rtl838x_6275B_intPhy_perport[i * 2],
+				rtl838x_6275B_intPhy_perport[i * 2 + 1]);
+			i++;
+		}
+		i = 0;
+		while (rtl8218b_6276B_hwEsd_perport[i * 2]) {
+			write_phy(mac + p, 0xfff,
+				rtl8218b_6276B_hwEsd_perport[i * 2],
+				rtl8218b_6276B_hwEsd_perport[i * 2 + 1]);
+			i++;
+		}
+	}
+	return 0;
+}
+
+static int rtl8380_configure_ext_rtl8218b(struct phy_device *phydev)
+{
+	u32 val, ipd, phy_id;
+	int i, l;
+	int mac = phydev->mdio.addr;
+	struct fw_header *h;
+	u32 *rtl8380_rtl8218b_perchip;
+	u32 *rtl8218B_6276B_rtl8380_perport;
+	u32 *rtl8380_rtl8218b_perport;
+
+	if (soc_info.family == RTL8380_FAMILY_ID && mac != 0 && mac != 16) {
+		phydev_err(phydev, "External RTL8218B must have PHY-IDs 0 or 16!\n");
+		return -1;
+	}
+	read_phy(mac, 0, 2, &val);
+	phy_id = val << 16;
+	read_phy(mac, 0, 3, &val);
+	phy_id |= val;
+	pr_info("Phy on MAC %d: %x\n", mac, phy_id);
+
+	/* Read internal PHY ID */
+	write_phy(mac, 31, 27, 0x0002);
+	read_phy(mac, 31, 28, &val);
+	if (val != 0x6276) {
+		phydev_err(phydev, "Expected external RTL8218B, found PHY-ID %x\n", val);
+		return -1;
+	}
+	phydev_info(phydev, "Detected external RTL8218B\n");
+
+	h = rtl838x_request_fw(phydev, &rtl838x_8218b_fw, FIRMWARE_838X_8218b_1);
+	if (!h)
+		return -1;
+
+	if (h->phy != 0x8218b000) {
+		phydev_err(phydev, "Wrong firmware file: PHY mismatch.\n");
+		return -1;
+	}
+
+	rtl8380_rtl8218b_perchip = (void *)h + sizeof(struct fw_header)
+			+ h->parts[0].start;
+
+	rtl8218B_6276B_rtl8380_perport = (void *)h + sizeof(struct fw_header)
+			+ h->parts[1].start;
+
+	rtl8380_rtl8218b_perport = (void *)h + sizeof(struct fw_header)
+			+ h->parts[2].start;
+
+	read_phy(mac, 0, 0, &val);
+	if (val & (1 << 11))
+		int_phy_on_off(mac, true);
+	else
+		phy_reset(mac);
+	msleep(100);
+
+	/* Get Chip revision */
+	write_phy(mac, 0xfff, 0x1f, 0x0);
+	write_phy(mac,  0xfff, 0x1b, 0x4);
+	read_phy(mac, 0xfff, 0x1c, &val);
+
+	i = 0;
+	while (rtl8380_rtl8218b_perchip[i * 3]
+		&& rtl8380_rtl8218b_perchip[i * 3 + 1]) {
+		write_phy(mac + rtl8380_rtl8218b_perchip[i * 3],
+					  0xfff, rtl8380_rtl8218b_perchip[i * 3 + 1],
+					  rtl8380_rtl8218b_perchip[i * 3 + 2]);
+		i++;
+	}
+
+	/* Enable PHY */
+	for (i = 0; i < 8; i++) {
+		write_phy(mac + i, 0xfff, 0x1f, 0x0000);
+		write_phy(mac + i, 0xfff, 0x00, 0x1140);
+	}
+	mdelay(100);
+
+	/* Request patch */
+	for (i = 0; i < 8; i++) {
+		write_phy(mac + i,  0xfff, 0x1f, 0x0b82);
+		write_phy(mac + i,  0xfff, 0x10, 0x0010);
+	}
+	mdelay(300);
+
+	/* Verify patch readiness */
+	for (i = 0; i < 8; i++) {
+		for (l = 0; l < 100; l++) {
+			read_phy(mac + i, 0xb80, 0x10, &val);
+			if (val & 0x40)
+				break;
+		}
+		if (l >= 100) {
+			phydev_err(phydev, "Could not patch PHY\n");
+			return -1;
+		}
+	}
+
+	/* Use Broadcast ID method for patching */
+	write_phy(mac, 0xfff, 0x1f, 0x0000);
+	write_phy(mac, 0xfff, 0x1d, 0x0008);
+	write_phy(mac, 0xfff, 0x1f, 0x0266);
+	write_phy(mac, 0xfff, 0x16, 0xff00 + mac);
+	write_phy(mac, 0xfff, 0x1f, 0x0000);
+	write_phy(mac, 0xfff, 0x1d, 0x0000);
+	mdelay(1);
+
+	write_phy(mac, 0xfff, 30, 8);
+	write_phy(mac, 0x26e, 17, 0xb);
+	write_phy(mac, 0x26e, 16, 0x2);
+	mdelay(1);
+	read_phy(mac, 0x26e, 19, &ipd);
+	write_phy(mac, 0, 30, 0);
+	ipd = (ipd >> 4) & 0xf;
+
+	i = 0;
+	while (rtl8218B_6276B_rtl8380_perport[i * 2]) {
+		write_phy(mac, 0xfff, rtl8218B_6276B_rtl8380_perport[i * 2],
+				  rtl8218B_6276B_rtl8380_perport[i * 2 + 1]);
+		i++;
+	}
+
+	/*Disable broadcast ID*/
+	write_phy(mac, 0xfff, 0x1f, 0x0000);
+	write_phy(mac, 0xfff, 0x1d, 0x0008);
+	write_phy(mac, 0xfff, 0x1f, 0x0266);
+	write_phy(mac, 0xfff, 0x16, 0x00 + mac);
+	write_phy(mac, 0xfff, 0x1f, 0x0000);
+	write_phy(mac, 0xfff, 0x1d, 0x0000);
+	mdelay(1);
+
+	return 0;
+}
+
+static int rtl8218b_ext_match_phy_device(struct phy_device *phydev)
+{
+	int addr = phydev->mdio.addr;
+
+	/* Both the RTL8214FC and the external RTL8218B have the same
+	 * PHY ID. On the RTL838x, the RTL8218B can only be attached_dev
+	 * at PHY IDs 0-7, while the RTL8214FC must be attached via
+	 * the pair of SGMII/1000Base-X with higher PHY-IDs
+	 */
+	if (soc_info.family == RTL8380_FAMILY_ID)
+		return phydev->phy_id == PHY_ID_RTL8218B_E && addr < 8;
+	else
+		return phydev->phy_id == PHY_ID_RTL8218B_E;
+}
+
+/*
+ * Read an mmd register of the PHY
+ */
+static int rtl83xx_read_mmd_phy(u32 port, u32 addr, u32 reg, u32 *val)
+{
+	u32 v;
+
+	mutex_lock(&smi_lock);
+
+	if (rtl838x_smi_wait_op(10000))
+		goto timeout;
+
+	sw_w32(1 << port, RTL838X_SMI_ACCESS_PHY_CTRL_0);
+	mdelay(10);
+
+	sw_w32_mask(0xffff0000, port << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2);
+
+	v = addr << 16 | reg;
+	sw_w32(v, RTL838X_SMI_ACCESS_PHY_CTRL_3);
+
+	/* mmd-access | read | cmd-start */
+	v = 1 << 1 | 0 << 2 | 1;
+	sw_w32(v, RTL838X_SMI_ACCESS_PHY_CTRL_1);
+
+	if (rtl838x_smi_wait_op(10000))
+		goto timeout;
+
+	*val = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_2) & 0xffff;
+
+	mutex_unlock(&smi_lock);
+	return 0;
+
+timeout:
+	mutex_unlock(&smi_lock);
+	return -ETIMEDOUT;
+}
+
+/*
+ * Write to an mmd register of the PHY
+ */
+static int rtl838x_write_mmd_phy(u32 port, u32 addr, u32 reg, u32 val)
+{
+	u32 v;
+
+	pr_debug("MMD write: port %d, dev %d, reg %d, val %x\n", port, addr, reg, val);
+	val &= 0xffff;
+	mutex_lock(&smi_lock);
+
+	if (rtl838x_smi_wait_op(10000))
+		goto timeout;
+
+	sw_w32(1 << port, RTL838X_SMI_ACCESS_PHY_CTRL_0);
+	mdelay(10);
+
+	sw_w32_mask(0xffff0000, val << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2);
+
+	sw_w32_mask(0x1f << 16, addr << 16, RTL838X_SMI_ACCESS_PHY_CTRL_3);
+	sw_w32_mask(0xffff, reg, RTL838X_SMI_ACCESS_PHY_CTRL_3);
+	/* mmd-access | write | cmd-start */
+	v = 1 << 1 | 1 << 2 | 1;
+	sw_w32(v, RTL838X_SMI_ACCESS_PHY_CTRL_1);
+
+	if (rtl838x_smi_wait_op(10000))
+		goto timeout;
+
+	mutex_unlock(&smi_lock);
+	return 0;
+
+timeout:
+	mutex_unlock(&smi_lock);
+	return -ETIMEDOUT;
+}
+
+static int rtl8218b_read_mmd(struct phy_device *phydev,
+				     int devnum, u16 regnum)
+{
+	int ret;
+	u32 val;
+	int addr = phydev->mdio.addr;
+
+	ret = rtl83xx_read_mmd_phy(addr, devnum, regnum, &val);
+	if (ret)
+		return ret;
+	return val;
+}
+
+static int rtl8218b_write_mmd(struct phy_device *phydev,
+				      int devnum, u16 regnum, u16 val)
+{
+	int addr = phydev->mdio.addr;
+
+	return rtl838x_write_mmd_phy(addr, devnum, regnum, val);
+}
+
+static void rtl8380_rtl8214fc_media_set(int mac, bool set_fibre)
+{
+	int base = mac - (mac % 4);
+	static int reg[] = {16, 19, 20, 21};
+	int val, media, power;
+
+	pr_info("%s: port %d, set_fibre: %d\n", __func__, mac, set_fibre);
+	write_phy(base, 0xfff, 29, 8);
+	read_phy(base, 0x266, reg[mac % 4], &val);
+
+	media = (val >> 10) & 0x3;
+	pr_info("Current media %x\n", media);
+	if (media & 0x2) {
+		pr_info("Powering off COPPER\n");
+		write_phy(base, 0xfff, 29, 1);
+		/* Ensure power is off */
+		read_phy(base, 0xa40, 16, &power);
+		if (!(power & (1 << 11)))
+			write_phy(base, 0xa40, 16, power | (1 << 11));
+	} else {
+		pr_info("Powering off FIBRE");
+		write_phy(base, 0xfff, 29, 3);
+		/* Ensure power is off */
+		read_phy(base, 0xa40, 16, &power);
+		if (!(power & (1 << 11)))
+			write_phy(base, 0xa40, 16, power | (1 << 11));
+	}
+
+	if (set_fibre) {
+		val |= 1 << 10;
+		val &= ~(1 << 11);
+	} else {
+		val |= 1 << 10;
+		val |= 1 << 11;
+	}
+	write_phy(base, 0xfff, 29, 8);
+	write_phy(base, 0x266, reg[mac % 4], val);
+	write_phy(base, 0xfff, 29, 0);
+
+	if (set_fibre) {
+		pr_info("Powering on FIBRE");
+		write_phy(base, 0xfff, 29, 3);
+		/* Ensure power is off */
+		read_phy(base, 0xa40, 16, &power);
+		if (power & (1 << 11))
+			write_phy(base, 0xa40, 16, power & ~(1 << 11));
+	} else {
+		pr_info("Powering on COPPER\n");
+		write_phy(base, 0xfff, 29, 1);
+		/* Ensure power is off */
+		read_phy(base, 0xa40, 16, &power);
+		if (power & (1 << 11))
+			write_phy(base, 0xa40, 16, power & ~(1 << 11));
+	}
+
+	write_phy(base, 0xfff, 29, 0);
+}
+
+static bool rtl8380_rtl8214fc_media_is_fibre(int mac)
+{
+	int base = mac - (mac % 4);
+	static int reg[] = {16, 19, 20, 21};
+	u32 val;
+
+	write_phy(base, 0xfff, 29, 8);
+	read_phy(base, 0x266, reg[mac % 4], &val);
+	write_phy(base, 0xfff, 29, 0);
+	if (val & (1 << 11))
+		return false;
+	return true;
+}
+
+static int rtl8214fc_set_port(struct phy_device *phydev, int port)
+{
+	bool is_fibre = (port == PORT_FIBRE ? true : false);
+	int addr = phydev->mdio.addr;
+
+	pr_debug("%s port %d to %d\n", __func__, addr, port);
+
+	rtl8380_rtl8214fc_media_set(addr, is_fibre);
+	return 0;
+}
+
+static int rtl8214fc_get_port(struct phy_device *phydev)
+{
+	int addr = phydev->mdio.addr;
+
+	pr_debug("%s: port %d\n", __func__, addr);
+	if (rtl8380_rtl8214fc_media_is_fibre(addr))
+		return PORT_FIBRE;
+	return PORT_MII;
+}
+
+static void rtl8218b_eee_set_u_boot(int port, bool enable)
+{
+	u32 val;
+	bool an_enabled;
+
+	/* Set GPHY page to copper */
+	write_phy(port, 0, 30, 0x0001);
+	read_phy(port, 0, 0, &val);
+	an_enabled = val & (1 << 12);
+
+	if (enable) {
+		/* 100/1000M EEE Capability */
+		write_phy(port, 0, 13, 0x0007);
+		write_phy(port, 0, 14, 0x003C);
+		write_phy(port, 0, 13, 0x4007);
+		write_phy(port, 0, 14, 0x0006);
+
+		read_phy(port, 0x0A43, 25, &val);
+		val |= 1 << 4;
+		write_phy(port, 0x0A43, 25, val);
+	} else {
+		/* 100/1000M EEE Capability */
+		write_phy(port, 0, 13, 0x0007);
+		write_phy(port, 0, 14, 0x003C);
+		write_phy(port, 0, 13, 0x0007);
+		write_phy(port, 0, 14, 0x0000);
+
+		read_phy(port, 0x0A43, 25, &val);
+		val &= ~(1 << 4);
+		write_phy(port, 0x0A43, 25, val);
+	}
+
+	/* Restart AN if enabled */
+	if (an_enabled) {
+		read_phy(port, 0, 0, &val);
+		val |= (1 << 12) | (1 << 9);
+		write_phy(port, 0, 0, val);
+	}
+
+	/* GPHY page back to auto*/
+	write_phy(port, 0xa42, 29, 0);
+}
+
+// TODO: unused
+static void rtl8380_rtl8218b_eee_set(int port, bool enable)
+{
+	u32 val;
+	bool an_enabled;
+
+	pr_debug("In %s %d, enable %d\n", __func__, port, enable);
+	/* Set GPHY page to copper */
+	write_phy(port, 0xa42, 29, 0x0001);
+
+	read_phy(port, 0, 0, &val);
+	an_enabled = val & (1 << 12);
+
+	/* MAC based EEE */
+	read_phy(port, 0xa43, 25, &val);
+	val &= ~(1 << 5);
+	write_phy(port, 0xa43, 25, val);
+
+	/* 100M / 1000M EEE */
+	if (enable)
+		rtl838x_write_mmd_phy(port, 7, 60, 0x6);
+	else
+		rtl838x_write_mmd_phy(port, 7, 60, 0);
+
+	/* 500M EEE ability */
+	read_phy(port, 0xa42, 20, &val);
+	if (enable)
+		val |= 1 << 7;
+	else
+		val &= ~(1 << 7);
+	write_phy(port, 0xa42, 20, val);
+
+	/* Restart AN if enabled */
+	if (an_enabled) {
+		read_phy(port, 0, 0, &val);
+		val |= (1 << 12) | (1 << 9);
+		write_phy(port, 0, 0, val);
+	}
+
+	/* GPHY page back to auto*/
+	write_phy(port, 0xa42, 29, 0);
+}
+
+static int rtl8218b_get_eee(struct phy_device *phydev,
+				     struct ethtool_eee *e)
+{
+	u32 val;
+	int addr = phydev->mdio.addr;
+
+	pr_debug("In %s, port %d\n", __func__, addr);
+
+	/* Set GPHY page to copper */
+	write_phy(addr, 0xa42, 29, 0x0001);
+
+	rtl83xx_read_mmd_phy(addr, 7, 60, &val);
+	if (e->eee_enabled && (!!(val & (1 << 7))))
+		e->eee_enabled = !!(val & (1 << 7));
+	else
+		e->eee_enabled = 0;
+
+	/* GPHY page to auto */
+	write_phy(addr, 0xa42, 29, 0x0000);
+
+	return 0;
+}
+
+// TODO: unused
+static void rtl8380_rtl8218b_green_set(int mac, bool enable)
+{
+	u32 val;
+
+	/* Set GPHY page to copper */
+	write_phy(mac, 0xa42, 29, 0x0001);
+
+	write_phy(mac, 0, 27, 0x8011);
+	read_phy(mac, 0, 28, &val);
+	if (enable) {
+		val |= 1 << 9;
+		write_phy(mac, 0, 27, 0x8011);
+		write_phy(mac, 0, 28, val);
+	} else {
+		val &= ~(1 << 9);
+		write_phy(mac, 0, 27, 0x8011);
+		write_phy(mac, 0, 28, val);
+	}
+
+	/* GPHY page to auto */
+	write_phy(mac, 0xa42, 29, 0x0000);
+}
+
+// TODO: unused
+static int rtl8380_rtl8214fc_get_green(struct phy_device *phydev, struct ethtool_eee *e)
+{
+	u32 val;
+	int addr = phydev->mdio.addr;
+
+	pr_debug("In %s %d\n", __func__, addr);
+	/* Set GPHY page to copper */
+	write_phy(addr, 0xa42, 29, 0x0001);
+
+	write_phy(addr, 0, 27, 0x8011);
+	read_phy(addr, 0, 28, &val);
+	if (e->eee_enabled && (!!(val & (1 << 9))))
+		e->eee_enabled = !!(val & (1 << 9));
+	else
+		e->eee_enabled = 0;
+
+	/* GPHY page to auto */
+	write_phy(addr, 0xa42, 29, 0x0000);
+
+	return 0;
+}
+
+static int rtl8214fc_set_eee(struct phy_device *phydev,
+				     struct ethtool_eee *e)
+{
+	u32 pollMask;
+	int addr = phydev->mdio.addr;
+
+	pr_debug("In %s port %d, enabled %d\n", __func__, addr, e->eee_enabled);
+
+	if (rtl8380_rtl8214fc_media_is_fibre(addr)) {
+		netdev_err(phydev->attached_dev, "Port %d configured for FIBRE", addr);
+		return -ENOTSUPP;
+	}
+
+	pollMask = sw_r32(RTL838X_SMI_POLL_CTRL);
+	sw_w32(0, RTL838X_SMI_POLL_CTRL);
+	rtl8218b_eee_set_u_boot(addr, (bool) e->eee_enabled);
+	sw_w32(pollMask, RTL838X_SMI_POLL_CTRL);
+	return 0;
+}
+
+static int rtl8214fc_get_eee(struct phy_device *phydev,
+				      struct ethtool_eee *e)
+{
+	int addr = phydev->mdio.addr;
+
+	pr_debug("In %s port %d, enabled %d\n", __func__, addr, e->eee_enabled);
+	if (rtl8380_rtl8214fc_media_is_fibre(addr)) {
+		netdev_err(phydev->attached_dev, "Port %d configured for FIBRE", addr);
+		return -ENOTSUPP;
+	}
+
+	return rtl8218b_get_eee(phydev, e);
+}
+
+static int rtl8218b_set_eee(struct phy_device *phydev,
+				     struct ethtool_eee *e)
+{
+	u32 pollMask;
+	int addr = phydev->mdio.addr;
+
+	pr_debug("In %s, port %d, enabled %d\n", __func__, addr, e->eee_enabled);
+
+	pollMask = sw_r32(RTL838X_SMI_POLL_CTRL);
+	sw_w32(0, RTL838X_SMI_POLL_CTRL);
+	rtl8218b_eee_set_u_boot(addr, (bool) e->eee_enabled);
+	sw_w32(pollMask, RTL838X_SMI_POLL_CTRL);
+
+	return 0;
+}
+
+static int rtl8214c_match_phy_device(struct phy_device *phydev)
+{
+	return phydev->phy_id == PHY_ID_RTL8214C;
+}
+
+static int rtl8380_configure_rtl8214c(struct phy_device *phydev)
+{
+	u32 phy_id, val;
+	int mac = phydev->mdio.addr;
+
+	read_phy(mac, 0, 2, &val);
+	phy_id = val << 16;
+	read_phy(mac, 0, 3, &val);
+	phy_id |= val;
+	pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
+
+	phydev_info(phydev, "Detected external RTL8214C\n");
+
+	/* GPHY auto conf */
+	write_phy(mac, 0xa42, 29, 0);
+	return 0;
+}
+
+static int rtl8380_configure_rtl8214fc(struct phy_device *phydev)
+{
+	u32 phy_id, val, page = 0;
+	int i, l;
+	int mac = phydev->mdio.addr;
+	struct fw_header *h;
+	u32 *rtl8380_rtl8214fc_perchip;
+	u32 *rtl8380_rtl8214fc_perport;
+
+	read_phy(mac, 0, 2, &val);
+	phy_id = val << 16;
+	read_phy(mac, 0, 3, &val);
+	phy_id |= val;
+	pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
+
+	/* Read internal PHY id */
+	write_phy(mac, 0, 30, 0x0001);
+	write_phy(mac, 0, 31, 0x0a42);
+	write_phy(mac, 31, 27, 0x0002);
+	read_phy(mac, 31, 28, &val);
+	if (val != 0x6276) {
+		phydev_err(phydev, "Expected external RTL8214FC, found PHY-ID %x\n", val);
+		return -1;
+	}
+	phydev_info(phydev, "Detected external RTL8214FC\n");
+
+	h = rtl838x_request_fw(phydev, &rtl838x_8214fc_fw, FIRMWARE_838X_8214FC_1);
+	if (!h)
+		return -1;
+
+	if (h->phy != 0x8214fc00) {
+		phydev_err(phydev, "Wrong firmware file: PHY mismatch.\n");
+		return -1;
+	}
+
+	rtl8380_rtl8214fc_perchip = (void *)h + sizeof(struct fw_header)
+		   + h->parts[0].start;
+
+	rtl8380_rtl8214fc_perport = (void *)h + sizeof(struct fw_header)
+		   + h->parts[1].start;
+
+	/* detect phy version */
+	write_phy(mac, 0xfff, 27, 0x0004);
+	read_phy(mac, 0xfff, 28, &val);
+
+	read_phy(mac, 0, 16, &val);
+	if (val & (1 << 11))
+		rtl8214fc_on_off(mac, true);
+	else
+		phy_reset(mac);
+
+	msleep(100);
+	write_phy(mac, 0, 30, 0x0001);
+
+	i = 0;
+	while (rtl8380_rtl8214fc_perchip[i * 3]
+	       && rtl8380_rtl8214fc_perchip[i * 3 + 1]) {
+		if (rtl8380_rtl8214fc_perchip[i * 3 + 1] == 0x1f)
+			page = rtl8380_rtl8214fc_perchip[i * 3 + 2];
+		if (rtl8380_rtl8214fc_perchip[i * 3 + 1] == 0x13 && page == 0x260) {
+			read_phy(mac + rtl8380_rtl8214fc_perchip[i * 3], 0x260, 13, &val);
+			val = (val & 0x1f00) | (rtl8380_rtl8214fc_perchip[i * 3 + 2]
+				& 0xe0ff);
+			write_phy(mac + rtl8380_rtl8214fc_perchip[i * 3],
+					  0xfff, rtl8380_rtl8214fc_perchip[i * 3 + 1], val);
+		} else {
+			write_phy(mac + rtl8380_rtl8214fc_perchip[i * 3],
+					  0xfff, rtl8380_rtl8214fc_perchip[i * 3 + 1],
+					  rtl8380_rtl8214fc_perchip[i * 3 + 2]);
+		}
+		i++;
+	}
+
+	/* Force copper medium */
+	for (i = 0; i < 4; i++) {
+		write_phy(mac + i, 0xfff, 0x1f, 0x0000);
+		write_phy(mac + i, 0xfff, 0x1e, 0x0001);
+	}
+
+	/* Enable PHY */
+	for (i = 0; i < 4; i++) {
+		write_phy(mac + i, 0xfff, 0x1f, 0x0000);
+		write_phy(mac + i, 0xfff, 0x00, 0x1140);
+	}
+	mdelay(100);
+
+	/* Disable Autosensing */
+	for (i = 0; i < 4; i++) {
+		for (l = 0; l < 100; l++) {
+			read_phy(mac + i, 0x0a42, 0x10, &val);
+			if ((val & 0x7) >= 3)
+				break;
+		}
+		if (l >= 100) {
+			phydev_err(phydev, "Could not disable autosensing\n");
+			return -1;
+		}
+	}
+
+	/* Request patch */
+	for (i = 0; i < 4; i++) {
+		write_phy(mac + i,  0xfff, 0x1f, 0x0b82);
+		write_phy(mac + i,  0xfff, 0x10, 0x0010);
+	}
+	mdelay(300);
+
+	/* Verify patch readiness */
+	for (i = 0; i < 4; i++) {
+		for (l = 0; l < 100; l++) {
+			read_phy(mac + i, 0xb80, 0x10, &val);
+			if (val & 0x40)
+				break;
+		}
+		if (l >= 100) {
+			phydev_err(phydev, "Could not patch PHY\n");
+			return -1;
+		}
+	}
+
+	/* Use Broadcast ID method for patching */
+	write_phy(mac, 0xfff, 0x1f, 0x0000);
+	write_phy(mac, 0xfff, 0x1d, 0x0008);
+	write_phy(mac, 0xfff, 0x1f, 0x0266);
+	write_phy(mac, 0xfff, 0x16, 0xff00 + mac);
+	write_phy(mac, 0xfff, 0x1f, 0x0000);
+	write_phy(mac, 0xfff, 0x1d, 0x0000);
+	mdelay(1);
+
+	i = 0;
+	while (rtl8380_rtl8214fc_perport[i * 2]) {
+		write_phy(mac, 0xfff, rtl8380_rtl8214fc_perport[i * 2],
+				  rtl8380_rtl8214fc_perport[i * 2 + 1]);
+		i++;
+	}
+
+	/*Disable broadcast ID*/
+	write_phy(mac, 0xfff, 0x1f, 0x0000);
+	write_phy(mac, 0xfff, 0x1d, 0x0008);
+	write_phy(mac, 0xfff, 0x1f, 0x0266);
+	write_phy(mac, 0xfff, 0x16, 0x00 + mac);
+	write_phy(mac, 0xfff, 0x1f, 0x0000);
+	write_phy(mac, 0xfff, 0x1d, 0x0000);
+	mdelay(1);
+
+	/* Auto medium selection */
+	for (i = 0; i < 4; i++) {
+		write_phy(mac + i, 0xfff, 0x1f, 0x0000);
+		write_phy(mac + i, 0xfff, 0x1e, 0x0000);
+	}
+
+	return 0;
+}
+
+static int rtl8214fc_match_phy_device(struct phy_device *phydev)
+{
+	int addr = phydev->mdio.addr;
+
+	return phydev->phy_id == PHY_ID_RTL8214FC && addr >= 24;
+}
+
+static int rtl8380_configure_serdes(struct phy_device *phydev)
+{
+	u32 v;
+	u32 sds_conf_value;
+	int i;
+	struct fw_header *h;
+	u32 *rtl8380_sds_take_reset;
+	u32 *rtl8380_sds_common;
+	u32 *rtl8380_sds01_qsgmii_6275b;
+	u32 *rtl8380_sds23_qsgmii_6275b;
+	u32 *rtl8380_sds4_fiber_6275b;
+	u32 *rtl8380_sds5_fiber_6275b;
+	u32 *rtl8380_sds_reset;
+	u32 *rtl8380_sds_release_reset;
+
+	phydev_info(phydev, "Detected internal RTL8380 SERDES\n");
+
+	h = rtl838x_request_fw(phydev, &rtl838x_8218b_fw, FIRMWARE_838X_8380_1);
+	if (!h)
+		return -1;
+
+	if (h->magic != 0x83808380) {
+		phydev_err(phydev, "Wrong firmware file: magic number mismatch.\n");
+		return -1;
+	}
+
+	rtl8380_sds_take_reset = (void *)h + sizeof(struct fw_header)
+		   + h->parts[0].start;
+
+	rtl8380_sds_common = (void *)h + sizeof(struct fw_header)
+		   + h->parts[1].start;
+
+	rtl8380_sds01_qsgmii_6275b = (void *)h + sizeof(struct fw_header)
+		   + h->parts[2].start;
+
+	rtl8380_sds23_qsgmii_6275b = (void *)h + sizeof(struct fw_header)
+		   + h->parts[3].start;
+
+	rtl8380_sds4_fiber_6275b = (void *)h + sizeof(struct fw_header)
+		   + h->parts[4].start;
+
+	rtl8380_sds5_fiber_6275b = (void *)h + sizeof(struct fw_header)
+		   + h->parts[5].start;
+
+	rtl8380_sds_reset = (void *)h + sizeof(struct fw_header)
+		   + h->parts[6].start;
+
+	rtl8380_sds_release_reset = (void *)h + sizeof(struct fw_header)
+		   + h->parts[7].start;
+
+	/* Back up serdes power off value */
+	sds_conf_value = sw_r32(RTL838X_SDS_CFG_REG);
+	pr_info("SDS power down value: %x\n", sds_conf_value);
+
+	/* take serdes into reset */
+	i = 0;
+	while (rtl8380_sds_take_reset[2 * i]) {
+		sw_w32(rtl8380_sds_take_reset[2 * i + 1], rtl8380_sds_take_reset[2 * i]);
+		i++;
+		udelay(1000);
+	}
+
+	/* apply common serdes patch */
+	i = 0;
+	while (rtl8380_sds_common[2 * i]) {
+		sw_w32(rtl8380_sds_common[2 * i + 1], rtl8380_sds_common[2 * i]);
+		i++;
+		udelay(1000);
+	}
+
+	/* internal R/W enable */
+	sw_w32(3, RTL838X_INT_RW_CTRL);
+
+	/* SerDes ports 4 and 5 are FIBRE ports */
+	sw_w32_mask(0x7 | 0x38, 1 | (1 << 3), RTL838X_INT_MODE_CTRL);
+
+	/* SerDes module settings, SerDes 0-3 are QSGMII */
+	v = 0x6 << 25 | 0x6 << 20 | 0x6 << 15 | 0x6 << 10;
+	/* SerDes 4 and 5 are 1000BX FIBRE */
+	v |= 0x4 << 5 | 0x4;
+	sw_w32(v, RTL838X_SDS_MODE_SEL);
+
+	pr_info("PLL control register: %x\n", sw_r32(RTL838X_PLL_CML_CTRL));
+	sw_w32_mask(0xfffffff0, 0xaaaaaaaf & 0xf, RTL838X_PLL_CML_CTRL);
+	i = 0;
+	while (rtl8380_sds01_qsgmii_6275b[2 * i]) {
+		sw_w32(rtl8380_sds01_qsgmii_6275b[2 * i + 1],
+			rtl8380_sds01_qsgmii_6275b[2 * i]);
+		i++;
+	}
+
+	i = 0;
+	while (rtl8380_sds23_qsgmii_6275b[2 * i]) {
+		sw_w32(rtl8380_sds23_qsgmii_6275b[2 * i + 1], rtl8380_sds23_qsgmii_6275b[2 * i]);
+		i++;
+	}
+
+	i = 0;
+	while (rtl8380_sds4_fiber_6275b[2 * i]) {
+		sw_w32(rtl8380_sds4_fiber_6275b[2 * i + 1], rtl8380_sds4_fiber_6275b[2 * i]);
+		i++;
+	}
+
+	i = 0;
+	while (rtl8380_sds5_fiber_6275b[2 * i]) {
+		sw_w32(rtl8380_sds5_fiber_6275b[2 * i + 1], rtl8380_sds5_fiber_6275b[2 * i]);
+		i++;
+	}
+
+	i = 0;
+	while (rtl8380_sds_reset[2 * i]) {
+		sw_w32(rtl8380_sds_reset[2 * i + 1], rtl8380_sds_reset[2 * i]);
+		i++;
+	}
+
+	i = 0;
+	while (rtl8380_sds_release_reset[2 * i]) {
+		sw_w32(rtl8380_sds_release_reset[2 * i + 1], rtl8380_sds_release_reset[2 * i]);
+		i++;
+	}
+
+	pr_info("SDS power down value now: %x\n", sw_r32(RTL838X_SDS_CFG_REG));
+	sw_w32(sds_conf_value, RTL838X_SDS_CFG_REG);
+
+	pr_info("Configuration of SERDES done\n");
+	return 0;
+}
+
+static int rtl8390_configure_serdes(struct phy_device *phydev)
+{
+	phydev_info(phydev, "Detected internal RTL8390 SERDES\n");
+
+	/* In autoneg state, force link, set SR4_CFG_EN_LINK_FIB1G */
+	sw_w32_mask(0, 1 << 18, RTL839X_SDS12_13_XSG0 + 0x0a);
+
+	/* Disable EEE: Clear FRE16_EEE_RSG_FIB1G, FRE16_EEE_STD_FIB1G,
+	 * FRE16_C1_PWRSAV_EN_FIB1G, FRE16_C2_PWRSAV_EN_FIB1G
+	 * and FRE16_EEE_QUIET_FIB1G
+	 */
+	sw_w32_mask(0x1f << 10, 0, RTL839X_SDS12_13_XSG0 + 0xe0);
+
+	return 0;
+}
+
+static int rtl8214fc_phy_probe(struct phy_device *phydev)
+{
+	struct device *dev = &phydev->mdio.dev;
+	struct rtl838x_phy_priv *priv;
+	int addr = phydev->mdio.addr;
+
+	/* 839x has internal SerDes */
+	if (soc_info.id == 0x8393)
+		return -ENODEV;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->name = "RTL8214FC";
+
+	/* All base addresses of the PHYs start at multiples of 8 */
+	if (!(addr % 8)) {
+		/* Configuration must be done whil patching still possible */
+		return rtl8380_configure_rtl8214fc(phydev);
+	}
+	return 0;
+}
+
+static int rtl8214c_phy_probe(struct phy_device *phydev)
+{
+	struct device *dev = &phydev->mdio.dev;
+	struct rtl838x_phy_priv *priv;
+	int addr = phydev->mdio.addr;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->name = "RTL8214C";
+
+	/* All base addresses of the PHYs start at multiples of 8 */
+	if (!(addr % 8)) {
+		/* Configuration must be done whil patching still possible */
+		return rtl8380_configure_rtl8214c(phydev);
+	}
+	return 0;
+}
+
+static int rtl8218b_ext_phy_probe(struct phy_device *phydev)
+{
+	struct device *dev = &phydev->mdio.dev;
+	struct rtl838x_phy_priv *priv;
+	int addr = phydev->mdio.addr;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->name = "RTL8218B (external)";
+
+	/* All base addresses of the PHYs start at multiples of 8 */
+	if (!(addr % 8) && soc_info.family == RTL8380_FAMILY_ID) {
+		/* Configuration must be done while patching still possible */
+		return rtl8380_configure_ext_rtl8218b(phydev);
+	}
+	return 0;
+}
+
+static int rtl8218b_int_phy_probe(struct phy_device *phydev)
+{
+	struct device *dev = &phydev->mdio.dev;
+	struct rtl838x_phy_priv *priv;
+	int addr = phydev->mdio.addr;
+
+	if (soc_info.family != RTL8380_FAMILY_ID)
+		return -ENODEV;
+	if (addr >= 24)
+		return -ENODEV;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->name = "RTL8218B (internal)";
+
+	/* All base addresses of the PHYs start at multiples of 8 */
+	if (!(addr % 8)) {
+		/* Configuration must be done while patching still possible */
+		return rtl8380_configure_int_rtl8218b(phydev);
+	}
+	return 0;
+}
+
+static int rtl838x_serdes_probe(struct phy_device *phydev)
+{
+	struct device *dev = &phydev->mdio.dev;
+	struct rtl838x_phy_priv *priv;
+	int addr = phydev->mdio.addr;
+
+	if (soc_info.family != RTL8380_FAMILY_ID)
+		return -ENODEV;
+	if (addr < 24)
+		return -ENODEV;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->name = "RTL8380 Serdes";
+
+	/* On the RTL8380M, PHYs 24-27 connect to the internal SerDes */
+	if (soc_info.id == 0x8380) {
+		if (addr == 24)
+			return rtl8380_configure_serdes(phydev);
+		return 0;
+	}
+	return -ENODEV;
+}
+
+static int rtl8393_serdes_probe(struct phy_device *phydev)
+{
+	struct device *dev = &phydev->mdio.dev;
+	struct rtl838x_phy_priv *priv;
+	int addr = phydev->mdio.addr;
+
+	pr_info("%s: id: %d\n", __func__, addr);
+	if (soc_info.family != RTL8390_FAMILY_ID)
+		return -ENODEV;
+
+	if (addr < 24)
+		return -ENODEV;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->name = "RTL8393 Serdes";
+	return rtl8390_configure_serdes(phydev);
+}
+
+static int rtl8390_serdes_probe(struct phy_device *phydev)
+{
+	struct device *dev = &phydev->mdio.dev;
+	struct rtl838x_phy_priv *priv;
+	int addr = phydev->mdio.addr;
+
+	if (soc_info.family != RTL8390_FAMILY_ID)
+		return -ENODEV;
+
+	if (addr < 24)
+		return -ENODEV;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->name = "RTL8390 Serdes";
+	return rtl8390_configure_generic(phydev);
+}
+
+static struct phy_driver rtl83xx_phy_driver[] = {
+	{
+		PHY_ID_MATCH_MODEL(PHY_ID_RTL8214C),
+		.name		= "Realtek RTL8214C",
+		.features	= PHY_GBIT_FEATURES,
+		.match_phy_device = rtl8214c_match_phy_device,
+		.probe		= rtl8214c_phy_probe,
+		.suspend	= genphy_suspend,
+		.resume		= genphy_resume,
+		.set_loopback	= genphy_loopback,
+	},
+	{
+		PHY_ID_MATCH_MODEL(PHY_ID_RTL8214FC),
+		.name		= "Realtek RTL8214FC",
+		.features	= PHY_GBIT_FIBRE_FEATURES,
+		.match_phy_device = rtl8214fc_match_phy_device,
+		.probe		= rtl8214fc_phy_probe,
+		.suspend	= genphy_suspend,
+		.resume		= genphy_resume,
+		.set_loopback	= genphy_loopback,
+		.read_mmd	= rtl8218b_read_mmd,
+		.write_mmd	= rtl8218b_write_mmd,
+		.set_port	= rtl8214fc_set_port,
+		.get_port	= rtl8214fc_get_port,
+		.set_eee	= rtl8214fc_set_eee,
+		.get_eee	= rtl8214fc_get_eee,
+	},
+	{
+		PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_E),
+		.name		= "Realtek RTL8218B (external)",
+		.features	= PHY_GBIT_FEATURES,
+		.match_phy_device = rtl8218b_ext_match_phy_device,
+		.probe		= rtl8218b_ext_phy_probe,
+		.suspend	= genphy_suspend,
+		.resume		= genphy_resume,
+		.set_loopback	= genphy_loopback,
+		.read_mmd	= rtl8218b_read_mmd,
+		.write_mmd	= rtl8218b_write_mmd,
+		.set_eee	= rtl8218b_set_eee,
+		.get_eee	= rtl8218b_get_eee,
+	},
+	{
+		PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_I),
+		.name		= "Realtek RTL8218B (internal)",
+		.features	= PHY_GBIT_FEATURES,
+		.probe		= rtl8218b_int_phy_probe,
+		.suspend	= genphy_suspend,
+		.resume		= genphy_resume,
+		.set_loopback	= genphy_loopback,
+		.read_mmd	= rtl8218b_read_mmd,
+		.write_mmd	= rtl8218b_write_mmd,
+		.set_eee	= rtl8218b_set_eee,
+		.get_eee	= rtl8218b_get_eee,
+	},
+	{
+		PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_I),
+		.name		= "Realtek RTL8380 SERDES",
+		.features	= PHY_GBIT_FIBRE_FEATURES,
+		.probe		= rtl838x_serdes_probe,
+		.suspend	= genphy_suspend,
+		.resume		= genphy_resume,
+		.set_loopback	= genphy_loopback,
+		.read_mmd	= rtl8218b_read_mmd,
+		.write_mmd	= rtl8218b_write_mmd,
+		.read_status	= rtl8380_read_status,
+	},
+	{
+		PHY_ID_MATCH_MODEL(PHY_ID_RTL8393_I),
+		.name		= "Realtek RTL8393 SERDES",
+		.features	= PHY_GBIT_FIBRE_FEATURES,
+		.probe		= rtl8393_serdes_probe,
+		.suspend	= genphy_suspend,
+		.resume		= genphy_resume,
+		.set_loopback	= genphy_loopback,
+		.read_status	= rtl8393_read_status,
+	},
+	{
+		PHY_ID_MATCH_MODEL(PHY_ID_RTL8390_GENERIC),
+		.name		= "Realtek RTL8390 Generic",
+		.features	= PHY_GBIT_FIBRE_FEATURES,
+		.probe		= rtl8390_serdes_probe,
+		.suspend	= genphy_suspend,
+		.resume		= genphy_resume,
+		.set_loopback	= genphy_loopback,
+	}
+};
+
+module_phy_driver(rtl83xx_phy_driver);
+
+static struct mdio_device_id __maybe_unused rtl83xx_tbl[] = {
+	{ PHY_ID_MATCH_MODEL(PHY_ID_RTL8214FC) },
+	{ }
+};
+
+MODULE_DEVICE_TABLE(mdio, rtl83xx_tbl);
+
+MODULE_AUTHOR("B. Koblitz");
+MODULE_DESCRIPTION("RTL83xx PHY driver");
+MODULE_LICENSE("GPL");
diff --git a/target/linux/realtek/files-5.4/drivers/net/phy/rtl83xx-phy.h b/target/linux/realtek/files-5.4/drivers/net/phy/rtl83xx-phy.h
new file mode 100644
index 0000000000..7af35a3583
--- /dev/null
+++ b/target/linux/realtek/files-5.4/drivers/net/phy/rtl83xx-phy.h
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+// TODO: not really used
+struct rtl838x_phy_priv {
+	char *name;
+};
+
+struct __attribute__ ((__packed__)) part {
+	uint16_t start;
+	uint8_t wordsize;
+	uint8_t words;
+};
+
+struct __attribute__ ((__packed__)) fw_header {
+	uint32_t magic;
+	uint32_t phy;
+	uint32_t checksum;
+	uint32_t version;
+	struct part parts[10];
+};
+
+// TODO: fixed path?
+#define FIRMWARE_838X_8380_1	"rtl838x_phy/rtl838x_8380.fw"
+#define FIRMWARE_838X_8214FC_1	"rtl838x_phy/rtl838x_8214fc.fw"
+#define FIRMWARE_838X_8218b_1	"rtl838x_phy/rtl838x_8218b.fw"
+
+/* External RTL8218B and RTL8214FC IDs are identical */
+#define PHY_ID_RTL8214C		0x001cc942
+#define PHY_ID_RTL8214FC	0x001cc981
+#define PHY_ID_RTL8218B_E	0x001cc981
+#define PHY_ID_RTL8218B_I	0x001cca40
+#define PHY_ID_RTL8390_GENERIC	0x001ccab0
+#define PHY_ID_RTL8393_I	0x001c8393
+
+#define RTL839X_SDS12_13_XSG0			(0xB800)
+
+#define RTL838X_SDS_MODE_SEL			(0x0028)
+#define RTL838X_SDS_CFG_REG			(0x0034)
+#define RTL838X_INT_MODE_CTRL			(0x005c)
+#define RTL838X_DMY_REG31			(0x3b28)