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| author | Daniel Golle <daniel@makrotopia.org> | 2022-07-28 16:45:03 +0200 |
|---|---|---|
| committer | Daniel Golle <daniel@makrotopia.org> | 2022-07-28 16:45:19 +0200 |
| commit | a49212d762fb2635564cd3365651da51d0c535d9 (patch) | |
| tree | c38dbd0098ffd32194eaca80db10331eb8d3751b /target/linux/realtek/dts-5.10/rtl8382_hpe_1920-24g.dts | |
| parent | aeaa02afac6b7d55dd2b8175858b9799a24fb494 (diff) | |
| download | upstream-a49212d762fb2635564cd3365651da51d0c535d9.tar.gz upstream-a49212d762fb2635564cd3365651da51d0c535d9.tar.bz2 upstream-a49212d762fb2635564cd3365651da51d0c535d9.zip | |
Revert "realtek: remove support for HPE 1920 series"
This reverts commit a63aeaecf1f3387df020854c9b22a365207399ce.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Diffstat (limited to 'target/linux/realtek/dts-5.10/rtl8382_hpe_1920-24g.dts')
| -rw-r--r-- | target/linux/realtek/dts-5.10/rtl8382_hpe_1920-24g.dts | 68 |
1 files changed, 68 insertions, 0 deletions
diff --git a/target/linux/realtek/dts-5.10/rtl8382_hpe_1920-24g.dts b/target/linux/realtek/dts-5.10/rtl8382_hpe_1920-24g.dts new file mode 100644 index 0000000000..61781c708e --- /dev/null +++ b/target/linux/realtek/dts-5.10/rtl8382_hpe_1920-24g.dts @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "rtl8382_hpe_1920.dtsi" + +/ { + compatible = "hpe,1920-24g", "realtek,rtl838x-soc"; + model = "HPE 1920-24G (JG924A)"; +}; + +&mdio { + EXTERNAL_PHY(0) + EXTERNAL_PHY(1) + EXTERNAL_PHY(2) + EXTERNAL_PHY(3) + EXTERNAL_PHY(4) + EXTERNAL_PHY(5) + EXTERNAL_PHY(6) + EXTERNAL_PHY(7) +}; + +&switch0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + SWITCH_PORT(0, 1, qsgmii) + SWITCH_PORT(1, 2, qsgmii) + SWITCH_PORT(2, 3, qsgmii) + SWITCH_PORT(3, 4, qsgmii) + SWITCH_PORT(4, 5, qsgmii) + SWITCH_PORT(5, 6, qsgmii) + SWITCH_PORT(6, 7, qsgmii) + SWITCH_PORT(7, 8, qsgmii) + + SWITCH_PORT(8, 9, internal) + SWITCH_PORT(9, 10, internal) + SWITCH_PORT(10, 11, internal) + SWITCH_PORT(11, 12, internal) + SWITCH_PORT(12, 13, internal) + SWITCH_PORT(13, 14, internal) + SWITCH_PORT(14, 15, internal) + SWITCH_PORT(15, 16, internal) + + SWITCH_PORT(16, 17, qsgmii) + SWITCH_PORT(17, 18, qsgmii) + SWITCH_PORT(18, 19, qsgmii) + SWITCH_PORT(19, 20, qsgmii) + SWITCH_PORT(20, 21, qsgmii) + SWITCH_PORT(21, 22, qsgmii) + SWITCH_PORT(22, 23, qsgmii) + SWITCH_PORT(23, 24, qsgmii) + + SWITCH_PORT(24, 25, qsgmii) + SWITCH_PORT(25, 26, qsgmii) + SWITCH_PORT(26, 27, qsgmii) + SWITCH_PORT(27, 28, qsgmii) + + port@28 { + ethernet = <ðernet0>; + reg = <28>; + phy-mode = "internal"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; +}; |