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authorGabor Juhos <juhosg@openwrt.org>2009-10-25 07:10:14 +0000
committerGabor Juhos <juhosg@openwrt.org>2009-10-25 07:10:14 +0000
commitd681005ce303bee73a426025b4ffe9510e382837 (patch)
treec5937ad7f43c48e4c25d26dfa5de3c0135498b7d /target/linux/ramips
parentebde2e4c90d550403f1a51955bbee7ac739109bd (diff)
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ramips: modify {read,write}_config helpers
SVN-Revision: 18141
Diffstat (limited to 'target/linux/ramips')
-rw-r--r--target/linux/ramips/files/arch/mips/pci/pci-rt288x.c32
1 files changed, 15 insertions, 17 deletions
diff --git a/target/linux/ramips/files/arch/mips/pci/pci-rt288x.c b/target/linux/ramips/files/arch/mips/pci/pci-rt288x.c
index 84a9735458..475009cdde 100644
--- a/target/linux/ramips/files/arch/mips/pci/pci-rt288x.c
+++ b/target/linux/ramips/files/arch/mips/pci/pci-rt288x.c
@@ -146,29 +146,28 @@ static struct pci_controller rt2880_pci_controller = {
.io_resource = &rt2880_pci_mem_resource,
};
-static inline void read_config(unsigned long bus, unsigned long dev,
- unsigned long func, unsigned long reg,
- unsigned long *val)
+static inline u32 rt2880_pci_read_u32(unsigned long reg)
{
- unsigned long address;
unsigned long flags;
+ u32 address;
+ u32 ret;
- address = rt2880_pci_get_cfgaddr(bus, dev, func, reg);
+ address = rt2880_pci_get_cfgaddr(0, 0, 0, reg);
spin_lock_irqsave(&rt2880_pci_lock, flags);
rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
- *val = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
+ ret = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
spin_unlock_irqrestore(&rt2880_pci_lock, flags);
+
+ return ret;
}
-static inline void write_config(unsigned long bus, unsigned long dev,
- unsigned long func, unsigned long reg,
- unsigned long val)
+static inline void rt2880_pci_write_u32(unsigned long reg, u32 val)
{
- unsigned long address;
unsigned long flags;
+ u32 address;
- address = rt2880_pci_get_cfgaddr(bus, dev, func, reg);
+ address = rt2880_pci_get_cfgaddr(0, 0, 0, reg);
spin_lock_irqsave(&rt2880_pci_lock, flags);
rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
@@ -179,7 +178,6 @@ static inline void write_config(unsigned long bus, unsigned long dev,
int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
u16 cmd;
- unsigned long val;
int irq = -1;
if (dev->bus->number != 0)
@@ -187,8 +185,8 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
switch (PCI_SLOT(dev->devfn)) {
case 0x00:
- write_config(0, 0, 0, PCI_BASE_ADDRESS_0, 0x08000000);
- read_config(0, 0, 0, PCI_BASE_ADDRESS_0, &val);
+ rt2880_pci_write_u32(PCI_BASE_ADDRESS_0, 0x08000000);
+ (void) rt2880_pci_read_u32(PCI_BASE_ADDRESS_0);
break;
case 0x11:
irq = RT288X_CPU_IRQ_PCI;
@@ -214,7 +212,6 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
static int __init rt2880_pci_init(void)
{
- unsigned long val = 0;
int i;
rt2880_pci_base = ioremap_nocache(RT2880_PCI_BASE, PAGE_SIZE);
@@ -231,8 +228,9 @@ static int __init rt2880_pci_init(void)
rt2880_pci_reg_write(0x00800001, RT2880_PCI_REG_CLASS);
rt2880_pci_reg_write(0x28801814, RT2880_PCI_REG_SUBID);
rt2880_pci_reg_write(0x000c0000, RT2880_PCI_REG_PCIMSK_ADDR);
- write_config(0, 0, 0, PCI_BASE_ADDRESS_0, 0x08000000);
- read_config(0, 0, 0, PCI_BASE_ADDRESS_0, &val);
+
+ rt2880_pci_write_u32(PCI_BASE_ADDRESS_0, 0x08000000);
+ (void) rt2880_pci_read_u32(PCI_BASE_ADDRESS_0);
register_pci_controller(&rt2880_pci_controller);
return 0;