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| author | Shiji Yang <yangshiji66@qq.com> | 2023-06-17 19:30:59 +0800 |
|---|---|---|
| committer | Nick Hainke <vincent@systemli.org> | 2023-07-30 13:09:23 +0200 |
| commit | 1f818b09f8ae1cbb4a2ae7ddaccaa9ce0c12ca93 (patch) | |
| tree | 35d4de6bee938f6a0e090c13d249f3fda0a4f84b /target/linux/ramips/rt305x | |
| parent | 8cacf2bda8009f07715a9617be6b26e53c5443bd (diff) | |
| download | upstream-1f818b09f8ae1cbb4a2ae7ddaccaa9ce0c12ca93.tar.gz upstream-1f818b09f8ae1cbb4a2ae7ddaccaa9ce0c12ca93.tar.bz2 upstream-1f818b09f8ae1cbb4a2ae7ddaccaa9ce0c12ca93.zip | |
ramips: add proper system clock and reset driver support for legacy SoCs
This series of upstream patches properly implement a clock and reset
driver for old ralink SoCs[1]. And it includes some related fixes[2] and
improvements[3][4]. All patches have been merged into linux-next. They
will be part of upcoming Linux 6.5. In order to switch to the new system
controller driver, all clocks and resets properties in SoC dtsi have been
updated, and kernel symbol "CONFIG_CLK_MTMIPS" have been added to the
kernel config files.
[1] https://lore.kernel.org/all/20230619040941.1340372-1-sergio.paracuellos@gmail.com
[2] https://lore.kernel.org/all/20230622-mips-ralink-clk-wuninitialized-v1-1-ea9041240d10@kernel.org
[3] https://lore.kernel.org/all/OSYP286MB03120BABB25900E113ED42B7BC5CA@OSYP286MB0312.JPNP286.PROD.OUTLOOK.COM
[4] https://lore.kernel.org/all/TYAP286MB03151148AF8C054621DD55C3BC23A@TYAP286MB0315.JPNP286.PROD.OUTLOOK.COM
Tested on Motorola MWR03 (MT7628)
Tested on Haier HW-L1W (MT7620)
Signed-off-by: Shiji Yang <yangshiji66@qq.com>
Diffstat (limited to 'target/linux/ramips/rt305x')
| -rw-r--r-- | target/linux/ramips/rt305x/config-5.15 | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/target/linux/ramips/rt305x/config-5.15 b/target/linux/ramips/rt305x/config-5.15 index fccc7370a50..5af80adca65 100644 --- a/target/linux/ramips/rt305x/config-5.15 +++ b/target/linux/ramips/rt305x/config-5.15 @@ -8,6 +8,7 @@ CONFIG_CEVT_R4K=y CONFIG_CEVT_SYSTICK_QUIRK=y CONFIG_CLKEVT_RT3352=y CONFIG_CLKSRC_MMIO=y +CONFIG_CLK_MTMIPS=y CONFIG_CLONE_BACKWARDS=y CONFIG_CMDLINE="rootfstype=squashfs,jffs2" CONFIG_CMDLINE_BOOL=y @@ -19,7 +20,7 @@ CONFIG_CPU_HAS_DIEI=y CONFIG_CPU_HAS_PREFETCH=y CONFIG_CPU_HAS_RIXI=y CONFIG_CPU_HAS_SYNC=y -CONFIG_CPU_LITTLE_ENDIAN=y` +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_MIPS32=y # CONFIG_CPU_MIPS32_R1 is not set CONFIG_CPU_MIPS32_R2=y |