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authorIlya Lipnitskiy <ilya.lipnitskiy@gmail.com>2021-02-19 18:59:29 -0800
committerAdrian Schmutzler <freifunk@adrianschmutzler.de>2021-03-06 11:24:12 +0100
commiteda836e390af2e9f08618dde8e06af851e732a47 (patch)
tree112baa14e8058067d164a92b81b279a10d1974ce /target/linux/ramips/patches-5.10/999-fix-pci-init-mt7620.patch
parenta9966793e81e1c0f48478ac42ea5bf284927c817 (diff)
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ramips: 5.10: copy patches from 5.4
Strict copy, no changes made. Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
Diffstat (limited to 'target/linux/ramips/patches-5.10/999-fix-pci-init-mt7620.patch')
-rw-r--r--target/linux/ramips/patches-5.10/999-fix-pci-init-mt7620.patch21
1 files changed, 21 insertions, 0 deletions
diff --git a/target/linux/ramips/patches-5.10/999-fix-pci-init-mt7620.patch b/target/linux/ramips/patches-5.10/999-fix-pci-init-mt7620.patch
new file mode 100644
index 0000000000..7c00d4c9ae
--- /dev/null
+++ b/target/linux/ramips/patches-5.10/999-fix-pci-init-mt7620.patch
@@ -0,0 +1,21 @@
+--- a/arch/mips/pci/pci-mt7620.c
++++ b/arch/mips/pci/pci-mt7620.c
+@@ -32,6 +32,7 @@
+ #define PPLL_CFG1 0x9c
+
+ #define PPLL_DRV 0xa0
++#define PPLL_LD BIT(23)
+ #define PDRV_SW_SET BIT(31)
+ #define LC_CKDRVPD BIT(19)
+ #define LC_CKDRVOHZ BIT(18)
+@@ -239,8 +240,8 @@ static int mt7620_pci_hw_init(struct pla
+ rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
+ mdelay(100);
+
+- if (!(rt_sysc_r32(PPLL_CFG1) & PDRV_SW_SET)) {
+- dev_err(&pdev->dev, "MT7620 PPLL unlock\n");
++ if (!(rt_sysc_r32(PPLL_CFG1) & PPLL_LD)) {
++ dev_err(&pdev->dev, "MT7620 PPLL is unlocked, aborting init\n");
+ reset_control_assert(rstpcie0);
+ rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
+ return -1;