aboutsummaryrefslogtreecommitdiffstats
path: root/target/linux/ramips/patches-3.9/0139-MIPS-ralink-add-spi-clock-definition-to-mt7620a.patch
diff options
context:
space:
mode:
authorJohn Crispin <john@openwrt.org>2013-07-22 13:52:32 +0000
committerJohn Crispin <john@openwrt.org>2013-07-22 13:52:32 +0000
commit5525b2136e90fcfc8823b519fa4aa2499f0120ba (patch)
treee614278bc48faf84a9ff7de35d9de77b7e630fb6 /target/linux/ramips/patches-3.9/0139-MIPS-ralink-add-spi-clock-definition-to-mt7620a.patch
parentec6954e64e7cd7e503b62ab73381cfa0adce24fc (diff)
downloadupstream-5525b2136e90fcfc8823b519fa4aa2499f0120ba.tar.gz
upstream-5525b2136e90fcfc8823b519fa4aa2499f0120ba.tar.bz2
upstream-5525b2136e90fcfc8823b519fa4aa2499f0120ba.zip
ralink: set v3.10 as default
Signed-off-by: John Crispin <blogic@openwrt.org> SVN-Revision: 37497
Diffstat (limited to 'target/linux/ramips/patches-3.9/0139-MIPS-ralink-add-spi-clock-definition-to-mt7620a.patch')
-rw-r--r--target/linux/ramips/patches-3.9/0139-MIPS-ralink-add-spi-clock-definition-to-mt7620a.patch20
1 files changed, 0 insertions, 20 deletions
diff --git a/target/linux/ramips/patches-3.9/0139-MIPS-ralink-add-spi-clock-definition-to-mt7620a.patch b/target/linux/ramips/patches-3.9/0139-MIPS-ralink-add-spi-clock-definition-to-mt7620a.patch
deleted file mode 100644
index fb0cd7bcdb..0000000000
--- a/target/linux/ramips/patches-3.9/0139-MIPS-ralink-add-spi-clock-definition-to-mt7620a.patch
+++ /dev/null
@@ -1,20 +0,0 @@
-From 17d26ed75f0981cdc497f9062aec5f66d3c44d88 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Thu, 23 May 2013 18:46:25 +0200
-Subject: [PATCH 139/164] MIPS: ralink: add spi clock definition to mt7620a
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/mt7620.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/arch/mips/ralink/mt7620.c
-+++ b/arch/mips/ralink/mt7620.c
-@@ -183,6 +183,7 @@ void __init ralink_clk_init(void)
- ralink_clk_add("cpu", cpu_rate);
- ralink_clk_add("10000100.timer", 40000000);
- ralink_clk_add("10000500.uart", 40000000);
-+ ralink_clk_add("10000b00.spi", 40000000);
- ralink_clk_add("10000c00.uartlite", 40000000);
- }
-